blob: cdc2a7b2ef3237c29fa36b78df9d72e759c54e62 [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -07001/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
7 #size-cells = <0>;
8
Simon Glass00606d72014-07-23 06:55:03 -06009 aliases {
10 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -060011 eth0 = "/eth@10002000";
12 eth5 = &eth_5;
Simon Glass9cc36a22015-01-25 08:27:05 -070013 i2c0 = "/i2c@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020014 pci0 = &pci;
Simon Glass52d3bc52015-05-22 15:42:17 -060015 rtc0 = &rtc_0;
16 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060017 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020018 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070019 testbus3 = "/some-bus";
20 testfdt0 = "/some-bus/c-test@0";
21 testfdt1 = "/some-bus/c-test@1";
22 testfdt3 = "/b-test";
23 testfdt5 = "/some-bus/c-test@5";
24 testfdt8 = "/a-test";
Simon Glasse00cb222015-03-25 12:23:05 -060025 usb0 = &usb_0;
26 usb1 = &usb_1;
27 usb2 = &usb_2;
Simon Glass00606d72014-07-23 06:55:03 -060028 };
29
Simon Glass2e7d35d2014-02-26 15:59:21 -070030 a-test {
31 reg = <0>;
32 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -060033 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070034 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -060035 u-boot,dm-pre-reloc;
Simon Glass3669e0e2015-01-05 20:05:29 -070036 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
37 <0>, <&gpio_a 12>;
38 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
39 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
40 <&gpio_b 9 0xc 3 2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070041 };
42
43 junk {
44 reg = <1>;
45 compatible = "not,compatible";
46 };
47
48 no-compatible {
49 reg = <2>;
50 };
51
52 b-test {
53 reg = <3>;
54 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -060055 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070056 ping-add = <3>;
57 };
58
59 some-bus {
60 #address-cells = <1>;
61 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -060062 compatible = "denx,u-boot-test-bus";
Simon Glass5a66a8f2014-07-23 06:55:12 -060063 reg = <3>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -060064 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070065 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -060066 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -070067 compatible = "denx,u-boot-fdt-test";
68 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -060069 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070070 ping-add = <5>;
71 };
Simon Glass1ca7e202014-07-23 06:55:18 -060072 c-test@0 {
73 compatible = "denx,u-boot-fdt-test";
74 reg = <0>;
75 ping-expect = <6>;
76 ping-add = <6>;
77 };
78 c-test@1 {
79 compatible = "denx,u-boot-fdt-test";
80 reg = <1>;
81 ping-expect = <7>;
82 ping-add = <7>;
83 };
Simon Glass2e7d35d2014-02-26 15:59:21 -070084 };
85
86 d-test {
Simon Glass5a66a8f2014-07-23 06:55:12 -060087 reg = <3>;
88 ping-expect = <6>;
89 ping-add = <6>;
90 compatible = "google,another-fdt-test";
91 };
92
93 e-test {
94 reg = <3>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -060095 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070096 ping-add = <6>;
97 compatible = "google,another-fdt-test";
98 };
99
Simon Glass9cc36a22015-01-25 08:27:05 -0700100 f-test {
101 compatible = "denx,u-boot-fdt-test";
102 };
103
104 g-test {
105 compatible = "denx,u-boot-fdt-test";
106 };
107
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600108 clk@0 {
109 compatible = "sandbox,clk";
110 };
111
Simon Glass171e9912015-05-22 15:42:15 -0600112 eth@10002000 {
113 compatible = "sandbox,eth";
114 reg = <0x10002000 0x1000>;
115 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x00>;
116 };
117
118 eth_5: eth@10003000 {
119 compatible = "sandbox,eth";
120 reg = <0x10003000 0x1000>;
121 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x11>;
122 };
123
124 eth@10004000 {
125 compatible = "sandbox,eth";
126 reg = <0x10004000 0x1000>;
127 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x22>;
128 };
129
Simon Glass0ae0cb72014-10-13 23:42:11 -0600130 gpio_a: base-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700131 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700132 gpio-controller;
133 #gpio-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700134 gpio-bank-name = "a";
135 num-gpios = <20>;
136 };
137
Simon Glass3669e0e2015-01-05 20:05:29 -0700138 gpio_b: extra-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700139 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700140 gpio-controller;
141 #gpio-cells = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700142 gpio-bank-name = "b";
143 num-gpios = <10>;
144 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600145
Simon Glassecc2ed52014-12-10 08:55:55 -0700146 i2c@0 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 reg = <0>;
150 compatible = "sandbox,i2c";
151 clock-frequency = <100000>;
152 eeprom@2c {
153 reg = <0x2c>;
154 compatible = "i2c-eeprom";
155 emul {
156 compatible = "sandbox,i2c-eeprom";
157 sandbox,filename = "i2c.bin";
158 sandbox,size = <256>;
159 };
160 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200161
Simon Glass52d3bc52015-05-22 15:42:17 -0600162 rtc_0: rtc@43 {
163 reg = <0x43>;
164 compatible = "sandbox-rtc";
165 emul {
166 compatible = "sandbox,i2c-rtc";
167 };
168 };
169
170 rtc_1: rtc@61 {
171 reg = <0x61>;
172 compatible = "sandbox-rtc";
173 emul {
174 compatible = "sandbox,i2c-rtc";
175 };
176 };
177
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200178 sandbox_pmic: sandbox_pmic {
179 reg = <0x40>;
180 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700181 };
182
Simon Glassd3b7ff12015-03-05 12:25:34 -0700183 pci: pci-controller {
184 compatible = "sandbox,pci";
185 device_type = "pci";
186 #address-cells = <3>;
187 #size-cells = <2>;
188 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
189 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
190 pci@1f,0 {
191 compatible = "pci-generic";
192 reg = <0xf800 0 0 0 0>;
193 emul@1f,0 {
194 compatible = "sandbox,swap-case";
195 };
196 };
197 };
198
Simon Glass64ce0ca2015-07-06 12:54:31 -0600199 ram {
200 compatible = "sandbox,ram";
201 };
202
Simon Glass5010d982015-07-06 12:54:29 -0600203 reset@0 {
204 compatible = "sandbox,warm-reset";
205 };
206
207 reset@1 {
208 compatible = "sandbox,reset";
209 };
210
Simon Glass0ae0cb72014-10-13 23:42:11 -0600211 spi@0 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 reg = <0>;
215 compatible = "sandbox,spi";
216 cs-gpios = <0>, <&gpio_a 0>;
217 spi.bin@0 {
218 reg = <0>;
219 compatible = "spansion,m25p16", "spi-flash";
220 spi-max-frequency = <40000000>;
221 sandbox,filename = "spi.bin";
222 };
223 };
224
Simon Glass171e9912015-05-22 15:42:15 -0600225 uart0: serial {
226 compatible = "sandbox,serial";
227 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500228 };
229
Simon Glasse00cb222015-03-25 12:23:05 -0600230 usb_0: usb@0 {
231 compatible = "sandbox,usb";
232 status = "disabled";
233 hub {
234 compatible = "sandbox,usb-hub";
235 #address-cells = <1>;
236 #size-cells = <0>;
237 flash-stick {
238 reg = <0>;
239 compatible = "sandbox,usb-flash";
240 };
241 };
242 };
243
244 usb_1: usb@1 {
245 compatible = "sandbox,usb";
246 hub {
247 compatible = "usb-hub";
248 usb,device-class = <9>;
249 hub-emul {
250 compatible = "sandbox,usb-hub";
251 #address-cells = <1>;
252 #size-cells = <0>;
253 flash-stick {
254 reg = <0>;
255 compatible = "sandbox,usb-flash";
256 sandbox,filepath = "testflash.bin";
257 };
258
259 };
260 };
261 };
262
263 usb_2: usb@2 {
264 compatible = "sandbox,usb";
265 status = "disabled";
266 };
267
Simon Glass2e7d35d2014-02-26 15:59:21 -0700268};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200269
270#include "sandbox_pmic.dtsi"