Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Fabio Estevam | 7dd6545 | 2012-09-24 08:09:33 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2012 Freescale Semiconductor, Inc. |
| 4 | * |
Otavio Salvador | 903e779 | 2012-10-02 09:22:10 +0000 | [diff] [blame] | 5 | * Configuration settings for the Freescale i.MX6Q SabreAuto board. |
Fabio Estevam | 7dd6545 | 2012-09-24 08:09:33 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
Vanessa Maegima | d7c1150 | 2017-06-29 09:33:46 -0300 | [diff] [blame] | 8 | #ifndef __MX6SABREAUTO_CONFIG_H |
| 9 | #define __MX6SABREAUTO_CONFIG_H |
Fabio Estevam | 7dd6545 | 2012-09-24 08:09:33 +0000 | [diff] [blame] | 10 | |
Vanessa Maegima | 823dff9 | 2017-06-29 09:33:45 -0300 | [diff] [blame] | 11 | #ifdef CONFIG_SPL |
| 12 | #include "imx6_spl.h" |
| 13 | #endif |
| 14 | |
Fabio Estevam | 7dd6545 | 2012-09-24 08:09:33 +0000 | [diff] [blame] | 15 | #define CONFIG_MACH_TYPE 3529 |
| 16 | #define CONFIG_MXC_UART_BASE UART4_BASE |
Simon Glass | 12ca05a | 2016-10-17 20:12:39 -0600 | [diff] [blame] | 17 | #define CONSOLE_DEV "ttymxc3" |
Fabio Estevam | 7dd6545 | 2012-09-24 08:09:33 +0000 | [diff] [blame] | 18 | |
Knut Wohlrab | 73448b1 | 2013-01-21 23:11:21 +0000 | [diff] [blame] | 19 | /* USB Configs */ |
Troy Kisky | d1a5286 | 2013-10-10 15:27:59 -0700 | [diff] [blame] | 20 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
| 21 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ |
Knut Wohlrab | 73448b1 | 2013-01-21 23:11:21 +0000 | [diff] [blame] | 22 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
| 23 | #define CONFIG_MXC_USB_FLAGS 0 |
| 24 | |
Ye.Li | 8fe280f | 2014-10-30 18:53:49 +0800 | [diff] [blame] | 25 | #define CONFIG_PCA953X |
| 26 | #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } |
| 27 | |
Pierre Aubert | c174797 | 2013-06-04 09:00:15 +0200 | [diff] [blame] | 28 | #include "mx6sabre_common.h" |
Otavio Salvador | 51535d9 | 2012-09-26 11:37:01 +0000 | [diff] [blame] | 29 | |
Diego Dorta | 07f6ddb | 2017-07-07 15:38:34 -0300 | [diff] [blame] | 30 | /* Falcon Mode */ |
| 31 | #ifdef CONFIG_SPL_OS_BOOT |
| 32 | #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" |
| 33 | #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" |
Diego Dorta | 07f6ddb | 2017-07-07 15:38:34 -0300 | [diff] [blame] | 34 | #define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 |
Diego Dorta | 07f6ddb | 2017-07-07 15:38:34 -0300 | [diff] [blame] | 35 | |
| 36 | /* Falcon Mode - MMC support: args@1MB kernel@2MB */ |
| 37 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ |
| 38 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) |
| 39 | #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ |
| 40 | #endif |
| 41 | |
Fabio Estevam | ca62e5d | 2017-07-10 15:59:11 -0300 | [diff] [blame] | 42 | #ifdef CONFIG_MTD_NOR_FLASH |
Fabio Estevam | cdbdde3 | 2014-11-14 11:27:23 -0200 | [diff] [blame] | 43 | #define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR |
| 44 | #define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) |
| 45 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 46 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
Fabio Estevam | cdbdde3 | 2014-11-14 11:27:23 -0200 | [diff] [blame] | 47 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
Fabio Estevam | 565cfcf | 2016-12-15 16:00:11 -0200 | [diff] [blame] | 48 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
Fabio Estevam | ca62e5d | 2017-07-10 15:59:11 -0300 | [diff] [blame] | 49 | #endif |
Fabio Estevam | cdbdde3 | 2014-11-14 11:27:23 -0200 | [diff] [blame] | 50 | |
Shawn Guo | de7d02a | 2012-12-30 14:14:59 +0000 | [diff] [blame] | 51 | #define CONFIG_SYS_FSL_USDHC_NUM 2 |
Shawn Guo | de7d02a | 2012-12-30 14:14:59 +0000 | [diff] [blame] | 52 | |
Renato Frias | 1957816 | 2013-05-13 18:01:12 +0000 | [diff] [blame] | 53 | /* I2C Configs */ |
trem | b089d03 | 2013-09-21 18:13:36 +0200 | [diff] [blame] | 54 | #define CONFIG_SYS_I2C |
| 55 | #define CONFIG_SYS_I2C_MXC |
Albert ARIBAUD \\(3ADEV\\) | 03544c6 | 2015-09-21 22:43:38 +0200 | [diff] [blame] | 56 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
| 57 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ |
York Sun | f8cb101 | 2015-03-20 10:20:40 -0700 | [diff] [blame] | 58 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
Renato Frias | 1957816 | 2013-05-13 18:01:12 +0000 | [diff] [blame] | 59 | #define CONFIG_SYS_I2C_SPEED 100000 |
| 60 | |
Ye.Li | 83bb321 | 2014-11-12 14:02:05 +0800 | [diff] [blame] | 61 | /* NAND stuff */ |
Ye.Li | 83bb321 | 2014-11-12 14:02:05 +0800 | [diff] [blame] | 62 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 63 | #define CONFIG_SYS_NAND_BASE 0x40000000 |
| 64 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
| 65 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
| 66 | |
| 67 | /* DMA stuff, needed for GPMI/MXS NAND support */ |
Ye.Li | 83bb321 | 2014-11-12 14:02:05 +0800 | [diff] [blame] | 68 | |
Ye.Li | 593243d | 2014-11-06 16:29:02 +0800 | [diff] [blame] | 69 | /* PMIC */ |
| 70 | #define CONFIG_POWER |
| 71 | #define CONFIG_POWER_I2C |
| 72 | #define CONFIG_POWER_PFUZE100 |
| 73 | #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 |
| 74 | |
Vanessa Maegima | d7c1150 | 2017-06-29 09:33:46 -0300 | [diff] [blame] | 75 | #endif /* __MX6SABREAUTO_CONFIG_H */ |