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wdenke887afc2002-08-27 09:44:07 +00001/*
2 * (C) Copyright 2000
3 * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <command.h>
wdenke887afc2002-08-27 09:44:07 +000026#if defined(CONFIG_8xx)
27#include <mpc8xx.h>
Niklaus Giger78d2a642009-10-04 20:04:21 +020028#elif defined (CONFIG_4xx)
29extern void ppc4xx_reginfo(void);
wdenk0db5bca2003-03-31 17:27:09 +000030#elif defined (CONFIG_5xx)
31#include <mpc5xx.h>
wdenk56523f12004-07-11 17:40:54 +000032#elif defined (CONFIG_MPC5200)
33#include <mpc5xxx.h>
Becky Bruce4f93f8b2008-01-23 16:31:06 -060034#elif defined (CONFIG_MPC86xx)
35extern void mpc86xx_reginfo(void);
Becky Bruce199e2622010-06-17 11:37:25 -050036#elif defined(CONFIG_MPC85xx)
37extern void mpc85xx_reginfo(void);
wdenke887afc2002-08-27 09:44:07 +000038#endif
Jon Loeliger65c450b2007-06-11 19:01:54 -050039
Kim Phillips088f1b12012-10-29 13:34:31 +000040static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
41 char * const argv[])
wdenke887afc2002-08-27 09:44:07 +000042{
43#if defined(CONFIG_8xx)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
wdenke887afc2002-08-27 09:44:07 +000045 volatile memctl8xx_t *memctl = &immap->im_memctl;
46 volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
47 volatile sit8xx_t *timers = &immap->im_sit;
48
49 /* Hopefully more PowerPC knowledgable people will add code to display
50 * other useful registers
51 */
52
wdenk4b9206e2004-03-23 22:14:11 +000053 printf ("\nSystem Configuration registers\n"
wdenke887afc2002-08-27 09:44:07 +000054
wdenk4b9206e2004-03-23 22:14:11 +000055 "\tIMMR\t0x%08X\n", get_immr(0));
wdenke887afc2002-08-27 09:44:07 +000056
57 printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
58 printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
59
60 printf("\tSWT\t0x%08X", sysconf->sc_swt);
61 printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
62
63 printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
64 sysconf->sc_sipend, sysconf->sc_simask);
65 printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
66 sysconf->sc_siel, sysconf->sc_sivec);
67 printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
68 sysconf->sc_tesr, sysconf->sc_sdcr);
69
wdenk4b9206e2004-03-23 22:14:11 +000070 printf ("Memory Controller Registers\n"
wdenke887afc2002-08-27 09:44:07 +000071
wdenk4b9206e2004-03-23 22:14:11 +000072 "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
wdenke887afc2002-08-27 09:44:07 +000073 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
74 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
75 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
76 printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
77 printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
78 printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
79 printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
wdenk4b9206e2004-03-23 22:14:11 +000080 printf ("\n"
81 "\tmamr\t0x%08X\tmbmr\t0x%08X \n",
wdenke887afc2002-08-27 09:44:07 +000082 memctl->memc_mamr, memctl->memc_mbmr );
83 printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
84 memctl->memc_mstat, memctl->memc_mptpr );
85 printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
86
wdenk4b9206e2004-03-23 22:14:11 +000087 printf ("\nSystem Integration Timers\n"
88 "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
wdenke887afc2002-08-27 09:44:07 +000089 timers->sit_tbscr, timers->sit_rtcsc);
90 printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
91
92 /*
93 * May be some CPM info here?
94 */
95
Niklaus Giger78d2a642009-10-04 20:04:21 +020096#elif defined (CONFIG_4xx)
97 ppc4xx_reginfo();
wdenk0db5bca2003-03-31 17:27:09 +000098#elif defined(CONFIG_5xx)
wdenke887afc2002-08-27 09:44:07 +000099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
wdenk0db5bca2003-03-31 17:27:09 +0000101 volatile memctl5xx_t *memctl = &immap->im_memctl;
102 volatile sysconf5xx_t *sysconf = &immap->im_siu_conf;
103 volatile sit5xx_t *timers = &immap->im_sit;
104 volatile car5xx_t *car = &immap->im_clkrst;
105 volatile uimb5xx_t *uimb = &immap->im_uimb;
106
wdenk4b9206e2004-03-23 22:14:11 +0000107 puts ("\nSystem Configuration registers\n");
wdenk0db5bca2003-03-31 17:27:09 +0000108 printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
109 printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
110 printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
111 printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
112 printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);
113
wdenk4b9206e2004-03-23 22:14:11 +0000114 puts ("\nMemory Controller Registers\n");
wdenk0db5bca2003-03-31 17:27:09 +0000115 printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
116 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
117 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
118 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
119 printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
120 printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);
121
wdenk4b9206e2004-03-23 22:14:11 +0000122 puts ("\nSystem Integration Timers\n");
wdenk0db5bca2003-03-31 17:27:09 +0000123 printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
124 printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
125
wdenk4b9206e2004-03-23 22:14:11 +0000126 puts ("\nClocks and Reset\n");
wdenk0db5bca2003-03-31 17:27:09 +0000127 printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);
128
wdenk4b9206e2004-03-23 22:14:11 +0000129 puts ("\nU-Bus to IMB3 Bus Interface\n");
wdenk0db5bca2003-03-31 17:27:09 +0000130 printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
wdenk4b9206e2004-03-23 22:14:11 +0000131 puts ("\n\n");
wdenk56523f12004-07-11 17:40:54 +0000132
133#elif defined(CONFIG_MPC5200)
134 puts ("\nMPC5200 registers\n");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135 printf ("MBAR=%08x\n", CONFIG_SYS_MBAR);
wdenk56523f12004-07-11 17:40:54 +0000136 puts ("Memory map registers\n");
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200137 printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000138 *(volatile ulong*)MPC5XXX_CS0_START,
139 *(volatile ulong*)MPC5XXX_CS0_STOP,
140 *(volatile ulong*)MPC5XXX_CS0_CFG,
141 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200142 printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000143 *(volatile ulong*)MPC5XXX_CS1_START,
144 *(volatile ulong*)MPC5XXX_CS1_STOP,
145 *(volatile ulong*)MPC5XXX_CS1_CFG,
146 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200147 printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000148 *(volatile ulong*)MPC5XXX_CS2_START,
149 *(volatile ulong*)MPC5XXX_CS2_STOP,
150 *(volatile ulong*)MPC5XXX_CS2_CFG,
151 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200152 printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000153 *(volatile ulong*)MPC5XXX_CS3_START,
154 *(volatile ulong*)MPC5XXX_CS3_STOP,
155 *(volatile ulong*)MPC5XXX_CS3_CFG,
156 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200157 printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000158 *(volatile ulong*)MPC5XXX_CS4_START,
159 *(volatile ulong*)MPC5XXX_CS4_STOP,
160 *(volatile ulong*)MPC5XXX_CS4_CFG,
161 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200162 printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000163 *(volatile ulong*)MPC5XXX_CS5_START,
164 *(volatile ulong*)MPC5XXX_CS5_STOP,
165 *(volatile ulong*)MPC5XXX_CS5_CFG,
166 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200167 printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000168 *(volatile ulong*)MPC5XXX_CS6_START,
169 *(volatile ulong*)MPC5XXX_CS6_STOP,
170 *(volatile ulong*)MPC5XXX_CS6_CFG,
171 (*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200172 printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000173 *(volatile ulong*)MPC5XXX_CS7_START,
174 *(volatile ulong*)MPC5XXX_CS7_STOP,
175 *(volatile ulong*)MPC5XXX_CS7_CFG,
176 (*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200177 printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000178 *(volatile ulong*)MPC5XXX_BOOTCS_START,
179 *(volatile ulong*)MPC5XXX_BOOTCS_STOP,
180 *(volatile ulong*)MPC5XXX_BOOTCS_CFG,
181 (*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200182 printf ("\tSDRAMCS0: %08lX\n",
wdenk56523f12004-07-11 17:40:54 +0000183 *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200184 printf ("\tSDRAMCS1: %08lX\n",
wdenk56523f12004-07-11 17:40:54 +0000185 *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600186#elif defined(CONFIG_MPC86xx)
187 mpc86xx_reginfo();
Mike Frysinger97c26e02008-02-04 19:26:56 -0500188
Becky Bruce199e2622010-06-17 11:37:25 -0500189#elif defined(CONFIG_MPC85xx)
190 mpc85xx_reginfo();
191
Mike Frysinger97c26e02008-02-04 19:26:56 -0500192#elif defined(CONFIG_BLACKFIN)
193 puts("\nSystem Configuration registers\n");
Sonic Zhanga2979dc2012-08-16 11:56:14 +0800194#ifndef __ADSPBF60x__
Mike Frysinger97c26e02008-02-04 19:26:56 -0500195 puts("\nPLL Registers\n");
196 printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n",
197 bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
198 printf("\tPLL_STAT: 0x%04x PLL_LOCKCNT: 0x%04x\n",
199 bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
200 printf("\tVR_CTL: 0x%04x\n", bfin_read_VR_CTL());
201
202 puts("\nEBIU AMC Registers\n");
203 printf("\tEBIU_AMGCTL: 0x%04x\n", bfin_read_EBIU_AMGCTL());
204 printf("\tEBIU_AMBCTL0: 0x%08x EBIU_AMBCTL1: 0x%08x\n",
205 bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
206# ifdef EBIU_MODE
207 printf("\tEBIU_MBSCTL: 0x%08x EBIU_ARBSTAT: 0x%08x\n",
208 bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
209 printf("\tEBIU_MODE: 0x%08x EBIU_FCTL: 0x%08x\n",
210 bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
211# endif
212
213# ifdef EBIU_RSTCTL
214 puts("\nEBIU DDR Registers\n");
215 printf("\tEBIU_DDRCTL0: 0x%08x EBIU_DDRCTL1: 0x%08x\n",
216 bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
217 printf("\tEBIU_DDRCTL2: 0x%08x EBIU_DDRCTL3: 0x%08x\n",
218 bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
219 printf("\tEBIU_DDRQUE: 0x%08x EBIU_RSTCTL 0x%04x\n",
220 bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
221 printf("\tEBIU_ERRADD: 0x%08x EBIU_ERRMST: 0x%04x\n",
222 bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
223# else
224 puts("\nEBIU SDC Registers\n");
225 printf("\tEBIU_SDRRC: 0x%04x EBIU_SDBCTL: 0x%04x\n",
226 bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
227 printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n",
228 bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
229# endif
Sonic Zhanga2979dc2012-08-16 11:56:14 +0800230#else
231 puts("\nCGU Registers\n");
232 printf("\tCGU_DIV: 0x%08x CGU_CTL: 0x%08x\n",
233 bfin_read_CGU_DIV(), bfin_read_CGU_CTL());
234 printf("\tCGU_STAT: 0x%08x CGU_LOCKCNT: 0x%08x\n",
235 bfin_read_CGU_STAT(), bfin_read_CGU_CLKOUTSEL());
Mike Frysinger97c26e02008-02-04 19:26:56 -0500236
Sonic Zhanga2979dc2012-08-16 11:56:14 +0800237 puts("\nSMC DDR Registers\n");
238 printf("\tDDR_CFG: 0x%08x DDR_TR0: 0x%08x\n",
239 bfin_read_DMC0_CFG(), bfin_read_DMC0_TR0());
240 printf("\tDDR_TR1: 0x%08x DDR_TR2: 0x%08x\n",
241 bfin_read_DMC0_TR1(), bfin_read_DMC0_TR2());
242 printf("\tDDR_MR: 0x%08x DDR_EMR1: 0x%08x\n",
243 bfin_read_DMC0_MR(), bfin_read_DMC0_EMR1());
244 printf("\tDDR_CTL: 0x%08x DDR_STAT: 0x%08x\n",
245 bfin_read_DMC0_CTL(), bfin_read_DMC0_STAT());
246 printf("\tDDR_DLLCTL:0x%08x\n", bfin_read_DMC0_DLLCTL());
247#endif
Wolfgang Denk9e04a812008-02-15 00:26:52 +0100248#endif /* CONFIG_BLACKFIN */
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600249
wdenke887afc2002-08-27 09:44:07 +0000250 return 0;
251}
252
wdenk8bde7f72003-06-27 21:31:46 +0000253 /**************************************************/
254
Mike Frysinger97c26e02008-02-04 19:26:56 -0500255#if defined(CONFIG_CMD_REGINFO)
wdenk0d498392003-07-01 21:06:45 +0000256U_BOOT_CMD(
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200257 reginfo, 2, 1, do_reginfo,
Peter Tyser2fb26042009-01-27 18:03:12 -0600258 "print register information",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200259 ""
wdenk8bde7f72003-06-27 21:31:46 +0000260);
261#endif