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wdenk0442ed82002-11-03 10:24:00 +00001/*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
Stefan Roese3cb86f32007-03-24 15:45:34 +01005 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
wdenk0442ed82002-11-03 10:24:00 +00006 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020025/*------------------------------------------------------------------------------+
26 *
27 * This source code has been made available to you by IBM on an AS-IS
28 * basis. Anyone receiving this source is licensed under IBM
29 * copyrights to use it in any way he or she deems fit, including
30 * copying it, modifying it, compiling it, and redistributing it either
31 * with or without modifications. No license under IBM patents or
32 * patent applications is to be implied by the copyright license.
33 *
34 * Any user of this software should understand that IBM cannot provide
35 * technical support for this software and will not be responsible for
36 * any consequences resulting from the use of this software.
37 *
38 * Any person who transfers this source code or any derivative work
39 * must include the IBM copyright notice, this paragraph, and the
40 * preceding two paragraphs in the transferred software.
41 *
42 * COPYRIGHT I B M CORPORATION 1995
43 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
44 *-------------------------------------------------------------------------------
45 */
wdenk0442ed82002-11-03 10:24:00 +000046
Wolfgang Denk0c8721a2005-09-23 11:05:55 +020047/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
wdenk0442ed82002-11-03 10:24:00 +000048 *
49 *
50 * The processor starts at 0xfffffffc and the code is executed
51 * from flash/rom.
52 * in memory, but as long we don't jump around before relocating.
53 * board_init lies at a quite high address and when the cpu has
54 * jumped there, everything is ok.
55 * This works because the cpu gives the FLASH (CS0) the whole
56 * address space at startup, and board_init lies as a echo of
57 * the flash somewhere up there in the memorymap.
58 *
59 * board_init will change CS0 to be positioned at the correct
60 * address and (s)dram will be positioned at address 0
61 */
62#include <config.h>
wdenk0442ed82002-11-03 10:24:00 +000063#include <ppc4xx.h>
64#include <version.h>
65
66#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
67
68#include <ppc_asm.tmpl>
69#include <ppc_defs.h>
70
71#include <asm/cache.h>
72#include <asm/mmu.h>
73
74#ifndef CONFIG_IDENT_STRING
75#define CONFIG_IDENT_STRING ""
76#endif
77
78#ifdef CFG_INIT_DCACHE_CS
79# if (CFG_INIT_DCACHE_CS == 0)
80# define PBxAP pb0ap
81# define PBxCR pb0cr
82# endif
83# if (CFG_INIT_DCACHE_CS == 1)
84# define PBxAP pb1ap
85# define PBxCR pb1cr
86# endif
87# if (CFG_INIT_DCACHE_CS == 2)
88# define PBxAP pb2ap
89# define PBxCR pb2cr
90# endif
91# if (CFG_INIT_DCACHE_CS == 3)
92# define PBxAP pb3ap
93# define PBxCR pb3cr
94# endif
95# if (CFG_INIT_DCACHE_CS == 4)
96# define PBxAP pb4ap
97# define PBxCR pb4cr
98# endif
99# if (CFG_INIT_DCACHE_CS == 5)
100# define PBxAP pb5ap
101# define PBxCR pb5cr
102# endif
103# if (CFG_INIT_DCACHE_CS == 6)
104# define PBxAP pb6ap
105# define PBxCR pb6cr
106# endif
107# if (CFG_INIT_DCACHE_CS == 7)
108# define PBxAP pb7ap
109# define PBxCR pb7cr
110# endif
111#endif /* CFG_INIT_DCACHE_CS */
112
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200113#define function_prolog(func_name) .text; \
Stefan Roesecf959c72007-06-01 15:27:11 +0200114 .align 2; \
115 .globl func_name; \
116 func_name:
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200117#define function_epilog(func_name) .type func_name,@function; \
Stefan Roesecf959c72007-06-01 15:27:11 +0200118 .size func_name,.-func_name
119
wdenk0442ed82002-11-03 10:24:00 +0000120/* We don't want the MMU yet.
121*/
122#undef MSR_KERNEL
123#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
124
125
126 .extern ext_bus_cntlr_init
127 .extern sdram_init
Stefan Roese887e2ec2006-09-07 11:51:23 +0200128#ifdef CONFIG_NAND_U_BOOT
129 .extern reconfig_tlb0
130#endif
wdenk0442ed82002-11-03 10:24:00 +0000131
132/*
133 * Set up GOT: Global Offset Table
134 *
135 * Use r14 to access the GOT
136 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200137#if !defined(CONFIG_NAND_SPL)
wdenk0442ed82002-11-03 10:24:00 +0000138 START_GOT
139 GOT_ENTRY(_GOT2_TABLE_)
140 GOT_ENTRY(_FIXUP_TABLE_)
141
142 GOT_ENTRY(_start)
143 GOT_ENTRY(_start_of_vectors)
144 GOT_ENTRY(_end_of_vectors)
145 GOT_ENTRY(transfer_to_handler)
146
wdenk3b57fe02003-05-30 12:48:29 +0000147 GOT_ENTRY(__init_end)
wdenk0442ed82002-11-03 10:24:00 +0000148 GOT_ENTRY(_end)
wdenk5d232d02003-05-22 22:52:13 +0000149 GOT_ENTRY(__bss_start)
wdenk0442ed82002-11-03 10:24:00 +0000150 END_GOT
Stefan Roese887e2ec2006-09-07 11:51:23 +0200151#endif /* CONFIG_NAND_SPL */
152
153#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
154 /*
155 * NAND U-Boot image is started from offset 0
156 */
157 .text
Stefan Roesec440bfe2007-06-06 11:42:13 +0200158#if defined(CONFIG_440)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200159 bl reconfig_tlb0
Stefan Roesec440bfe2007-06-06 11:42:13 +0200160#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200161 GET_GOT
162 bl cpu_init_f /* run low-level CPU init code (from Flash) */
163 bl board_init_f
164#endif
wdenk0442ed82002-11-03 10:24:00 +0000165
166/*
167 * 440 Startup -- on reset only the top 4k of the effective
168 * address space is mapped in by an entry in the instruction
169 * and data shadow TLB. The .bootpg section is located in the
170 * top 4k & does only what's necessary to map in the the rest
171 * of the boot rom. Once the boot rom is mapped in we can
172 * proceed with normal startup.
173 *
174 * NOTE: CS0 only covers the top 2MB of the effective address
175 * space after reset.
176 */
177
178#if defined(CONFIG_440)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200179#if !defined(CONFIG_NAND_SPL)
wdenk0442ed82002-11-03 10:24:00 +0000180 .section .bootpg,"ax"
Stefan Roese887e2ec2006-09-07 11:51:23 +0200181#endif
wdenk0442ed82002-11-03 10:24:00 +0000182 .globl _start_440
183
184/**************************************************************************/
185_start_440:
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200186 /*--------------------------------------------------------------------+
187 | 440EPX BUP Change - Hardware team request
188 +--------------------------------------------------------------------*/
Stefan Roese887e2ec2006-09-07 11:51:23 +0200189#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
190 sync
191 nop
192 nop
193#endif
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200194 /*----------------------------------------------------------------+
195 | Core bug fix. Clear the esr
196 +-----------------------------------------------------------------*/
Marian Balakowiczedd6cf22006-07-06 21:17:24 +0200197 li r0,0
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200198 mtspr esr,r0
wdenk0442ed82002-11-03 10:24:00 +0000199 /*----------------------------------------------------------------*/
200 /* Clear and set up some registers. */
201 /*----------------------------------------------------------------*/
Wolfgang Denkf901a832005-08-06 01:42:58 +0200202 iccci r0,r0 /* NOTE: operands not used for 440 */
203 dccci r0,r0 /* NOTE: operands not used for 440 */
wdenk0442ed82002-11-03 10:24:00 +0000204 sync
205 li r0,0
206 mtspr srr0,r0
207 mtspr srr1,r0
208 mtspr csrr0,r0
209 mtspr csrr1,r0
Stefan Roese887e2ec2006-09-07 11:51:23 +0200210 /* NOTE: 440GX adds machine check status regs */
211#if defined(CONFIG_440) && !defined(CONFIG_440GP)
Wolfgang Denkf901a832005-08-06 01:42:58 +0200212 mtspr mcsrr0,r0
213 mtspr mcsrr1,r0
Stefan Roese887e2ec2006-09-07 11:51:23 +0200214 mfspr r1,mcsr
Wolfgang Denkf901a832005-08-06 01:42:58 +0200215 mtspr mcsr,r1
wdenkba56f622004-02-06 23:19:44 +0000216#endif
Stefan Roese20532832006-11-22 13:20:50 +0100217
218 /*----------------------------------------------------------------*/
219 /* CCR0 init */
220 /*----------------------------------------------------------------*/
221 /* Disable store gathering & broadcast, guarantee inst/data
222 * cache block touch, force load/store alignment
223 * (see errata 1.12: 440_33)
224 */
225 lis r1,0x0030 /* store gathering & broadcast disable */
226 ori r1,r1,0x6000 /* cache touch */
227 mtspr ccr0,r1
228
wdenk0442ed82002-11-03 10:24:00 +0000229 /*----------------------------------------------------------------*/
230 /* Initialize debug */
231 /*----------------------------------------------------------------*/
Stefan Roese887e2ec2006-09-07 11:51:23 +0200232 mfspr r1,dbcr0
233 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
234 bne skip_debug_init /* if set, don't clear debug register */
wdenk0442ed82002-11-03 10:24:00 +0000235 mtspr dbcr0,r0
236 mtspr dbcr1,r0
237 mtspr dbcr2,r0
238 mtspr iac1,r0
239 mtspr iac2,r0
240 mtspr iac3,r0
241 mtspr dac1,r0
242 mtspr dac2,r0
243 mtspr dvc1,r0
244 mtspr dvc2,r0
245
246 mfspr r1,dbsr
247 mtspr dbsr,r1 /* Clear all valid bits */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200248skip_debug_init:
wdenk0442ed82002-11-03 10:24:00 +0000249
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200250#if defined (CONFIG_440SPE)
251 /*----------------------------------------------------------------+
252 | Initialize Core Configuration Reg1.
253 | a. ICDPEI: Record even parity. Normal operation.
254 | b. ICTPEI: Record even parity. Normal operation.
255 | c. DCTPEI: Record even parity. Normal operation.
256 | d. DCDPEI: Record even parity. Normal operation.
257 | e. DCUPEI: Record even parity. Normal operation.
258 | f. DCMPEI: Record even parity. Normal operation.
259 | g. FCOM: Normal operation
260 | h. MMUPEI: Record even parity. Normal operation.
261 | i. FFF: Flush only as much data as necessary.
Marian Balakowiczedd6cf22006-07-06 21:17:24 +0200262 | j. TCS: Timebase increments from CPU clock.
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200263 +-----------------------------------------------------------------*/
Marian Balakowiczedd6cf22006-07-06 21:17:24 +0200264 li r0,0
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200265 mtspr ccr1, r0
266
267 /*----------------------------------------------------------------+
268 | Reset the timebase.
269 | The previous write to CCR1 sets the timebase source.
270 +-----------------------------------------------------------------*/
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200271 mtspr tbl, r0
272 mtspr tbu, r0
273#endif
274
wdenk0442ed82002-11-03 10:24:00 +0000275 /*----------------------------------------------------------------*/
276 /* Setup interrupt vectors */
277 /*----------------------------------------------------------------*/
278 mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200279 li r1,0x0100
wdenk0442ed82002-11-03 10:24:00 +0000280 mtspr ivor0,r1 /* Critical input */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200281 li r1,0x0200
wdenk0442ed82002-11-03 10:24:00 +0000282 mtspr ivor1,r1 /* Machine check */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200283 li r1,0x0300
wdenk0442ed82002-11-03 10:24:00 +0000284 mtspr ivor2,r1 /* Data storage */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200285 li r1,0x0400
wdenk0442ed82002-11-03 10:24:00 +0000286 mtspr ivor3,r1 /* Instruction storage */
287 li r1,0x0500
288 mtspr ivor4,r1 /* External interrupt */
289 li r1,0x0600
290 mtspr ivor5,r1 /* Alignment */
291 li r1,0x0700
292 mtspr ivor6,r1 /* Program check */
293 li r1,0x0800
294 mtspr ivor7,r1 /* Floating point unavailable */
295 li r1,0x0c00
296 mtspr ivor8,r1 /* System call */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200297 li r1,0x0a00
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200298 mtspr ivor9,r1 /* Auxiliary Processor unavailable */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200299 li r1,0x0900
300 mtspr ivor10,r1 /* Decrementer */
wdenk0442ed82002-11-03 10:24:00 +0000301 li r1,0x1300
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200302 mtspr ivor13,r1 /* Data TLB error */
303 li r1,0x1400
wdenk0442ed82002-11-03 10:24:00 +0000304 mtspr ivor14,r1 /* Instr TLB error */
305 li r1,0x2000
306 mtspr ivor15,r1 /* Debug */
307
308 /*----------------------------------------------------------------*/
309 /* Configure cache regions */
310 /*----------------------------------------------------------------*/
311 mtspr inv0,r0
312 mtspr inv1,r0
313 mtspr inv2,r0
314 mtspr inv3,r0
315 mtspr dnv0,r0
316 mtspr dnv1,r0
317 mtspr dnv2,r0
318 mtspr dnv3,r0
319 mtspr itv0,r0
320 mtspr itv1,r0
321 mtspr itv2,r0
322 mtspr itv3,r0
323 mtspr dtv0,r0
324 mtspr dtv1,r0
325 mtspr dtv2,r0
326 mtspr dtv3,r0
327
328 /*----------------------------------------------------------------*/
329 /* Cache victim limits */
330 /*----------------------------------------------------------------*/
331 /* floors 0, ceiling max to use the entire cache -- nothing locked
332 */
333 lis r1,0x0001
334 ori r1,r1,0xf800
335 mtspr ivlim,r1
336 mtspr dvlim,r1
337
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200338 /*----------------------------------------------------------------+
339 |Initialize MMUCR[STID] = 0.
340 +-----------------------------------------------------------------*/
341 mfspr r0,mmucr
342 addis r1,0,0xFFFF
343 ori r1,r1,0xFF00
344 and r0,r0,r1
345 mtspr mmucr,r0
346
wdenk0442ed82002-11-03 10:24:00 +0000347 /*----------------------------------------------------------------*/
348 /* Clear all TLB entries -- TID = 0, TS = 0 */
349 /*----------------------------------------------------------------*/
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200350 addis r0,0,0x0000
wdenk0442ed82002-11-03 10:24:00 +0000351 li r1,0x003f /* 64 TLB entries */
352 mtctr r1
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200353rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
354 tlbwe r0,r1,0x0001
355 tlbwe r0,r1,0x0002
wdenk0442ed82002-11-03 10:24:00 +0000356 subi r1,r1,0x0001
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200357 bdnz rsttlb
wdenk0442ed82002-11-03 10:24:00 +0000358
359 /*----------------------------------------------------------------*/
360 /* TLB entry setup -- step thru tlbtab */
361 /*----------------------------------------------------------------*/
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200362#if defined(CONFIG_440SPE)
363 /*----------------------------------------------------------------*/
364 /* We have different TLB tables for revA and rev B of 440SPe */
365 /*----------------------------------------------------------------*/
366 mfspr r1, PVR
367 lis r0,0x5342
368 ori r0,r0,0x1891
369 cmpw r7,r1,r0
370 bne r7,..revA
371 bl tlbtabB
372 b ..goon
373..revA:
374 bl tlbtabA
375..goon:
376#else
wdenk0442ed82002-11-03 10:24:00 +0000377 bl tlbtab /* Get tlbtab pointer */
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200378#endif
wdenk0442ed82002-11-03 10:24:00 +0000379 mr r5,r0
380 li r1,0x003f /* 64 TLB entries max */
381 mtctr r1
382 li r4,0 /* TLB # */
383
384 addi r5,r5,-4
3851: lwzu r0,4(r5)
386 cmpwi r0,0
387 beq 2f /* 0 marks end */
388 lwzu r1,4(r5)
389 lwzu r2,4(r5)
390 tlbwe r0,r4,0 /* TLB Word 0 */
391 tlbwe r1,r4,1 /* TLB Word 1 */
392 tlbwe r2,r4,2 /* TLB Word 2 */
393 addi r4,r4,1 /* Next TLB */
394 bdnz 1b
395
396 /*----------------------------------------------------------------*/
397 /* Continue from 'normal' start */
398 /*----------------------------------------------------------------*/
Stefan Roese887e2ec2006-09-07 11:51:23 +02003992:
400
401#if defined(CONFIG_NAND_SPL)
Stefan Roesecf959c72007-06-01 15:27:11 +0200402#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200403 /*
Stefan Roesecf959c72007-06-01 15:27:11 +0200404 * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200405 */
406 lis r2,0x7fff
407 ori r2,r2,0xffff
408 mfdcr r1,isram0_dpc
409 and r1,r1,r2 /* Disable parity check */
410 mtdcr isram0_dpc,r1
411 mfdcr r1,isram0_pmeg
412 and r1,r1,r2 /* Disable pwr mgmt */
413 mtdcr isram0_pmeg,r1
Stefan Roesecf959c72007-06-01 15:27:11 +0200414#endif
415#if defined(CONFIG_440EP)
416 /*
417 * On 440EP with no internal SRAM, we setup SDRAM very early
418 * and copy the NAND_SPL to SDRAM and jump to it
419 */
420 /* Clear Dcache to use as RAM */
421 addis r3,r0,CFG_INIT_RAM_ADDR@h
422 ori r3,r3,CFG_INIT_RAM_ADDR@l
423 addis r4,r0,CFG_INIT_RAM_END@h
424 ori r4,r4,CFG_INIT_RAM_END@l
425 rlwinm. r5,r4,0,27,31
426 rlwinm r5,r4,27,5,31
427 beq ..d_ran3
428 addi r5,r5,0x0001
429..d_ran3:
430 mtctr r5
431..d_ag3:
432 dcbz r0,r3
433 addi r3,r3,32
434 bdnz ..d_ag3
435 /*----------------------------------------------------------------*/
436 /* Setup the stack in internal SRAM */
437 /*----------------------------------------------------------------*/
438 lis r1,CFG_INIT_RAM_ADDR@h
439 ori r1,r1,CFG_INIT_SP_OFFSET@l
440 li r0,0
441 stwu r0,-4(r1)
442 stwu r0,-4(r1) /* Terminate call chain */
443
444 stwu r1,-8(r1) /* Save back chain and move SP */
445 lis r0,RESET_VECTOR@h /* Address of reset vector */
446 ori r0,r0, RESET_VECTOR@l
447 stwu r1,-8(r1) /* Save back chain and move SP */
448 stw r0,+12(r1) /* Save return addr (underflow vect) */
449 sync
450 bl early_sdram_init
451 sync
452#endif /* CONFIG_440EP */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200453
454 /*
455 * Copy SPL from cache into internal SRAM
456 */
457 li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
458 mtctr r4
459 lis r2,CFG_NAND_BOOT_SPL_SRC@h
460 ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
461 lis r3,CFG_NAND_BOOT_SPL_DST@h
462 ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
463spl_loop:
464 lwzu r4,4(r2)
465 stwu r4,4(r3)
466 bdnz spl_loop
467
468 /*
469 * Jump to code in RAM
470 */
471 bl 00f
47200: mflr r10
473 lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
474 ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
475 sub r10,r10,r3
476 addi r10,r10,28
477 mtlr r10
478 blr
479
480start_ram:
481 sync
482 isync
Stefan Roesecf959c72007-06-01 15:27:11 +0200483#endif /* CONFIG_NAND_SPL */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200484
485 bl 3f
wdenk0442ed82002-11-03 10:24:00 +0000486 b _start
487
4883: li r0,0
489 mtspr srr1,r0 /* Keep things disabled for now */
490 mflr r1
491 mtspr srr0,r1
492 rfi
stroeseb867d702003-05-23 11:18:02 +0000493#endif /* CONFIG_440 */
wdenk0442ed82002-11-03 10:24:00 +0000494
495/*
496 * r3 - 1st arg to board_init(): IMMP pointer
497 * r4 - 2nd arg to board_init(): boot flag
498 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200499#ifndef CONFIG_NAND_SPL
wdenk0442ed82002-11-03 10:24:00 +0000500 .text
501 .long 0x27051956 /* U-Boot Magic Number */
502 .globl version_string
503version_string:
504 .ascii U_BOOT_VERSION
505 .ascii " (", __DATE__, " - ", __TIME__, ")"
506 .ascii CONFIG_IDENT_STRING, "\0"
507
wdenk0442ed82002-11-03 10:24:00 +0000508 . = EXC_OFF_SYS_RESET
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200509 .globl _start_of_vectors
510_start_of_vectors:
511
512/* Critical input. */
513 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
514
515#ifdef CONFIG_440
516/* Machine check */
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200517 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200518#else
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200519 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200520#endif /* CONFIG_440 */
521
522/* Data Storage exception. */
523 STD_EXCEPTION(0x300, DataStorage, UnknownException)
524
525/* Instruction Storage exception. */
526 STD_EXCEPTION(0x400, InstStorage, UnknownException)
527
528/* External Interrupt exception. */
529 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
530
531/* Alignment exception. */
532 . = 0x600
533Alignment:
534 EXCEPTION_PROLOG(SRR0, SRR1)
535 mfspr r4,DAR
536 stw r4,_DAR(r21)
537 mfspr r5,DSISR
538 stw r5,_DSISR(r21)
539 addi r3,r1,STACK_FRAME_OVERHEAD
540 li r20,MSR_KERNEL
541 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
542 lwz r6,GOT(transfer_to_handler)
543 mtlr r6
544 blrl
545.L_Alignment:
546 .long AlignmentException - _start + _START_OFFSET
547 .long int_return - _start + _START_OFFSET
548
549/* Program check exception */
550 . = 0x700
551ProgramCheck:
552 EXCEPTION_PROLOG(SRR0, SRR1)
553 addi r3,r1,STACK_FRAME_OVERHEAD
554 li r20,MSR_KERNEL
555 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
556 lwz r6,GOT(transfer_to_handler)
557 mtlr r6
558 blrl
559.L_ProgramCheck:
560 .long ProgramCheckException - _start + _START_OFFSET
561 .long int_return - _start + _START_OFFSET
562
563#ifdef CONFIG_440
564 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
565 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
566 STD_EXCEPTION(0xa00, APU, UnknownException)
Stefan Roesedf8a24c2007-06-19 16:42:31 +0200567#endif
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200568 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
569
570#ifdef CONFIG_440
571 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
572 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
573#else
574 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
575 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
576 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
577#endif
578 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
579
580 .globl _end_of_vectors
581_end_of_vectors:
582 . = _START_OFFSET
Stefan Roese887e2ec2006-09-07 11:51:23 +0200583#endif
wdenk0442ed82002-11-03 10:24:00 +0000584 .globl _start
585_start:
586
587/*****************************************************************************/
588#if defined(CONFIG_440)
589
590 /*----------------------------------------------------------------*/
591 /* Clear and set up some registers. */
592 /*----------------------------------------------------------------*/
593 li r0,0x0000
594 lis r1,0xffff
595 mtspr dec,r0 /* prevent dec exceptions */
596 mtspr tbl,r0 /* prevent fit & wdt exceptions */
597 mtspr tbu,r0
598 mtspr tsr,r1 /* clear all timer exception status */
599 mtspr tcr,r0 /* disable all */
600 mtspr esr,r0 /* clear exception syndrome register */
601 mtxer r0 /* clear integer exception register */
wdenk0442ed82002-11-03 10:24:00 +0000602
603 /*----------------------------------------------------------------*/
604 /* Debug setup -- some (not very good) ice's need an event*/
605 /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
606 /* value you need in this case 0x8cff 0000 should do the trick */
607 /*----------------------------------------------------------------*/
608#if defined(CFG_INIT_DBCR)
609 lis r1,0xffff
610 ori r1,r1,0xffff
611 mtspr dbsr,r1 /* Clear all status bits */
612 lis r0,CFG_INIT_DBCR@h
613 ori r0,r0,CFG_INIT_DBCR@l
614 mtspr dbcr0,r0
615 isync
616#endif
617
618 /*----------------------------------------------------------------*/
619 /* Setup the internal SRAM */
620 /*----------------------------------------------------------------*/
621 li r0,0
Stefan Roese887e2ec2006-09-07 11:51:23 +0200622
623#ifdef CFG_INIT_RAM_DCACHE
Stefan Roesec157d8e2005-08-01 16:41:48 +0200624 /* Clear Dcache to use as RAM */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200625 addis r3,r0,CFG_INIT_RAM_ADDR@h
626 ori r3,r3,CFG_INIT_RAM_ADDR@l
627 addis r4,r0,CFG_INIT_RAM_END@h
628 ori r4,r4,CFG_INIT_RAM_END@l
Stefan Roesec157d8e2005-08-01 16:41:48 +0200629 rlwinm. r5,r4,0,27,31
Wolfgang Denkf901a832005-08-06 01:42:58 +0200630 rlwinm r5,r4,27,5,31
631 beq ..d_ran
632 addi r5,r5,0x0001
Stefan Roesec157d8e2005-08-01 16:41:48 +0200633..d_ran:
Wolfgang Denkf901a832005-08-06 01:42:58 +0200634 mtctr r5
Stefan Roesec157d8e2005-08-01 16:41:48 +0200635..d_ag:
Wolfgang Denkf901a832005-08-06 01:42:58 +0200636 dcbz r0,r3
637 addi r3,r3,32
638 bdnz ..d_ag
Stefan Roese887e2ec2006-09-07 11:51:23 +0200639#endif /* CFG_INIT_RAM_DCACHE */
640
641 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
642#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
643 /* not all PPC's have internal SRAM usable as L2-cache */
644#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Wolfgang Denkf901a832005-08-06 01:42:58 +0200645 mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
wdenkba56f622004-02-06 23:19:44 +0000646#endif
wdenk0442ed82002-11-03 10:24:00 +0000647
Stefan Roese887e2ec2006-09-07 11:51:23 +0200648 lis r2,0x7fff
wdenk0442ed82002-11-03 10:24:00 +0000649 ori r2,r2,0xffff
650 mfdcr r1,isram0_dpc
651 and r1,r1,r2 /* Disable parity check */
652 mtdcr isram0_dpc,r1
653 mfdcr r1,isram0_pmeg
Stefan Roese887e2ec2006-09-07 11:51:23 +0200654 and r1,r1,r2 /* Disable pwr mgmt */
wdenk0442ed82002-11-03 10:24:00 +0000655 mtdcr isram0_pmeg,r1
656
657 lis r1,0x8000 /* BAS = 8000_0000 */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100658#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
wdenkba56f622004-02-06 23:19:44 +0000659 ori r1,r1,0x0980 /* first 64k */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200660 mtdcr isram0_sb0cr,r1
wdenkba56f622004-02-06 23:19:44 +0000661 lis r1,0x8001
662 ori r1,r1,0x0980 /* second 64k */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200663 mtdcr isram0_sb1cr,r1
wdenkba56f622004-02-06 23:19:44 +0000664 lis r1, 0x8002
665 ori r1,r1, 0x0980 /* third 64k */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200666 mtdcr isram0_sb2cr,r1
wdenkba56f622004-02-06 23:19:44 +0000667 lis r1, 0x8003
668 ori r1,r1, 0x0980 /* fourth 64k */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200669 mtdcr isram0_sb3cr,r1
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200670#elif defined(CONFIG_440SPE)
671 lis r1,0x0000 /* BAS = 0000_0000 */
672 ori r1,r1,0x0984 /* first 64k */
673 mtdcr isram0_sb0cr,r1
674 lis r1,0x0001
675 ori r1,r1,0x0984 /* second 64k */
676 mtdcr isram0_sb1cr,r1
677 lis r1, 0x0002
678 ori r1,r1, 0x0984 /* third 64k */
679 mtdcr isram0_sb2cr,r1
680 lis r1, 0x0003
681 ori r1,r1, 0x0984 /* fourth 64k */
682 mtdcr isram0_sb3cr,r1
Stefan Roese887e2ec2006-09-07 11:51:23 +0200683#elif defined(CONFIG_440GP)
wdenk0442ed82002-11-03 10:24:00 +0000684 ori r1,r1,0x0380 /* 8k rw */
685 mtdcr isram0_sb0cr,r1
Stefan Roese887e2ec2006-09-07 11:51:23 +0200686 mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
wdenkba56f622004-02-06 23:19:44 +0000687#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200688#endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
wdenk0442ed82002-11-03 10:24:00 +0000689
690 /*----------------------------------------------------------------*/
691 /* Setup the stack in internal SRAM */
692 /*----------------------------------------------------------------*/
693 lis r1,CFG_INIT_RAM_ADDR@h
694 ori r1,r1,CFG_INIT_SP_OFFSET@l
wdenk0442ed82002-11-03 10:24:00 +0000695 li r0,0
696 stwu r0,-4(r1)
697 stwu r0,-4(r1) /* Terminate call chain */
698
699 stwu r1,-8(r1) /* Save back chain and move SP */
700 lis r0,RESET_VECTOR@h /* Address of reset vector */
701 ori r0,r0, RESET_VECTOR@l
702 stwu r1,-8(r1) /* Save back chain and move SP */
703 stw r0,+12(r1) /* Save return addr (underflow vect) */
704
Stefan Roese887e2ec2006-09-07 11:51:23 +0200705#ifdef CONFIG_NAND_SPL
706 bl nand_boot /* will not return */
707#else
wdenk0442ed82002-11-03 10:24:00 +0000708 GET_GOT
Stefan Roese5568e612005-11-22 13:20:42 +0100709
710 bl cpu_init_f /* run low-level CPU init code (from Flash) */
wdenk0442ed82002-11-03 10:24:00 +0000711 bl board_init_f
Stefan Roese887e2ec2006-09-07 11:51:23 +0200712#endif
wdenk0442ed82002-11-03 10:24:00 +0000713
714#endif /* CONFIG_440 */
715
716/*****************************************************************************/
717#ifdef CONFIG_IOP480
718 /*----------------------------------------------------------------------- */
719 /* Set up some machine state registers. */
720 /*----------------------------------------------------------------------- */
721 addi r0,r0,0x0000 /* initialize r0 to zero */
722 mtspr esr,r0 /* clear Exception Syndrome Reg */
723 mttcr r0 /* timer control register */
724 mtexier r0 /* disable all interrupts */
wdenk0442ed82002-11-03 10:24:00 +0000725 addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
726 ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
727 mtdbsr r4 /* clear/reset the dbsr */
728 mtexisr r4 /* clear all pending interrupts */
729 addis r4,r0,0x8000
730 mtexier r4 /* enable critical exceptions */
731 addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
732 ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
733 mtiocr r4 /* since bit not used) & DRC to latch */
734 /* data bus on rising edge of CAS */
735 /*----------------------------------------------------------------------- */
736 /* Clear XER. */
737 /*----------------------------------------------------------------------- */
738 mtxer r0
739 /*----------------------------------------------------------------------- */
740 /* Invalidate i-cache and d-cache TAG arrays. */
741 /*----------------------------------------------------------------------- */
742 addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
743 addi r4,0,1024 /* 1/4 of I-cache */
744..cloop:
745 iccci 0,r3
746 iccci r4,r3
747 dccci 0,r3
748 addic. r3,r3,-16 /* move back one cache line */
749 bne ..cloop /* loop back to do rest until r3 = 0 */
750
751 /* */
752 /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
753 /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
754 /* */
755
756 /* first copy IOP480 register base address into r3 */
757 addis r3,0,0x5000 /* IOP480 register base address hi */
758/* ori r3,r3,0x0000 / IOP480 register base address lo */
759
760#ifdef CONFIG_ADCIOP
761 /* use r4 as the working variable */
762 /* turn on CS3 (LOCCTL.7) */
763 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
764 andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
765 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
766#endif
767
768#ifdef CONFIG_DASA_SIM
769 /* use r4 as the working variable */
770 /* turn on MA17 (LOCCTL.7) */
771 lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
772 ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
773 stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
774#endif
775
776 /* turn on MA16..13 (LCS0BRD.12 = 0) */
777 lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
778 andi. r4,r4,0xefff /* make bit 12 = 0 */
779 stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
780
781 /* make sure above stores all comlete before going on */
782 sync
783
784 /* last thing, set local init status done bit (DEVINIT.31) */
785 lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
786 oris r4,r4,0x8000 /* make bit 31 = 1 */
787 stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
788
789 /* clear all pending interrupts and disable all interrupts */
790 li r4,-1 /* set p1 to 0xffffffff */
791 stw r4,0x1b0(r3) /* clear all pending interrupts */
792 stw r4,0x1b8(r3) /* clear all pending interrupts */
793 li r4,0 /* set r4 to 0 */
794 stw r4,0x1b4(r3) /* disable all interrupts */
795 stw r4,0x1bc(r3) /* disable all interrupts */
796
797 /* make sure above stores all comlete before going on */
798 sync
799
800 /*----------------------------------------------------------------------- */
801 /* Enable two 128MB cachable regions. */
802 /*----------------------------------------------------------------------- */
803 addis r1,r0,0x8000
804 addi r1,r1,0x0001
805 mticcr r1 /* instruction cache */
806
807 addis r1,r0,0x0000
808 addi r1,r1,0x0000
809 mtdccr r1 /* data cache */
810
811 addis r1,r0,CFG_INIT_RAM_ADDR@h
812 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
813 li r0, 0 /* Make room for stack frame header and */
814 stwu r0, -4(r1) /* clear final stack frame so that */
815 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
816
817 GET_GOT /* initialize GOT access */
818
819 bl board_init_f /* run first part of init code (from Flash) */
820
821#endif /* CONFIG_IOP480 */
822
823/*****************************************************************************/
Stefan Roesee01bd212007-03-21 13:38:59 +0100824#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
825 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
826 defined(CONFIG_405)
wdenk0442ed82002-11-03 10:24:00 +0000827 /*----------------------------------------------------------------------- */
828 /* Clear and set up some registers. */
829 /*----------------------------------------------------------------------- */
830 addi r4,r0,0x0000
831 mtspr sgr,r4
832 mtspr dcwr,r4
833 mtesr r4 /* clear Exception Syndrome Reg */
834 mttcr r4 /* clear Timer Control Reg */
835 mtxer r4 /* clear Fixed-Point Exception Reg */
836 mtevpr r4 /* clear Exception Vector Prefix Reg */
wdenk0442ed82002-11-03 10:24:00 +0000837 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
838 /* dbsr is cleared by setting bits to 1) */
839 mtdbsr r4 /* clear/reset the dbsr */
840
841 /*----------------------------------------------------------------------- */
842 /* Invalidate I and D caches. Enable I cache for defined memory regions */
843 /* to speed things up. Leave the D cache disabled for now. It will be */
844 /* enabled/left disabled later based on user selected menu options. */
845 /* Be aware that the I cache may be disabled later based on the menu */
846 /* options as well. See miscLib/main.c. */
847 /*----------------------------------------------------------------------- */
848 bl invalidate_icache
849 bl invalidate_dcache
850
851 /*----------------------------------------------------------------------- */
852 /* Enable two 128MB cachable regions. */
853 /*----------------------------------------------------------------------- */
Stefan Roesee01bd212007-03-21 13:38:59 +0100854 lis r4,0x8000
855 ori r4,r4,0x0001
wdenk0442ed82002-11-03 10:24:00 +0000856 mticcr r4 /* instruction cache */
857 isync
858
Stefan Roesee01bd212007-03-21 13:38:59 +0100859 lis r4,0x0000
860 ori r4,r4,0x0000
wdenk0442ed82002-11-03 10:24:00 +0000861 mtdccr r4 /* data cache */
862
863#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
864 /*----------------------------------------------------------------------- */
865 /* Tune the speed and size for flash CS0 */
866 /*----------------------------------------------------------------------- */
867 bl ext_bus_cntlr_init
868#endif
869
stroeseb867d702003-05-23 11:18:02 +0000870#if defined(CONFIG_405EP)
871 /*----------------------------------------------------------------------- */
872 /* DMA Status, clear to come up clean */
873 /*----------------------------------------------------------------------- */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200874 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
875 ori r3,r3, 0xFFFF
876 mtdcr dmasr, r3
stroeseb867d702003-05-23 11:18:02 +0000877
Wolfgang Denkf901a832005-08-06 01:42:58 +0200878 bl ppc405ep_init /* do ppc405ep specific init */
stroeseb867d702003-05-23 11:18:02 +0000879#endif /* CONFIG_405EP */
880
wdenk0442ed82002-11-03 10:24:00 +0000881#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
Stefan Roesee01bd212007-03-21 13:38:59 +0100882#if defined(CONFIG_405EZ)
883 /********************************************************************
884 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
885 *******************************************************************/
886 /*
887 * We can map the OCM on the PLB3, so map it at
888 * CFG_OCM_DATA_ADDR + 0x8000
889 */
890 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
891 ori r3,r3,CFG_OCM_DATA_ADDR@l
Stefan Roesedf8a24c2007-06-19 16:42:31 +0200892 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
Stefan Roesee01bd212007-03-21 13:38:59 +0100893 mtdcr ocmplb3cr1,r3 /* Set PLB Access */
894 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
895 mtdcr ocmplb3cr2,r3 /* Set PLB Access */
896 isync
897
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200898 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
Stefan Roesee01bd212007-03-21 13:38:59 +0100899 ori r3,r3,CFG_OCM_DATA_ADDR@l
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200900 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
901 mtdcr ocmdscr1, r3 /* Set Data Side */
902 mtdcr ocmiscr1, r3 /* Set Instruction Side */
Stefan Roesee01bd212007-03-21 13:38:59 +0100903 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200904 mtdcr ocmdscr2, r3 /* Set Data Side */
905 mtdcr ocmiscr2, r3 /* Set Instruction Side */
906 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
Stefan Roesed7568942007-05-24 09:49:00 +0200907 mtdcr ocmdsisdpc,r3
Stefan Roesee01bd212007-03-21 13:38:59 +0100908
909 isync
Stefan Roese3cb86f32007-03-24 15:45:34 +0100910#else /* CONFIG_405EZ */
wdenk0442ed82002-11-03 10:24:00 +0000911 /********************************************************************
912 * Setup OCM - On Chip Memory
913 *******************************************************************/
914 /* Setup OCM */
wdenk8bde7f72003-06-27 21:31:46 +0000915 lis r0, 0x7FFF
916 ori r0, r0, 0xFFFF
Wolfgang Denkf901a832005-08-06 01:42:58 +0200917 mfdcr r3, ocmiscntl /* get instr-side IRAM config */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100918 mfdcr r4, ocmdscntl /* get data-side IRAM config */
919 and r3, r3, r0 /* disable data-side IRAM */
920 and r4, r4, r0 /* disable data-side IRAM */
921 mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
922 mtdcr ocmdscntl, r4 /* set data-side IRAM config */
wdenk8bde7f72003-06-27 21:31:46 +0000923 isync
wdenk0442ed82002-11-03 10:24:00 +0000924
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +0200925 lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100926 ori r3,r3,CFG_OCM_DATA_ADDR@l
wdenk0442ed82002-11-03 10:24:00 +0000927 mtdcr ocmdsarc, r3
928 addis r4, 0, 0xC000 /* OCM data area enabled */
929 mtdcr ocmdscntl, r4
wdenk8bde7f72003-06-27 21:31:46 +0000930 isync
Stefan Roesee01bd212007-03-21 13:38:59 +0100931#endif /* CONFIG_405EZ */
wdenk0442ed82002-11-03 10:24:00 +0000932#endif
933
Stefan Roesec440bfe2007-06-06 11:42:13 +0200934#ifdef CONFIG_NAND_SPL
935 /*
936 * Copy SPL from cache into internal SRAM
937 */
938 li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
939 mtctr r4
940 lis r2,CFG_NAND_BOOT_SPL_SRC@h
941 ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
942 lis r3,CFG_NAND_BOOT_SPL_DST@h
943 ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
944spl_loop:
945 lwzu r4,4(r2)
946 stwu r4,4(r3)
947 bdnz spl_loop
948
949 /*
950 * Jump to code in RAM
951 */
952 bl 00f
95300: mflr r10
954 lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
955 ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
956 sub r10,r10,r3
957 addi r10,r10,28
958 mtlr r10
959 blr
960
961start_ram:
962 sync
963 isync
964#endif /* CONFIG_NAND_SPL */
965
wdenk0442ed82002-11-03 10:24:00 +0000966 /*----------------------------------------------------------------------- */
967 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
968 /*----------------------------------------------------------------------- */
969#ifdef CFG_INIT_DCACHE_CS
970 /*----------------------------------------------------------------------- */
971 /* Memory Bank x (nothingness) initialization 1GB+64MEG */
972 /* used as temporary stack pointer for stage0 */
973 /*----------------------------------------------------------------------- */
974 li r4,PBxAP
975 mtdcr ebccfga,r4
976 lis r4,0x0380
977 ori r4,r4,0x0480
978 mtdcr ebccfgd,r4
979
980 addi r4,0,PBxCR
981 mtdcr ebccfga,r4
982 lis r4,0x400D
983 ori r4,r4,0xa000
984 mtdcr ebccfgd,r4
985
986 /* turn on data chache for this region */
987 lis r4,0x0080
988 mtdccr r4
989
990 /* set stack pointer and clear stack to known value */
991
992 lis r1,CFG_INIT_RAM_ADDR@h
Wolfgang Denkf901a832005-08-06 01:42:58 +0200993 ori r1,r1,CFG_INIT_SP_OFFSET@l
wdenk0442ed82002-11-03 10:24:00 +0000994
995 li r4,2048 /* we store 2048 words to stack */
996 mtctr r4
997
998 lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200999 ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */
wdenk0442ed82002-11-03 10:24:00 +00001000
1001 lis r4,0xdead /* we store 0xdeaddead in the stack */
1002 ori r4,r4,0xdead
1003
1004..stackloop:
1005 stwu r4,-4(r2)
1006 bdnz ..stackloop
1007
1008 li r0, 0 /* Make room for stack frame header and */
1009 stwu r0, -4(r1) /* clear final stack frame so that */
1010 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
1011 /*
1012 * Set up a dummy frame to store reset vector as return address.
1013 * this causes stack underflow to reset board.
1014 */
1015 stwu r1, -8(r1) /* Save back chain and move SP */
1016 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1017 ori r0, r0, RESET_VECTOR@l
1018 stwu r1, -8(r1) /* Save back chain and move SP */
1019 stw r0, +12(r1) /* Save return addr (underflow vect) */
1020
1021#elif defined(CFG_TEMP_STACK_OCM) && \
1022 (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
1023 /*
1024 * Stack in OCM.
1025 */
1026
1027 /* Set up Stack at top of OCM */
1028 lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
1029 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
1030
1031 /* Set up a zeroized stack frame so that backtrace works right */
1032 li r0, 0
1033 stwu r0, -4(r1)
1034 stwu r0, -4(r1)
1035
1036 /*
1037 * Set up a dummy frame to store reset vector as return address.
1038 * this causes stack underflow to reset board.
1039 */
1040 stwu r1, -8(r1) /* Save back chain and move SP */
1041 lis r0, RESET_VECTOR@h /* Address of reset vector */
1042 ori r0, r0, RESET_VECTOR@l
1043 stwu r1, -8(r1) /* Save back chain and move SP */
1044 stw r0, +12(r1) /* Save return addr (underflow vect) */
1045#endif /* CFG_INIT_DCACHE_CS */
1046
1047 /*----------------------------------------------------------------------- */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001048 /* Initialize SDRAM Controller */
wdenk0442ed82002-11-03 10:24:00 +00001049 /*----------------------------------------------------------------------- */
1050 bl sdram_init
1051
1052 /*
1053 * Setup temporary stack pointer only for boards
1054 * that do not use SDRAM SPD I2C stuff since it
1055 * is already initialized to use DCACHE or OCM
1056 * stacks.
1057 */
1058#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
1059 lis r1, CFG_INIT_RAM_ADDR@h
1060 ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
1061
1062 li r0, 0 /* Make room for stack frame header and */
1063 stwu r0, -4(r1) /* clear final stack frame so that */
1064 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
1065 /*
1066 * Set up a dummy frame to store reset vector as return address.
1067 * this causes stack underflow to reset board.
1068 */
1069 stwu r1, -8(r1) /* Save back chain and move SP */
1070 lis r0, RESET_VECTOR@h /* Address of reset vector */
1071 ori r0, r0, RESET_VECTOR@l
1072 stwu r1, -8(r1) /* Save back chain and move SP */
1073 stw r0, +12(r1) /* Save return addr (underflow vect) */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001074#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
wdenk0442ed82002-11-03 10:24:00 +00001075
Stefan Roesec440bfe2007-06-06 11:42:13 +02001076#ifdef CONFIG_NAND_SPL
1077 bl nand_boot /* will not return */
1078#else
wdenk0442ed82002-11-03 10:24:00 +00001079 GET_GOT /* initialize GOT access */
1080
Wolfgang Denkf901a832005-08-06 01:42:58 +02001081 bl cpu_init_f /* run low-level CPU init code (from Flash) */
wdenk0442ed82002-11-03 10:24:00 +00001082
1083 /* NEVER RETURNS! */
1084 bl board_init_f /* run first part of init code (from Flash) */
Stefan Roesec440bfe2007-06-06 11:42:13 +02001085#endif /* CONFIG_NAND_SPL */
wdenk0442ed82002-11-03 10:24:00 +00001086
wdenk12f34242003-09-02 22:48:03 +00001087#endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1088 /*----------------------------------------------------------------------- */
wdenk0442ed82002-11-03 10:24:00 +00001089
1090
Stefan Roese887e2ec2006-09-07 11:51:23 +02001091#ifndef CONFIG_NAND_SPL
wdenk0442ed82002-11-03 10:24:00 +00001092/*
1093 * This code finishes saving the registers to the exception frame
1094 * and jumps to the appropriate handler for the exception.
1095 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1096 */
1097 .globl transfer_to_handler
1098transfer_to_handler:
1099 stw r22,_NIP(r21)
1100 lis r22,MSR_POW@h
1101 andc r23,r23,r22
1102 stw r23,_MSR(r21)
1103 SAVE_GPR(7, r21)
1104 SAVE_4GPRS(8, r21)
1105 SAVE_8GPRS(12, r21)
1106 SAVE_8GPRS(24, r21)
wdenk0442ed82002-11-03 10:24:00 +00001107 mflr r23
1108 andi. r24,r23,0x3f00 /* get vector offset */
1109 stw r24,TRAP(r21)
1110 li r22,0
1111 stw r22,RESULT(r21)
1112 mtspr SPRG2,r22 /* r1 is now kernel sp */
wdenk0442ed82002-11-03 10:24:00 +00001113 lwz r24,0(r23) /* virtual address of handler */
1114 lwz r23,4(r23) /* where to go when done */
1115 mtspr SRR0,r24
1116 mtspr SRR1,r20
1117 mtlr r23
1118 SYNC
1119 rfi /* jump to handler, enable MMU */
1120
1121int_return:
1122 mfmsr r28 /* Disable interrupts */
1123 li r4,0
1124 ori r4,r4,MSR_EE
1125 andc r28,r28,r4
1126 SYNC /* Some chip revs need this... */
1127 mtmsr r28
1128 SYNC
1129 lwz r2,_CTR(r1)
1130 lwz r0,_LINK(r1)
1131 mtctr r2
1132 mtlr r0
1133 lwz r2,_XER(r1)
1134 lwz r0,_CCR(r1)
1135 mtspr XER,r2
1136 mtcrf 0xFF,r0
1137 REST_10GPRS(3, r1)
1138 REST_10GPRS(13, r1)
1139 REST_8GPRS(23, r1)
1140 REST_GPR(31, r1)
1141 lwz r2,_NIP(r1) /* Restore environment */
1142 lwz r0,_MSR(r1)
1143 mtspr SRR0,r2
1144 mtspr SRR1,r0
1145 lwz r0,GPR0(r1)
1146 lwz r2,GPR2(r1)
1147 lwz r1,GPR1(r1)
1148 SYNC
1149 rfi
1150
1151crit_return:
1152 mfmsr r28 /* Disable interrupts */
1153 li r4,0
1154 ori r4,r4,MSR_EE
1155 andc r28,r28,r4
1156 SYNC /* Some chip revs need this... */
1157 mtmsr r28
1158 SYNC
1159 lwz r2,_CTR(r1)
1160 lwz r0,_LINK(r1)
1161 mtctr r2
1162 mtlr r0
1163 lwz r2,_XER(r1)
1164 lwz r0,_CCR(r1)
1165 mtspr XER,r2
1166 mtcrf 0xFF,r0
1167 REST_10GPRS(3, r1)
1168 REST_10GPRS(13, r1)
1169 REST_8GPRS(23, r1)
1170 REST_GPR(31, r1)
1171 lwz r2,_NIP(r1) /* Restore environment */
1172 lwz r0,_MSR(r1)
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001173 mtspr csrr0,r2
1174 mtspr csrr1,r0
wdenk0442ed82002-11-03 10:24:00 +00001175 lwz r0,GPR0(r1)
1176 lwz r2,GPR2(r1)
1177 lwz r1,GPR1(r1)
1178 SYNC
1179 rfci
1180
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001181#ifdef CONFIG_440
1182mck_return:
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001183 mfmsr r28 /* Disable interrupts */
1184 li r4,0
1185 ori r4,r4,MSR_EE
1186 andc r28,r28,r4
1187 SYNC /* Some chip revs need this... */
1188 mtmsr r28
1189 SYNC
1190 lwz r2,_CTR(r1)
1191 lwz r0,_LINK(r1)
1192 mtctr r2
1193 mtlr r0
1194 lwz r2,_XER(r1)
1195 lwz r0,_CCR(r1)
1196 mtspr XER,r2
1197 mtcrf 0xFF,r0
1198 REST_10GPRS(3, r1)
1199 REST_10GPRS(13, r1)
1200 REST_8GPRS(23, r1)
1201 REST_GPR(31, r1)
1202 lwz r2,_NIP(r1) /* Restore environment */
1203 lwz r0,_MSR(r1)
1204 mtspr mcsrr0,r2
1205 mtspr mcsrr1,r0
1206 lwz r0,GPR0(r1)
1207 lwz r2,GPR2(r1)
1208 lwz r1,GPR1(r1)
1209 SYNC
1210 rfmci
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001211#endif /* CONFIG_440 */
1212
1213
1214/*
1215 * Cache functions.
1216 *
1217 * NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
1218 * although for some cache-ralated calls stubs have to be provided to satisfy
1219 * symbols resolution.
Sergei Poselenovb4489622007-07-05 08:17:37 +02001220 * Icache-related functions are used in POST framework.
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001221 *
1222 */
1223#ifdef CONFIG_440
1224 .globl dcache_disable
Wolfgang Denk4ef218f2007-07-10 00:01:28 +02001225 .globl icache_disable
Sergei Poselenovb4489622007-07-05 08:17:37 +02001226 .globl icache_enable
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001227dcache_disable:
Sergei Poselenovb4489622007-07-05 08:17:37 +02001228icache_disable:
1229icache_enable:
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001230 blr
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001231
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001232 .globl dcache_status
Sergei Poselenovb4489622007-07-05 08:17:37 +02001233 .globl icache_status
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001234dcache_status:
Sergei Poselenovb4489622007-07-05 08:17:37 +02001235icache_status:
1236 mr r3, 0
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001237 blr
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001238#else
wdenk0442ed82002-11-03 10:24:00 +00001239flush_dcache:
1240 addis r9,r0,0x0002 /* set mask for EE and CE msr bits */
1241 ori r9,r9,0x8000
1242 mfmsr r12 /* save msr */
1243 andc r9,r12,r9
1244 mtmsr r9 /* disable EE and CE */
1245 addi r10,r0,0x0001 /* enable data cache for unused memory */
1246 mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */
1247 or r10,r10,r9 /* bit 31 in dccr */
1248 mtdccr r10
1249
1250 /* do loop for # of congruence classes. */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001251 lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
1252 ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
1253 lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
1254 ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
wdenk0442ed82002-11-03 10:24:00 +00001255 mtctr r10
Wolfgang Denkf901a832005-08-06 01:42:58 +02001256 addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
wdenk0442ed82002-11-03 10:24:00 +00001257 add r11,r10,r11 /* add to get to other side of cache line */
1258..flush_dcache_loop:
1259 lwz r3,0(r10) /* least recently used side */
1260 lwz r3,0(r11) /* the other side */
1261 dccci r0,r11 /* invalidate both sides */
1262 addi r10,r10,CFG_CACHELINE_SIZE /* bump to next line */
1263 addi r11,r11,CFG_CACHELINE_SIZE /* bump to next line */
1264 bdnz ..flush_dcache_loop
1265 sync /* allow memory access to complete */
1266 mtdccr r9 /* restore dccr */
1267 mtmsr r12 /* restore msr */
1268 blr
1269
1270 .globl icache_enable
1271icache_enable:
1272 mflr r8
1273 bl invalidate_icache
1274 mtlr r8
1275 isync
1276 addis r3,r0, 0x8000 /* set bit 0 */
1277 mticcr r3
1278 blr
1279
1280 .globl icache_disable
1281icache_disable:
1282 addis r3,r0, 0x0000 /* clear bit 0 */
1283 mticcr r3
1284 isync
1285 blr
1286
1287 .globl icache_status
1288icache_status:
1289 mficcr r3
1290 srwi r3, r3, 31 /* >>31 => select bit 0 */
1291 blr
1292
1293 .globl dcache_enable
1294dcache_enable:
1295 mflr r8
1296 bl invalidate_dcache
1297 mtlr r8
1298 isync
1299 addis r3,r0, 0x8000 /* set bit 0 */
1300 mtdccr r3
1301 blr
1302
1303 .globl dcache_disable
1304dcache_disable:
1305 mflr r8
1306 bl flush_dcache
1307 mtlr r8
1308 addis r3,r0, 0x0000 /* clear bit 0 */
1309 mtdccr r3
1310 blr
1311
1312 .globl dcache_status
1313dcache_status:
1314 mfdccr r3
1315 srwi r3, r3, 31 /* >>31 => select bit 0 */
1316 blr
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001317#endif
wdenk0442ed82002-11-03 10:24:00 +00001318
1319 .globl get_pvr
1320get_pvr:
1321 mfspr r3, PVR
1322 blr
1323
wdenk0442ed82002-11-03 10:24:00 +00001324/*------------------------------------------------------------------------------- */
wdenk0442ed82002-11-03 10:24:00 +00001325/* Function: out16 */
1326/* Description: Output 16 bits */
1327/*------------------------------------------------------------------------------- */
1328 .globl out16
1329out16:
1330 sth r4,0x0000(r3)
1331 blr
1332
1333/*------------------------------------------------------------------------------- */
1334/* Function: out16r */
1335/* Description: Byte reverse and output 16 bits */
1336/*------------------------------------------------------------------------------- */
1337 .globl out16r
1338out16r:
1339 sthbrx r4,r0,r3
1340 blr
1341
1342/*------------------------------------------------------------------------------- */
wdenk0442ed82002-11-03 10:24:00 +00001343/* Function: out32r */
1344/* Description: Byte reverse and output 32 bits */
1345/*------------------------------------------------------------------------------- */
1346 .globl out32r
1347out32r:
1348 stwbrx r4,r0,r3
1349 blr
1350
1351/*------------------------------------------------------------------------------- */
1352/* Function: in16 */
1353/* Description: Input 16 bits */
1354/*------------------------------------------------------------------------------- */
1355 .globl in16
1356in16:
1357 lhz r3,0x0000(r3)
1358 blr
1359
1360/*------------------------------------------------------------------------------- */
1361/* Function: in16r */
1362/* Description: Input 16 bits and byte reverse */
1363/*------------------------------------------------------------------------------- */
1364 .globl in16r
1365in16r:
1366 lhbrx r3,r0,r3
1367 blr
1368
1369/*------------------------------------------------------------------------------- */
wdenk0442ed82002-11-03 10:24:00 +00001370/* Function: in32r */
1371/* Description: Input 32 bits and byte reverse */
1372/*------------------------------------------------------------------------------- */
1373 .globl in32r
1374in32r:
1375 lwbrx r3,r0,r3
1376 blr
1377
1378/*------------------------------------------------------------------------------- */
1379/* Function: ppcDcbf */
1380/* Description: Data Cache block flush */
1381/* Input: r3 = effective address */
1382/* Output: none. */
1383/*------------------------------------------------------------------------------- */
1384 .globl ppcDcbf
1385ppcDcbf:
1386 dcbf r0,r3
1387 blr
1388
1389/*------------------------------------------------------------------------------- */
1390/* Function: ppcDcbi */
1391/* Description: Data Cache block Invalidate */
1392/* Input: r3 = effective address */
1393/* Output: none. */
1394/*------------------------------------------------------------------------------- */
1395 .globl ppcDcbi
1396ppcDcbi:
1397 dcbi r0,r3
1398 blr
1399
1400/*------------------------------------------------------------------------------- */
1401/* Function: ppcSync */
1402/* Description: Processor Synchronize */
1403/* Input: none. */
1404/* Output: none. */
1405/*------------------------------------------------------------------------------- */
1406 .globl ppcSync
1407ppcSync:
1408 sync
1409 blr
1410
wdenk0442ed82002-11-03 10:24:00 +00001411/*
1412 * void relocate_code (addr_sp, gd, addr_moni)
1413 *
1414 * This "function" does not return, instead it continues in RAM
1415 * after relocating the monitor code.
1416 *
1417 * r3 = dest
1418 * r4 = src
1419 * r5 = length in bytes
1420 * r6 = cachelinesize
1421 */
1422 .globl relocate_code
1423relocate_code:
Stefan Roese887e2ec2006-09-07 11:51:23 +02001424#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1425 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roese00cdb4c2007-03-08 10:13:16 +01001426 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Stefan Roesea4c8d132006-06-02 16:18:04 +02001427 /*
1428 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1429 * to speed up the boot process. Now this cache needs to be disabled.
1430 */
1431 iccci 0,0 /* Invalidate inst cache */
1432 dccci 0,0 /* Invalidate data cache, now no longer our stack */
Stefan Roesec157d8e2005-08-01 16:41:48 +02001433 sync
Stefan Roesea4c8d132006-06-02 16:18:04 +02001434 isync
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001435 addi r1,r0,0x0000 /* TLB entry #0 */
Stefan Roesec157d8e2005-08-01 16:41:48 +02001436 tlbre r0,r1,0x0002 /* Read contents */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001437 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001438 tlbwe r0,r1,0x0002 /* Save it out */
Stefan Roesea4c8d132006-06-02 16:18:04 +02001439 sync
Stefan Roesec157d8e2005-08-01 16:41:48 +02001440 isync
1441#endif
wdenk0442ed82002-11-03 10:24:00 +00001442 mr r1, r3 /* Set new stack pointer */
1443 mr r9, r4 /* Save copy of Init Data pointer */
1444 mr r10, r5 /* Save copy of Destination Address */
1445
1446 mr r3, r5 /* Destination Address */
1447 lis r4, CFG_MONITOR_BASE@h /* Source Address */
1448 ori r4, r4, CFG_MONITOR_BASE@l
wdenk3b57fe02003-05-30 12:48:29 +00001449 lwz r5, GOT(__init_end)
1450 sub r5, r5, r4
wdenk0442ed82002-11-03 10:24:00 +00001451 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
1452
1453 /*
1454 * Fix GOT pointer:
1455 *
1456 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
1457 *
1458 * Offset:
1459 */
1460 sub r15, r10, r4
1461
1462 /* First our own GOT */
1463 add r14, r14, r15
1464 /* the the one used by the C code */
1465 add r30, r30, r15
1466
1467 /*
1468 * Now relocate code
1469 */
1470
1471 cmplw cr1,r3,r4
1472 addi r0,r5,3
1473 srwi. r0,r0,2
1474 beq cr1,4f /* In place copy is not necessary */
1475 beq 7f /* Protect against 0 count */
1476 mtctr r0
1477 bge cr1,2f
1478
1479 la r8,-4(r4)
1480 la r7,-4(r3)
14811: lwzu r0,4(r8)
1482 stwu r0,4(r7)
1483 bdnz 1b
1484 b 4f
1485
14862: slwi r0,r0,2
1487 add r8,r4,r0
1488 add r7,r3,r0
14893: lwzu r0,-4(r8)
1490 stwu r0,-4(r7)
1491 bdnz 3b
1492
1493/*
1494 * Now flush the cache: note that we must start from a cache aligned
1495 * address. Otherwise we might miss one cache line.
1496 */
14974: cmpwi r6,0
1498 add r5,r3,r5
1499 beq 7f /* Always flush prefetch queue in any case */
1500 subi r0,r6,1
1501 andc r3,r3,r0
1502 mr r4,r3
15035: dcbst 0,r4
1504 add r4,r4,r6
1505 cmplw r4,r5
1506 blt 5b
1507 sync /* Wait for all dcbst to complete on bus */
1508 mr r4,r3
15096: icbi 0,r4
1510 add r4,r4,r6
1511 cmplw r4,r5
1512 blt 6b
15137: sync /* Wait for all icbi to complete on bus */
1514 isync
1515
1516/*
1517 * We are done. Do not return, instead branch to second part of board
1518 * initialization, now running from RAM.
1519 */
1520
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001521 addi r0, r10, in_ram - _start + _START_OFFSET
wdenk0442ed82002-11-03 10:24:00 +00001522 mtlr r0
1523 blr /* NEVER RETURNS! */
1524
1525in_ram:
1526
1527 /*
1528 * Relocation Function, r14 point to got2+0x8000
1529 *
1530 * Adjust got2 pointers, no need to check for 0, this code
1531 * already puts a few entries in the table.
1532 */
1533 li r0,__got2_entries@sectoff@l
1534 la r3,GOT(_GOT2_TABLE_)
1535 lwz r11,GOT(_GOT2_TABLE_)
1536 mtctr r0
1537 sub r11,r3,r11
1538 addi r3,r3,-4
15391: lwzu r0,4(r3)
1540 add r0,r0,r11
1541 stw r0,0(r3)
1542 bdnz 1b
1543
1544 /*
1545 * Now adjust the fixups and the pointers to the fixups
1546 * in case we need to move ourselves again.
1547 */
15482: li r0,__fixup_entries@sectoff@l
1549 lwz r3,GOT(_FIXUP_TABLE_)
1550 cmpwi r0,0
1551 mtctr r0
1552 addi r3,r3,-4
1553 beq 4f
15543: lwzu r4,4(r3)
1555 lwzux r0,r4,r11
1556 add r0,r0,r11
1557 stw r10,0(r3)
1558 stw r0,0(r4)
1559 bdnz 3b
15604:
1561clear_bss:
1562 /*
1563 * Now clear BSS segment
1564 */
wdenk5d232d02003-05-22 22:52:13 +00001565 lwz r3,GOT(__bss_start)
wdenk0442ed82002-11-03 10:24:00 +00001566 lwz r4,GOT(_end)
1567
1568 cmplw 0, r3, r4
1569 beq 6f
1570
1571 li r0, 0
15725:
1573 stw r0, 0(r3)
1574 addi r3, r3, 4
1575 cmplw 0, r3, r4
1576 bne 5b
15776:
1578
1579 mr r3, r9 /* Init Data pointer */
1580 mr r4, r10 /* Destination Address */
1581 bl board_init_r
1582
wdenk0442ed82002-11-03 10:24:00 +00001583 /*
1584 * Copy exception vector code to low memory
1585 *
1586 * r3: dest_addr
1587 * r7: source address, r8: end address, r9: target address
1588 */
1589 .globl trap_init
1590trap_init:
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001591 lwz r7, GOT(_start_of_vectors)
wdenk0442ed82002-11-03 10:24:00 +00001592 lwz r8, GOT(_end_of_vectors)
1593
wdenk682011f2003-06-03 23:54:09 +00001594 li r9, 0x100 /* reset vector always at 0x100 */
wdenk0442ed82002-11-03 10:24:00 +00001595
1596 cmplw 0, r7, r8
1597 bgelr /* return if r7>=r8 - just in case */
1598
1599 mflr r4 /* save link register */
16001:
1601 lwz r0, 0(r7)
1602 stw r0, 0(r9)
1603 addi r7, r7, 4
1604 addi r9, r9, 4
1605 cmplw 0, r7, r8
1606 bne 1b
1607
1608 /*
1609 * relocate `hdlr' and `int_return' entries
1610 */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001611 li r7, .L_MachineCheck - _start + _START_OFFSET
1612 li r8, Alignment - _start + _START_OFFSET
wdenk0442ed82002-11-03 10:24:00 +000016132:
1614 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001615 addi r7, r7, 0x100 /* next exception vector */
wdenk0442ed82002-11-03 10:24:00 +00001616 cmplw 0, r7, r8
1617 blt 2b
1618
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001619 li r7, .L_Alignment - _start + _START_OFFSET
wdenk0442ed82002-11-03 10:24:00 +00001620 bl trap_reloc
1621
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001622 li r7, .L_ProgramCheck - _start + _START_OFFSET
wdenk0442ed82002-11-03 10:24:00 +00001623 bl trap_reloc
1624
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001625#ifdef CONFIG_440
1626 li r7, .L_FPUnavailable - _start + _START_OFFSET
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001627 bl trap_reloc
wdenk0442ed82002-11-03 10:24:00 +00001628
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001629 li r7, .L_Decrementer - _start + _START_OFFSET
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001630 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001631
1632 li r7, .L_APU - _start + _START_OFFSET
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001633 bl trap_reloc
Stefan Roesedf8a24c2007-06-19 16:42:31 +02001634
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001635 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1636 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001637
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001638 li r7, .L_DataTLBError - _start + _START_OFFSET
1639 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001640#else /* CONFIG_440 */
1641 li r7, .L_PIT - _start + _START_OFFSET
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001642 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001643
1644 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001645 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001646
1647 li r7, .L_DataTLBMiss - _start + _START_OFFSET
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001648 bl trap_reloc
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +02001649#endif /* CONFIG_440 */
1650
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001651 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1652 bl trap_reloc
wdenk0442ed82002-11-03 10:24:00 +00001653
Stefan Roese887e2ec2006-09-07 11:51:23 +02001654#if !defined(CONFIG_440)
Stefan Roese9a7b4082006-03-13 09:42:28 +01001655 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1656 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1657 mtmsr r7 /* change MSR */
1658#else
Stefan Roese887e2ec2006-09-07 11:51:23 +02001659 bl __440_msr_set
1660 b __440_msr_continue
Stefan Roese9a7b4082006-03-13 09:42:28 +01001661
Stefan Roese887e2ec2006-09-07 11:51:23 +02001662__440_msr_set:
Stefan Roese9a7b4082006-03-13 09:42:28 +01001663 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1664 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1665 mtspr srr1,r7
1666 mflr r7
1667 mtspr srr0,r7
1668 rfi
Stefan Roese887e2ec2006-09-07 11:51:23 +02001669__440_msr_continue:
Stefan Roese9a7b4082006-03-13 09:42:28 +01001670#endif
1671
wdenk0442ed82002-11-03 10:24:00 +00001672 mtlr r4 /* restore link register */
1673 blr
1674
1675 /*
1676 * Function: relocate entries for one exception vector
1677 */
1678trap_reloc:
1679 lwz r0, 0(r7) /* hdlr ... */
1680 add r0, r0, r3 /* ... += dest_addr */
1681 stw r0, 0(r7)
1682
1683 lwz r0, 4(r7) /* int_return ... */
1684 add r0, r0, r3 /* ... += dest_addr */
1685 stw r0, 4(r7)
1686
1687 blr
Stefan Roesecf959c72007-06-01 15:27:11 +02001688
1689#if defined(CONFIG_440)
1690/*----------------------------------------------------------------------------+
1691| dcbz_area.
1692+----------------------------------------------------------------------------*/
1693 function_prolog(dcbz_area)
1694 rlwinm. r5,r4,0,27,31
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001695 rlwinm r5,r4,27,5,31
1696 beq ..d_ra2
1697 addi r5,r5,0x0001
1698..d_ra2:mtctr r5
1699..d_ag2:dcbz r0,r3
1700 addi r3,r3,32
1701 bdnz ..d_ag2
Stefan Roesecf959c72007-06-01 15:27:11 +02001702 sync
1703 blr
1704 function_epilog(dcbz_area)
1705
1706/*----------------------------------------------------------------------------+
1707| dflush. Assume 32K at vector address is cachable.
1708+----------------------------------------------------------------------------*/
1709 function_prolog(dflush)
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001710 mfmsr r9
1711 rlwinm r8,r9,0,15,13
1712 rlwinm r8,r8,0,17,15
1713 mtmsr r8
1714 addi r3,r0,0x0000
1715 mtspr dvlim,r3
1716 mfspr r3,ivpr
1717 addi r4,r0,1024
1718 mtctr r4
Stefan Roesecf959c72007-06-01 15:27:11 +02001719..dflush_loop:
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001720 lwz r6,0x0(r3)
1721 addi r3,r3,32
1722 bdnz ..dflush_loop
1723 addi r3,r3,-32
1724 mtctr r4
1725..ag: dcbf r0,r3
1726 addi r3,r3,-32
1727 bdnz ..ag
Stefan Roesecf959c72007-06-01 15:27:11 +02001728 sync
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +02001729 mtmsr r9
Stefan Roesecf959c72007-06-01 15:27:11 +02001730 blr
1731 function_epilog(dflush)
1732#endif /* CONFIG_440 */
Stefan Roese887e2ec2006-09-07 11:51:23 +02001733#endif /* CONFIG_NAND_SPL */
stroeseb867d702003-05-23 11:18:02 +00001734
Stefan Roesecf959c72007-06-01 15:27:11 +02001735/*------------------------------------------------------------------------------- */
1736/* Function: in8 */
1737/* Description: Input 8 bits */
1738/*------------------------------------------------------------------------------- */
1739 .globl in8
1740in8:
1741 lbz r3,0x0000(r3)
1742 blr
1743
1744/*------------------------------------------------------------------------------- */
1745/* Function: out8 */
1746/* Description: Output 8 bits */
1747/*------------------------------------------------------------------------------- */
1748 .globl out8
1749out8:
1750 stb r4,0x0000(r3)
1751 blr
1752
1753/*------------------------------------------------------------------------------- */
1754/* Function: out32 */
1755/* Description: Output 32 bits */
1756/*------------------------------------------------------------------------------- */
1757 .globl out32
1758out32:
1759 stw r4,0x0000(r3)
1760 blr
1761
1762/*------------------------------------------------------------------------------- */
1763/* Function: in32 */
1764/* Description: Input 32 bits */
1765/*------------------------------------------------------------------------------- */
1766 .globl in32
1767in32:
1768 lwz 3,0x0000(3)
1769 blr
stroeseb867d702003-05-23 11:18:02 +00001770
Stefan Roesec440bfe2007-06-06 11:42:13 +02001771invalidate_icache:
1772 iccci r0,r0 /* for 405, iccci invalidates the */
1773 blr /* entire I cache */
1774
1775invalidate_dcache:
1776 addi r6,0,0x0000 /* clear GPR 6 */
1777 /* Do loop for # of dcache congruence classes. */
1778 lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
1779 ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
1780 /* NOTE: dccci invalidates both */
1781 mtctr r7 /* ways in the D cache */
1782..dcloop:
1783 dccci 0,r6 /* invalidate line */
1784 addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
1785 bdnz ..dcloop
1786 blr
1787
stroeseb867d702003-05-23 11:18:02 +00001788/**************************************************************************/
Wolfgang Denkf901a832005-08-06 01:42:58 +02001789/* PPC405EP specific stuff */
stroeseb867d702003-05-23 11:18:02 +00001790/**************************************************************************/
1791#ifdef CONFIG_405EP
1792ppc405ep_init:
stroeseb828dda2003-12-09 14:54:43 +00001793
Stefan Roesec157d8e2005-08-01 16:41:48 +02001794#ifdef CONFIG_BUBINGA
stroeseb828dda2003-12-09 14:54:43 +00001795 /*
1796 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1797 * function) to support FPGA and NVRAM accesses below.
1798 */
1799
1800 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1801 ori r3,r3,GPIO0_OSRH@l
1802 lis r4,CFG_GPIO0_OSRH@h
1803 ori r4,r4,CFG_GPIO0_OSRH@l
1804 stw r4,0(r3)
1805 lis r3,GPIO0_OSRL@h
1806 ori r3,r3,GPIO0_OSRL@l
1807 lis r4,CFG_GPIO0_OSRL@h
1808 ori r4,r4,CFG_GPIO0_OSRL@l
1809 stw r4,0(r3)
1810
1811 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1812 ori r3,r3,GPIO0_ISR1H@l
1813 lis r4,CFG_GPIO0_ISR1H@h
1814 ori r4,r4,CFG_GPIO0_ISR1H@l
1815 stw r4,0(r3)
1816 lis r3,GPIO0_ISR1L@h
1817 ori r3,r3,GPIO0_ISR1L@l
1818 lis r4,CFG_GPIO0_ISR1L@h
1819 ori r4,r4,CFG_GPIO0_ISR1L@l
1820 stw r4,0(r3)
1821
1822 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1823 ori r3,r3,GPIO0_TSRH@l
1824 lis r4,CFG_GPIO0_TSRH@h
1825 ori r4,r4,CFG_GPIO0_TSRH@l
1826 stw r4,0(r3)
1827 lis r3,GPIO0_TSRL@h
1828 ori r3,r3,GPIO0_TSRL@l
1829 lis r4,CFG_GPIO0_TSRL@h
1830 ori r4,r4,CFG_GPIO0_TSRL@l
1831 stw r4,0(r3)
1832
1833 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1834 ori r3,r3,GPIO0_TCR@l
1835 lis r4,CFG_GPIO0_TCR@h
1836 ori r4,r4,CFG_GPIO0_TCR@l
1837 stw r4,0(r3)
1838
1839 li r3,pb1ap /* program EBC bank 1 for RTC access */
1840 mtdcr ebccfga,r3
1841 lis r3,CFG_EBC_PB1AP@h
1842 ori r3,r3,CFG_EBC_PB1AP@l
1843 mtdcr ebccfgd,r3
1844 li r3,pb1cr
1845 mtdcr ebccfga,r3
1846 lis r3,CFG_EBC_PB1CR@h
1847 ori r3,r3,CFG_EBC_PB1CR@l
1848 mtdcr ebccfgd,r3
1849
1850 li r3,pb1ap /* program EBC bank 1 for RTC access */
1851 mtdcr ebccfga,r3
1852 lis r3,CFG_EBC_PB1AP@h
1853 ori r3,r3,CFG_EBC_PB1AP@l
1854 mtdcr ebccfgd,r3
1855 li r3,pb1cr
1856 mtdcr ebccfga,r3
1857 lis r3,CFG_EBC_PB1CR@h
1858 ori r3,r3,CFG_EBC_PB1CR@l
1859 mtdcr ebccfgd,r3
1860
1861 li r3,pb4ap /* program EBC bank 4 for FPGA access */
1862 mtdcr ebccfga,r3
1863 lis r3,CFG_EBC_PB4AP@h
1864 ori r3,r3,CFG_EBC_PB4AP@l
1865 mtdcr ebccfgd,r3
1866 li r3,pb4cr
1867 mtdcr ebccfga,r3
1868 lis r3,CFG_EBC_PB4CR@h
1869 ori r3,r3,CFG_EBC_PB4CR@l
1870 mtdcr ebccfgd,r3
1871#endif
1872
Stefan Roesed7762332006-10-12 19:50:17 +02001873#ifndef CFG_CPC0_PCI
1874 li r3,CPC0_PCI_HOST_CFG_EN
Stefan Roesec157d8e2005-08-01 16:41:48 +02001875#ifdef CONFIG_BUBINGA
wdenk8bde7f72003-06-27 21:31:46 +00001876 /*
1877 !-----------------------------------------------------------------------
1878 ! Check FPGA for PCI internal/external arbitration
1879 ! If board is set to internal arbitration, update cpc0_pci
1880 !-----------------------------------------------------------------------
stroeseb867d702003-05-23 11:18:02 +00001881 */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001882 addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
1883 ori r5,r5,FPGA_REG1@l
1884 lbz r5,0x0(r5) /* read to get PCI arb selection */
1885 andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
1886 beq ..pci_cfg_set /* if not set, then bypass reg write*/
stroeseb867d702003-05-23 11:18:02 +00001887#endif
Wolfgang Denkf901a832005-08-06 01:42:58 +02001888 ori r3,r3,CPC0_PCI_ARBIT_EN
Stefan Roesed7762332006-10-12 19:50:17 +02001889#else /* CFG_CPC0_PCI */
1890 li r3,CFG_CPC0_PCI
1891#endif /* CFG_CPC0_PCI */
stroeseb867d702003-05-23 11:18:02 +00001892..pci_cfg_set:
Wolfgang Denkf901a832005-08-06 01:42:58 +02001893 mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
stroeseb867d702003-05-23 11:18:02 +00001894
wdenk8bde7f72003-06-27 21:31:46 +00001895 /*
1896 !-----------------------------------------------------------------------
1897 ! Check to see if chip is in bypass mode.
1898 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1899 ! CPU reset Otherwise, skip this step and keep going.
Wolfgang Denkf901a832005-08-06 01:42:58 +02001900 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1901 ! will not be fast enough for the SDRAM (min 66MHz)
wdenk8bde7f72003-06-27 21:31:46 +00001902 !-----------------------------------------------------------------------
stroeseb867d702003-05-23 11:18:02 +00001903 */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001904 mfdcr r5, CPC0_PLLMR1
1905 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1906 cmpi cr0,0,r4,0x1
stroeseb867d702003-05-23 11:18:02 +00001907
Wolfgang Denkf901a832005-08-06 01:42:58 +02001908 beq pll_done /* if SSCS =b'1' then PLL has */
wdenk8bde7f72003-06-27 21:31:46 +00001909 /* already been set */
1910 /* and CPU has been reset */
1911 /* so skip to next section */
stroeseb867d702003-05-23 11:18:02 +00001912
Stefan Roesec157d8e2005-08-01 16:41:48 +02001913#ifdef CONFIG_BUBINGA
stroeseb867d702003-05-23 11:18:02 +00001914 /*
wdenk8bde7f72003-06-27 21:31:46 +00001915 !-----------------------------------------------------------------------
1916 ! Read NVRAM to get value to write in PLLMR.
1917 ! If value has not been correctly saved, write default value
1918 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1919 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1920 !
1921 ! WARNING: This code assumes the first three words in the nvram_t
Wolfgang Denkf901a832005-08-06 01:42:58 +02001922 ! structure in openbios.h. Changing the beginning of
1923 ! the structure will break this code.
wdenk8bde7f72003-06-27 21:31:46 +00001924 !
1925 !-----------------------------------------------------------------------
stroeseb867d702003-05-23 11:18:02 +00001926 */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001927 addis r3,0,NVRAM_BASE@h
1928 addi r3,r3,NVRAM_BASE@l
stroeseb867d702003-05-23 11:18:02 +00001929
Wolfgang Denkf901a832005-08-06 01:42:58 +02001930 lwz r4, 0(r3)
1931 addis r5,0,NVRVFY1@h
1932 addi r5,r5,NVRVFY1@l
1933 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1934 bne ..no_pllset
1935 addi r3,r3,4
1936 lwz r4, 0(r3)
1937 addis r5,0,NVRVFY2@h
1938 addi r5,r5,NVRVFY2@l
1939 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1940 bne ..no_pllset
1941 addi r3,r3,8 /* Skip over conf_size */
1942 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1943 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1944 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1945 cmpi cr0,0,r5,1 /* See if PLL is locked */
1946 beq pll_write
stroeseb867d702003-05-23 11:18:02 +00001947..no_pllset:
Stefan Roesec157d8e2005-08-01 16:41:48 +02001948#endif /* CONFIG_BUBINGA */
stroeseb867d702003-05-23 11:18:02 +00001949
Wolfgang Denkf901a832005-08-06 01:42:58 +02001950 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1951 ori r3,r3,PLLMR0_DEFAULT@l /* */
1952 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1953 ori r4,r4,PLLMR1_DEFAULT@l /* */
stroeseb867d702003-05-23 11:18:02 +00001954
Wolfgang Denkf901a832005-08-06 01:42:58 +02001955 b pll_write /* Write the CPC0_PLLMR with new value */
stroeseb867d702003-05-23 11:18:02 +00001956
1957pll_done:
wdenk8bde7f72003-06-27 21:31:46 +00001958 /*
1959 !-----------------------------------------------------------------------
1960 ! Clear Soft Reset Register
1961 ! This is needed to enable PCI if not booting from serial EPROM
1962 !-----------------------------------------------------------------------
stroeseb867d702003-05-23 11:18:02 +00001963 */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001964 addi r3, 0, 0x0
1965 mtdcr CPC0_SRR, r3
stroeseb867d702003-05-23 11:18:02 +00001966
Wolfgang Denkf901a832005-08-06 01:42:58 +02001967 addis r3,0,0x0010
1968 mtctr r3
stroeseb867d702003-05-23 11:18:02 +00001969pci_wait:
Wolfgang Denkf901a832005-08-06 01:42:58 +02001970 bdnz pci_wait
stroeseb867d702003-05-23 11:18:02 +00001971
1972 blr /* return to main code */
1973
1974/*
1975!-----------------------------------------------------------------------------
Wolfgang Denkf901a832005-08-06 01:42:58 +02001976! Function: pll_write
1977! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1978! That is:
1979! 1. Pll is first disabled (de-activated by putting in bypass mode)
1980! 2. PLL is reset
1981! 3. Clock dividers are set while PLL is held in reset and bypassed
1982! 4. PLL Reset is cleared
1983! 5. Wait 100us for PLL to lock
1984! 6. A core reset is performed
stroeseb867d702003-05-23 11:18:02 +00001985! Input: r3 = Value to write to CPC0_PLLMR0
1986! Input: r4 = Value to write to CPC0_PLLMR1
1987! Output r3 = none
1988!-----------------------------------------------------------------------------
1989*/
1990pll_write:
wdenk8bde7f72003-06-27 21:31:46 +00001991 mfdcr r5, CPC0_UCR
1992 andis. r5,r5,0xFFFF
Wolfgang Denkf901a832005-08-06 01:42:58 +02001993 ori r5,r5,0x0101 /* Stop the UART clocks */
1994 mtdcr CPC0_UCR,r5 /* Before changing PLL */
stroeseb867d702003-05-23 11:18:02 +00001995
wdenk8bde7f72003-06-27 21:31:46 +00001996 mfdcr r5, CPC0_PLLMR1
Wolfgang Denkf901a832005-08-06 01:42:58 +02001997 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1998 mtdcr CPC0_PLLMR1,r5
1999 oris r5,r5,0x4000 /* Set PLL Reset */
2000 mtdcr CPC0_PLLMR1,r5
stroeseb867d702003-05-23 11:18:02 +00002001
Wolfgang Denkf901a832005-08-06 01:42:58 +02002002 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
2003 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
2004 oris r5,r5,0x4000 /* Set PLL Reset */
2005 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
2006 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
2007 mtdcr CPC0_PLLMR1,r5
stroeseb867d702003-05-23 11:18:02 +00002008
2009 /*
wdenk8bde7f72003-06-27 21:31:46 +00002010 ! Wait min of 100us for PLL to lock.
2011 ! See CMOS 27E databook for more info.
2012 ! At 200MHz, that means waiting 20,000 instructions
stroeseb867d702003-05-23 11:18:02 +00002013 */
Wolfgang Denkf901a832005-08-06 01:42:58 +02002014 addi r3,0,20000 /* 2000 = 0x4e20 */
2015 mtctr r3
stroeseb867d702003-05-23 11:18:02 +00002016pll_wait:
Wolfgang Denkf901a832005-08-06 01:42:58 +02002017 bdnz pll_wait
stroeseb867d702003-05-23 11:18:02 +00002018
Wolfgang Denkf901a832005-08-06 01:42:58 +02002019 oris r5,r5,0x8000 /* Enable PLL */
2020 mtdcr CPC0_PLLMR1,r5 /* Engage */
stroeseb867d702003-05-23 11:18:02 +00002021
wdenk8bde7f72003-06-27 21:31:46 +00002022 /*
2023 * Reset CPU to guarantee timings are OK
2024 * Not sure if this is needed...
2025 */
2026 addis r3,0,0x1000
Wolfgang Denkf901a832005-08-06 01:42:58 +02002027 mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
wdenk8bde7f72003-06-27 21:31:46 +00002028 /* execution will continue from the poweron */
2029 /* vector of 0xfffffffc */
stroeseb867d702003-05-23 11:18:02 +00002030#endif /* CONFIG_405EP */
Stefan Roese4745aca2007-02-20 10:57:08 +01002031
2032#if defined(CONFIG_440)
Stefan Roese4745aca2007-02-20 10:57:08 +01002033/*----------------------------------------------------------------------------+
2034| mttlb3.
2035+----------------------------------------------------------------------------*/
2036 function_prolog(mttlb3)
2037 TLBWE(4,3,2)
2038 blr
2039 function_epilog(mttlb3)
2040
2041/*----------------------------------------------------------------------------+
2042| mftlb3.
2043+----------------------------------------------------------------------------*/
2044 function_prolog(mftlb3)
Wolfgang Denk74357112007-02-27 14:26:04 +01002045 TLBRE(3,3,2)
Stefan Roese4745aca2007-02-20 10:57:08 +01002046 blr
2047 function_epilog(mftlb3)
2048
2049/*----------------------------------------------------------------------------+
2050| mttlb2.
2051+----------------------------------------------------------------------------*/
2052 function_prolog(mttlb2)
2053 TLBWE(4,3,1)
2054 blr
2055 function_epilog(mttlb2)
2056
2057/*----------------------------------------------------------------------------+
2058| mftlb2.
2059+----------------------------------------------------------------------------*/
2060 function_prolog(mftlb2)
Wolfgang Denk74357112007-02-27 14:26:04 +01002061 TLBRE(3,3,1)
Stefan Roese4745aca2007-02-20 10:57:08 +01002062 blr
2063 function_epilog(mftlb2)
2064
2065/*----------------------------------------------------------------------------+
2066| mttlb1.
2067+----------------------------------------------------------------------------*/
2068 function_prolog(mttlb1)
2069 TLBWE(4,3,0)
2070 blr
2071 function_epilog(mttlb1)
2072
2073/*----------------------------------------------------------------------------+
2074| mftlb1.
2075+----------------------------------------------------------------------------*/
2076 function_prolog(mftlb1)
Wolfgang Denk74357112007-02-27 14:26:04 +01002077 TLBRE(3,3,0)
Stefan Roese4745aca2007-02-20 10:57:08 +01002078 blr
2079 function_epilog(mftlb1)
2080#endif /* CONFIG_440 */