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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/***********************************************************
16 * High Level Configuration Options
17 * (easy to change)
18 ***********************************************************/
19#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc6097192002-11-03 00:24:07 +000020#define CONFIG_PIP405 1 /* ...on a PIP405 board */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020021
22#define CONFIG_SYS_TEXT_BASE 0xFFF80000
23
David Müller (ELSOFT AG)3f2b5bb2014-09-30 12:32:20 +020024#define CONFIG_SYS_GENERIC_BOARD
25
wdenkc6097192002-11-03 00:24:07 +000026/***********************************************************
27 * Clock
28 ***********************************************************/
29#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
30
Jon Loeligeracf02692007-07-08 14:49:44 -050031
32/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050033 * BOOTP options
34 */
35#define CONFIG_BOOTP_BOOTFILESIZE
36#define CONFIG_BOOTP_BOOTPATH
37#define CONFIG_BOOTP_GATEWAY
38#define CONFIG_BOOTP_HOSTNAME
39
40
41/*
Jon Loeligeracf02692007-07-08 14:49:44 -050042 * Command line configuration.
43 */
44#include <config_cmd_default.h>
45
46#define CONFIG_CMD_IDE
47#define CONFIG_CMD_DHCP
48#define CONFIG_CMD_PCI
49#define CONFIG_CMD_CACHE
50#define CONFIG_CMD_IRQ
51#define CONFIG_CMD_EEPROM
52#define CONFIG_CMD_I2C
53#define CONFIG_CMD_REGINFO
54#define CONFIG_CMD_FDC
55#define CONFIG_CMD_SCSI
56#define CONFIG_CMD_FAT
57#define CONFIG_CMD_DATE
58#define CONFIG_CMD_ELF
59#define CONFIG_CMD_USB
60#define CONFIG_CMD_MII
61#define CONFIG_CMD_SDRAM
Jon Loeligeracf02692007-07-08 14:49:44 -050062#define CONFIG_CMD_PING
63#define CONFIG_CMD_SAVES
64#define CONFIG_CMD_BSP
65
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_HUSH_PARSER
wdenkc6097192002-11-03 00:24:07 +000067/**************************************************************
68 * I2C Stuff:
69 * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
70 * 0x53.
71 * Caution: on the same bus is the SPD (Serial Presens Detect
72 * EEPROM of the SDRAM
73 * The Atmel EEPROM uses 16Bit addressing.
74 ***************************************************************/
Dirk Eibach880540d2013-04-25 02:40:01 +000075#define CONFIG_SYS_I2C
76#define CONFIG_SYS_I2C_PPC4XX
77#define CONFIG_SYS_I2C_PPC4XX_CH0
78#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
79#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
wdenkc6097192002-11-03 00:24:07 +000080
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
82#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +020083#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020084#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
85#define CONFIG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */
wdenkc6097192002-11-03 00:24:07 +000086
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
88#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
wdenkc6097192002-11-03 00:24:07 +000089 /* 64 byte page write mode using*/
90 /* last 6 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkc6097192002-11-03 00:24:07 +000092
93
94/***************************************************************
95 * Definitions for Serial Presence Detect EEPROM address
96 * (to get SDRAM settings)
97 ***************************************************************/
98#define SPD_EEPROM_ADDRESS 0x50
99
wdenkc837dcb2004-01-20 23:12:12 +0000100#define CONFIG_BOARD_EARLY_INIT_F
David Müller21be3092011-12-22 13:38:20 +0100101#define CONFIG_BOARD_EARLY_INIT_R
102
wdenkc6097192002-11-03 00:24:07 +0000103/**************************************************************
104 * Environment definitions
105 **************************************************************/
106#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
107
108
109#define CONFIG_BOOTDELAY 5
110/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
Wolfgang Denk2afbe4e2005-08-13 02:04:37 +0200111/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200112#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
wdenkc6097192002-11-03 00:24:07 +0000113
114
wdenk3e386912003-04-05 00:53:31 +0000115#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
wdenkc6097192002-11-03 00:24:07 +0000116#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
117
118#define CONFIG_IPADDR 10.0.0.100
119#define CONFIG_SERVERIP 10.0.0.1
120#define CONFIG_PREBOOT
121/***************************************************************
122 * defines if the console is stored in the environment
123 ***************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
wdenkc6097192002-11-03 00:24:07 +0000125/***************************************************************
126 * defines if an overwrite_console function exists
127 *************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
129#define CONFIG_SYS_CONSOLE_INFO_QUIET
wdenkc6097192002-11-03 00:24:07 +0000130/***************************************************************
131 * defines if the overwrite_console should be stored in the
132 * environment
133 **************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
wdenkc6097192002-11-03 00:24:07 +0000135
136/**************************************************************
137 * loads config
138 *************************************************************/
139#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkc6097192002-11-03 00:24:07 +0000141
wdenk7205e402003-09-10 22:30:53 +0000142#define CONFIG_MISC_INIT_R
wdenkc6097192002-11-03 00:24:07 +0000143/***********************************************************
144 * Miscellaneous configurable options
145 **********************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeligeracf02692007-07-08 14:49:44 -0500147#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000149#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000151#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
153#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
154#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
157#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000158
Stefan Roese550650d2010-09-20 16:05:31 +0200159#define CONFIG_CONS_INDEX 1 /* Use UART0 */
160#define CONFIG_SYS_NS16550
161#define CONFIG_SYS_NS16550_SERIAL
162#define CONFIG_SYS_NS16550_REG_SIZE 1
163#define CONFIG_SYS_NS16550_CLK get_serial_clock()
164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
166#define CONFIG_SYS_BASE_BAUD 691200
wdenkc6097192002-11-03 00:24:07 +0000167
168/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_BAUDRATE_TABLE \
wdenkc6097192002-11-03 00:24:07 +0000170 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
171 57600, 115200, 230400, 460800, 921600 }
172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
174#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkc6097192002-11-03 00:24:07 +0000175
wdenkc6097192002-11-03 00:24:07 +0000176/*-----------------------------------------------------------------------
177 * PCI stuff
178 *-----------------------------------------------------------------------
179 */
180#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
181#define PCI_HOST_FORCE 1 /* configure as pci host */
182#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
183
184#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000185#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenkc6097192002-11-03 00:24:07 +0000186#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
187#define CONFIG_PCI_PNP /* pci plug-and-play */
188 /* resource configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
190#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
191#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
192#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
193#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
194#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
195#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
196#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000197
198/*-----------------------------------------------------------------------
199 * Start addresses for the final memory configuration
200 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_SDRAM_BASE 0x00000000
204#define CONFIG_SYS_FLASH_BASE 0xFFF80000
205#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
206#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
207#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000208
209/*
210 * For booting Linux, the board info and command line data
211 * have to be in the first 8 MB of memory, since this is
212 * the maximum mapped by the Linux kernel during initialization.
213 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000215/*-----------------------------------------------------------------------
216 * FLASH organization
217 */
David Müller21be3092011-12-22 13:38:20 +0100218#define CONFIG_SYS_UPDATE_FLASH_SIZE
219#define CONFIG_SYS_FLASH_PROTECTION
220#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenkc6097192002-11-03 00:24:07 +0000221
David Müller21be3092011-12-22 13:38:20 +0100222#define CONFIG_SYS_FLASH_CFI
223#define CONFIG_FLASH_CFI_DRIVER
224
225#define CONFIG_FLASH_SHOW_PROGRESS 45
226
227#define CONFIG_SYS_MAX_FLASH_BANKS 1
228#define CONFIG_SYS_MAX_FLASH_SECT 256
wdenkc6097192002-11-03 00:24:07 +0000229
wdenkc6097192002-11-03 00:24:07 +0000230/*
231 * Init Memory Controller:
232 */
wdenk7205e402003-09-10 22:30:53 +0000233#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
234#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
235/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
236#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
wdenkc6097192002-11-03 00:24:07 +0000237
wdenkc837dcb2004-01-20 23:12:12 +0000238#define CONFIG_BOARD_EARLY_INIT_F
wdenkc6097192002-11-03 00:24:07 +0000239
240/* Configuration Port location */
241#define CONFIG_PORT_ADDR 0xF4000000
242#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
243
244
wdenkc6097192002-11-03 00:24:07 +0000245/*-----------------------------------------------------------------------
246 * Definitions for initial stack pointer and data area (in On Chip SRAM)
247 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_TEMP_STACK_OCM 1
249#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
250#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
251#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200252#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200253#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000255
wdenkc6097192002-11-03 00:24:07 +0000256/***********************************************************************
257 * External peripheral base address
258 ***********************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
wdenkc6097192002-11-03 00:24:07 +0000260
261/***********************************************************************
262 * Last Stage Init
263 ***********************************************************************/
264#define CONFIG_LAST_STAGE_INIT
265/************************************************************
266 * Ethernet Stuff
267 ***********************************************************/
Ben Warren96e21f82008-10-27 23:50:15 -0700268#define CONFIG_PPC4xx_EMAC
wdenkc6097192002-11-03 00:24:07 +0000269#define CONFIG_MII 1 /* MII PHY management */
270#define CONFIG_PHY_ADDR 1 /* PHY address */
wdenkc6097192002-11-03 00:24:07 +0000271/************************************************************
272 * RTC
273 ***********************************************************/
274#define CONFIG_RTC_MC146818
275#undef CONFIG_WATCHDOG /* watchdog disabled */
276
277/************************************************************
278 * IDE/ATA stuff
279 ************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
281#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000282
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
284#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
285#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
286#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
287#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
288#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
wdenkc6097192002-11-03 00:24:07 +0000289
290#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
291#undef CONFIG_IDE_LED /* no led for ide supported */
292#define CONFIG_IDE_RESET /* reset for ide supported... */
293#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
wdenk7205e402003-09-10 22:30:53 +0000294#define CONFIG_SUPPORT_VFAT
wdenkc6097192002-11-03 00:24:07 +0000295
296/************************************************************
297 * ATAPI support (experimental)
298 ************************************************************/
299#define CONFIG_ATAPI /* enable ATAPI Support */
300
301/************************************************************
302 * SCSI support (experimental) only SYM53C8xx supported
303 ************************************************************/
304#define CONFIG_SCSI_SYM53C8XX
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */
306#define CONFIG_SYS_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
307#define CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
308#define CONFIG_SYS_SCSI_SPIN_UP_TIME 2
wdenkc6097192002-11-03 00:24:07 +0000309
310/************************************************************
311 * Disk-On-Chip configuration
312 ************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
314#define CONFIG_SYS_DOC_SHORT_TIMEOUT
315#define CONFIG_SYS_DOC_SUPPORT_2000
316#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
wdenkc6097192002-11-03 00:24:07 +0000317
318/************************************************************
319 * DISK Partition support
320 ************************************************************/
321#define CONFIG_DOS_PARTITION
322#define CONFIG_MAC_PARTITION
323#define CONFIG_ISO_PARTITION /* Experimental */
324
325/************************************************************
326 * Keyboard support
327 ************************************************************/
328#define CONFIG_ISA_KEYBOARD
329
330/************************************************************
331 * Video support
332 ************************************************************/
333#define CONFIG_VIDEO /*To enable video controller support */
334#define CONFIG_VIDEO_CT69000
335#define CONFIG_CFB_CONSOLE
336#define CONFIG_VIDEO_LOGO
337#define CONFIG_CONSOLE_EXTRA_INFO
338#define CONFIG_VGA_AS_SINGLE_DEVICE
339#define CONFIG_VIDEO_SW_CURSOR
340#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
341
342/************************************************************
343 * USB support
344 ************************************************************/
345#define CONFIG_USB_UHCI
346#define CONFIG_USB_KEYBOARD
347#define CONFIG_USB_STORAGE
348
349/* Enable needed helper functions */
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +0200350#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
wdenkc6097192002-11-03 00:24:07 +0000351
352/************************************************************
353 * Debug support
354 ************************************************************/
Jon Loeligeracf02692007-07-08 14:49:44 -0500355#if defined(CONFIG_CMD_KGDB)
wdenkc6097192002-11-03 00:24:07 +0000356#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenkc6097192002-11-03 00:24:07 +0000357#endif
358
359/************************************************************
wdenka2663ea2003-12-07 18:32:37 +0000360 * support BZIP2 compression
361 ************************************************************/
362#define CONFIG_BZIP2 1
363
364/************************************************************
wdenkc6097192002-11-03 00:24:07 +0000365 * Ident
366 ************************************************************/
367#define VERSION_TAG "released"
wdenkf3e0de62003-06-04 15:05:30 +0000368#define CONFIG_ISO_STRING "MEV-10066-001"
369#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
wdenkc6097192002-11-03 00:24:07 +0000370
371
372#endif /* __CONFIG_H */