blob: ac85278cdf0d705c1c7aa751339d7799ad49c3ab [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Graeme Russd47ab0e2011-12-23 16:51:29 +11002/*
3 * (C) Copyright 2011
4 * Graeme Russ, <graeme.russ@gmail.com>
Graeme Russd47ab0e2011-12-23 16:51:29 +11005 */
Bin Mengc17ca6b2015-08-13 00:29:10 -07006
Graeme Russd47ab0e2011-12-23 16:51:29 +11007#include <common.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +09008#include <linux/errno.h>
Simon Glassdb55bd72015-01-01 16:18:11 -07009#include <asm/mtrr.h>
Graeme Russd47ab0e2011-12-23 16:51:29 +110010
11DECLARE_GLOBAL_DATA_PTR;
12
Simon Glass5e989472013-02-28 19:26:10 +000013/* Get the top of usable RAM */
14__weak ulong board_get_usable_ram_top(ulong total_size)
Graeme Russa1d57b72011-12-23 21:14:22 +110015{
Simon Glass5e989472013-02-28 19:26:10 +000016 return gd->ram_size;
17}
18
Graeme Russa1d57b72011-12-23 21:14:22 +110019int init_cache_f_r(void)
20{
Simon Glass665cb182019-04-25 21:59:06 -060021#if (CONFIG_IS_ENABLED(X86_32BIT_INIT) || \
22 (!defined(CONFIG_SPL_BUILD) && \
23 !CONFIG_IS_ENABLED(CONFIG_X86_RUN_64BIT))) && \
24 !defined(CONFIG_HAVE_FSP)
Simon Glassdb55bd72015-01-01 16:18:11 -070025 int ret;
26
27 ret = mtrr_commit(false);
Bin Meng3b621cc2015-01-22 11:29:41 +080028 /* If MTRR MSR is not implemented by the processor, just ignore it */
29 if (ret && ret != -ENOSYS)
Simon Glassdb55bd72015-01-01 16:18:11 -070030 return ret;
31#endif
Graeme Russa1d57b72011-12-23 21:14:22 +110032 /* Initialise the CPU cache(s) */
33 return init_cache();
34}