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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37#define CONFIG_RRVISION 1 /* ...on a RRvision board */
38
Wolfgang Denk2ae18242010-10-06 09:05:45 +020039#define CONFIG_SYS_TEXT_BASE 0x40000000
40
wdenke2211742002-11-02 23:30:20 +000041#define CONFIG_8xx_GCLK_FREQ 64000000
42
43#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
44#undef CONFIG_8xx_CONS_SMC2
45#undef CONFIG_8xx_CONS_NONE
46#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
47#if 0
48#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
49#else
50#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
51#endif
52
53#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
54
55#define CONFIG_PREBOOT "setenv stdout serial"
56
57#undef CONFIG_BOOTARGS
58#define CONFIG_ETHADDR 00:50:C2:00:E0:70
59#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
60#define CONFIG_IPADDR 10.0.0.5
61#define CONFIG_SERVERIP 10.0.0.2
62#define CONFIG_NETMASK 255.0.0.0
Joe Hershberger8b3637c2011-10-13 13:03:47 +000063#define CONFIG_ROOTPATH "/opt/eldk/ppc_8xx"
wdenke2211742002-11-02 23:30:20 +000064#define CONFIG_BOOTCOMMAND "run flash_self"
65
66#define CONFIG_EXTRA_ENV_SETTINGS \
67 "netdev=eth0\0" \
68 "ramargs=setenv bootargs root=/dev/ram rw\0" \
69 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010070 "nfsroot=${serverip}:${rootpath}\0" \
71 "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}" \
72 ":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
73 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
wdenke2211742002-11-02 23:30:20 +000074 "load=tftp 100000 /tftpboot/u-boot.bin\0" \
75 "update=protect off 1:0-8;era 1:0-8;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010076 "cp.b 100000 40000000 ${filesize};" \
wdenke2211742002-11-02 23:30:20 +000077 "setenv filesize;saveenv\0" \
78 "kernel_addr=40040000\0" \
79 "ramdisk_addr=40100000\0" \
wdenk3bac3512003-03-12 10:41:04 +000080 "kernel_img=/tftpboot/uImage\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010081 "kernel_load=tftp 200000 ${kernel_img}\0" \
wdenke2211742002-11-02 23:30:20 +000082 "net_nfs=run kernel_load nfsargs addip addtty;bootm\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010083 "flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0" \
wdenke2211742002-11-02 23:30:20 +000084 "flash_self=run ramargs addip addtty;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010085 "bootm ${kernel_addr} ${ramdisk_addr}\0"
wdenke2211742002-11-02 23:30:20 +000086
87
88#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenke2211742002-11-02 23:30:20 +000090
91#undef CONFIG_WATCHDOG /* watchdog disabled */
92
93#undef CONFIG_STATUS_LED /* disturbs display */
94
95#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
96
Jon Loeliger18225e82007-07-09 21:31:24 -050097/*
98 * BOOTP options
99 */
100#define CONFIG_BOOTP_SUBNETMASK
101#define CONFIG_BOOTP_GATEWAY
102#define CONFIG_BOOTP_HOSTNAME
103#define CONFIG_BOOTP_BOOTPATH
104#define CONFIG_BOOTP_BOOTFILESIZE
105
wdenke2211742002-11-02 23:30:20 +0000106
107#define CONFIG_MAC_PARTITION
108#define CONFIG_DOS_PARTITION
109
110#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
111
112
wdenk8564acf2003-07-14 22:13:32 +0000113#ifndef CONFIG_LCD
wdenke2211742002-11-02 23:30:20 +0000114#define CONFIG_VIDEO 1 /* To enable the video initialization */
115
116/* Video related */
117#define CONFIG_VIDEO_LOGO 1 /* Show the logo */
wdenk8564acf2003-07-14 22:13:32 +0000118#define CONFIG_VIDEO_ENCODER_AD7179 1 /* Enable this encoder */
119#define CONFIG_VIDEO_ENCODER_AD7179_ADDR 0x2A /* ALSB to ground */
wdenke2211742002-11-02 23:30:20 +0000120#endif
121
122/* enable I2C and select the hardware/software driver */
123#undef CONFIG_HARD_I2C /* I2C with hardware support */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200124#define CONFIG_SOFT_I2C /* I2C bit-banged */
wdenke2211742002-11-02 23:30:20 +0000125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126# define CONFIG_SYS_I2C_SPEED 50000 /* 50 kHz is supposed to work */
127# define CONFIG_SYS_I2C_SLAVE 0xFE
wdenke2211742002-11-02 23:30:20 +0000128
129#ifdef CONFIG_SOFT_I2C
130/*
131 * Software (bit-bang) I2C driver configuration
132 */
133#define PB_SCL 0x00000020 /* PB 26 */
134#define PB_SDA 0x00000010 /* PB 27 */
135
136#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
137#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
138#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
139#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
140#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
141 else immr->im_cpm.cp_pbdat &= ~PB_SDA
142#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
143 else immr->im_cpm.cp_pbdat &= ~PB_SCL
144#define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */
145#endif /* CONFIG_SOFT_I2C */
146
147
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500148/*
149 * Command line configuration.
150 */
151#include <config_cmd_default.h>
wdenke2211742002-11-02 23:30:20 +0000152
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500153#define CONFIG_CMD_DHCP
154#define CONFIG_CMD_I2C
155#define CONFIG_CMD_IDE
156#define CONFIG_CMD_DATE
157
158#undef CONFIG_CMD_PCMCIA
159#undef CONFIG_CMD_IDE
160
wdenke2211742002-11-02 23:30:20 +0000161
162/*
163 * Miscellaneous configurable options
164 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_LONGHELP /* undef to save memory */
166#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500167#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000169#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000171#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
173#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
174#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
177#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenke2211742002-11-02 23:30:20 +0000180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000182
wdenke2211742002-11-02 23:30:20 +0000183/*
184 * Low Level Configuration Settings
185 * (address mappings, register initial values, etc.)
186 * You should know what you are doing if you make changes here.
187 */
188/*-----------------------------------------------------------------------
189 * Internal Memory Mapped Register
190 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_IMMR 0xFFF00000
wdenke2211742002-11-02 23:30:20 +0000192
193/*-----------------------------------------------------------------------
194 * Definitions for initial stack pointer and data area (in DPRAM)
195 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200197#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200198#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000200
201/*-----------------------------------------------------------------------
202 * Start addresses for the final memory configuration
203 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke2211742002-11-02 23:30:20 +0000205 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_SDRAM_BASE 0x00000000
207#define CONFIG_SYS_FLASH_BASE 0x40000000
208#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
209#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
210#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000211
212/*
213 * For booting Linux, the board info and command line data
214 * have to be in the first 8 MB of memory, since this is
215 * the maximum mapped by the Linux kernel during initialization.
216 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000218
219/*-----------------------------------------------------------------------
220 * FLASH organization
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
223#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenke2211742002-11-02 23:30:20 +0000224
225/* timeout values are in ticks = ms */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_FLASH_ERASE_TOUT (120*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
227#define CONFIG_SYS_FLASH_WRITE_TOUT (1 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenke2211742002-11-02 23:30:20 +0000228
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200229#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200230#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
231#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenke2211742002-11-02 23:30:20 +0000232
233/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200234#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
235#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenke2211742002-11-02 23:30:20 +0000236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200238
wdenke2211742002-11-02 23:30:20 +0000239/*-----------------------------------------------------------------------
240 * Cache Configuration
241 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500243#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000245#endif
246
247/*-----------------------------------------------------------------------
248 * SYPCR - System Protection Control 11-9
249 * SYPCR can only be written once after reset!
250 *-----------------------------------------------------------------------
251 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
252 */
253#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenke2211742002-11-02 23:30:20 +0000255 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
256#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenke2211742002-11-02 23:30:20 +0000258#endif
259
260/*-----------------------------------------------------------------------
261 * SIUMCR - SIU Module Configuration 11-6
262 *-----------------------------------------------------------------------
263 * PCMCIA config., multi-function pin tri-state
264 */
265#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenke2211742002-11-02 23:30:20 +0000267#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenke2211742002-11-02 23:30:20 +0000269#endif /* CONFIG_CAN_DRIVER */
270
271/*-----------------------------------------------------------------------
272 * TBSCR - Time Base Status and Control 11-26
273 *-----------------------------------------------------------------------
274 * Clear Reference Interrupt Status, Timebase freezing enabled
275 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenke2211742002-11-02 23:30:20 +0000277
278/*-----------------------------------------------------------------------
279 * RTCSC - Real-Time Clock Status and Control Register 11-27
280 *-----------------------------------------------------------------------
281 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenke2211742002-11-02 23:30:20 +0000283
284/*-----------------------------------------------------------------------
285 * PISCR - Periodic Interrupt Status and Control 11-31
286 *-----------------------------------------------------------------------
287 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
288 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
wdenke2211742002-11-02 23:30:20 +0000290
291/*-----------------------------------------------------------------------
292 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
293 *-----------------------------------------------------------------------
294 * Reset PLL lock status sticky bit, timer expired status bit and timer
295 * interrupt status bit
296 */
297
298/* for 64 MHz, we use a 16 MHz clock * 4 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
wdenke2211742002-11-02 23:30:20 +0000300
301/*-----------------------------------------------------------------------
302 * SCCR - System Clock and reset Control Register 15-27
303 *-----------------------------------------------------------------------
304 * Set clock output, timebase and RTC source and divider,
305 * power management and some other internal clocks
306 */
307#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_RTSEL | SCCR_RTDIV | \
wdenke2211742002-11-02 23:30:20 +0000309 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
310 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
311 SCCR_DFALCD00)
312
313/*-----------------------------------------------------------------------
314 * PCMCIA stuff
315 *-----------------------------------------------------------------------
316 *
317 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
319#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
320#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
321#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
322#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
323#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
324#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
325#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenke2211742002-11-02 23:30:20 +0000326
327/*-----------------------------------------------------------------------
328 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
329 *-----------------------------------------------------------------------
330 */
331
332#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
333
334#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
335#undef CONFIG_IDE_LED /* LED for ide not supported */
336#undef CONFIG_IDE_RESET /* reset for ide not supported */
337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
339#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenke2211742002-11-02 23:30:20 +0000340
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenke2211742002-11-02 23:30:20 +0000342
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenke2211742002-11-02 23:30:20 +0000344
345/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenke2211742002-11-02 23:30:20 +0000347
348/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenke2211742002-11-02 23:30:20 +0000350
351/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenke2211742002-11-02 23:30:20 +0000353
354/*-----------------------------------------------------------------------
355 *
356 *-----------------------------------------------------------------------
357 *
358 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359/*#define CONFIG_SYS_DER 0x2002000F*/
360#define CONFIG_SYS_DER 0
wdenke2211742002-11-02 23:30:20 +0000361
362/*
363 * Init Memory Controller:
364 *
365 * BR0/1 (FLASH)
366 */
367
368#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
369
370/* used to re-map FLASH both when starting from SRAM or FLASH:
371 * restrict access enough to keep SRAM working (if any)
372 * but not too much to meddle with FLASH accesses
373 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
375#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenke2211742002-11-02 23:30:20 +0000376
377/*
378 * FLASH timing:
379 */
380/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenke2211742002-11-02 23:30:20 +0000382 OR_SCY_3_CLK | OR_EHTR | OR_BI)
383
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
385#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
386#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenke2211742002-11-02 23:30:20 +0000387
388/*
389 * BR2/3 and OR2/3 (SDRAM)
390 *
391 */
392#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
393#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
394#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
395
396/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenke2211742002-11-02 23:30:20 +0000398
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
400#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenke2211742002-11-02 23:30:20 +0000401
402#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
404#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenke2211742002-11-02 23:30:20 +0000405#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
407#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
408#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
409#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenke2211742002-11-02 23:30:20 +0000410 BR_PS_8 | BR_MS_UPMB | BR_V )
411#endif /* CONFIG_CAN_DRIVER */
412
413/*
414 * Memory Periodic Timer Prescaler
415 *
416 * The Divider for PTA (refresh timer) configuration is based on an
417 * example SDRAM configuration (64 MBit, one bank). The adjustment to
418 * the number of chip selects (NCS) and the actually needed refresh
419 * rate is done by setting MPTPR.
420 *
421 * PTA is calculated from
422 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
423 *
424 * gclk CPU clock (not bus clock!)
425 * Trefresh Refresh cycle * 4 (four word bursts used)
426 *
427 * 4096 Rows from SDRAM example configuration
428 * 1000 factor s -> ms
429 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
430 * 4 Number of refresh cycles per period
431 * 64 Refresh cycle in ms per number of rows
432 * --------------------------------------------
433 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
434 *
435 * 50 MHz => 50.000.000 / Divider = 98
436 * 66 Mhz => 66.000.000 / Divider = 129
437 * 80 Mhz => 80.000.000 / Divider = 156
438 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_MAMR_PTA 129
wdenke2211742002-11-02 23:30:20 +0000440
441/*
442 * For 16 MBit, refresh rates could be 31.3 us
443 * (= 64 ms / 2K = 125 / quad bursts).
444 * For a simpler initialization, 15.6 us is used instead.
445 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
447 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenke2211742002-11-02 23:30:20 +0000448 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
450#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenke2211742002-11-02 23:30:20 +0000451
452/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
454#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenke2211742002-11-02 23:30:20 +0000455
456/*
457 * MAMR settings for SDRAM
458 */
459
460/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenke2211742002-11-02 23:30:20 +0000462 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
463 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
464/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenke2211742002-11-02 23:30:20 +0000466 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
467 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
468
469
wdenke2211742002-11-02 23:30:20 +0000470#endif /* __CONFIG_H */