wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1 | /*------------------------------------------------------------------------ |
| 2 | . smc91111.c |
| 3 | . This is a driver for SMSC's 91C111 single-chip Ethernet device. |
| 4 | . |
| 5 | . (C) Copyright 2002 |
| 6 | . Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 7 | . Rolf Offermanns <rof@sysgo.de> |
| 8 | . |
| 9 | . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 10 | . Developed by Simple Network Magic Corporation (SNMC) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 11 | . Copyright (C) 1996 by Erik Stahlman (ES) |
| 12 | . |
| 13 | . This program is free software; you can redistribute it and/or modify |
| 14 | . it under the terms of the GNU General Public License as published by |
| 15 | . the Free Software Foundation; either version 2 of the License, or |
| 16 | . (at your option) any later version. |
| 17 | . |
| 18 | . This program is distributed in the hope that it will be useful, |
| 19 | . but WITHOUT ANY WARRANTY; without even the implied warranty of |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 20 | . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 21 | . GNU General Public License for more details. |
| 22 | . |
| 23 | . You should have received a copy of the GNU General Public License |
| 24 | . along with this program; if not, write to the Free Software |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 25 | . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 26 | . |
| 27 | . Information contained in this file was obtained from the LAN91C111 |
| 28 | . manual from SMC. To get a copy, if you really want one, you can find |
| 29 | . information under www.smsc.com. |
| 30 | . |
| 31 | . |
| 32 | . "Features" of the SMC chip: |
| 33 | . Integrated PHY/MAC for 10/100BaseT Operation |
| 34 | . Supports internal and external MII |
| 35 | . Integrated 8K packet memory |
| 36 | . EEPROM interface for configuration |
| 37 | . |
| 38 | . Arguments: |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 39 | . io = for the base address |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 40 | . irq = for the IRQ |
| 41 | . |
| 42 | . author: |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 43 | . Erik Stahlman ( erik@vt.edu ) |
| 44 | . Daris A Nevil ( dnevil@snmc.com ) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 45 | . |
| 46 | . |
| 47 | . Hardware multicast code from Peter Cammaert ( pc@denkart.be ) |
| 48 | . |
| 49 | . Sources: |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 50 | . o SMSC LAN91C111 databook (www.smsc.com) |
| 51 | . o smc9194.c by Erik Stahlman |
| 52 | . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov ) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 53 | . |
| 54 | . History: |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 55 | . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks. |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 56 | . 10/17/01 Marco Hasewinkel Modify for DNP/1110 |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 57 | . 07/25/01 Woojung Huh Modify for ADS Bitsy |
| 58 | . 04/25/01 Daris A Nevil Initial public release through SMSC |
| 59 | . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111 |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 60 | ----------------------------------------------------------------------------*/ |
| 61 | |
| 62 | #include <common.h> |
| 63 | #include <command.h> |
wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 64 | #include <config.h> |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 65 | #include <malloc.h> |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 66 | #include "smc91111.h" |
| 67 | #include <net.h> |
| 68 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 69 | /* Use power-down feature of the chip */ |
| 70 | #define POWER_DOWN 0 |
| 71 | |
| 72 | #define NO_AUTOPROBE |
| 73 | |
Wolfgang Denk | 0be248f | 2006-03-07 00:22:36 +0100 | [diff] [blame] | 74 | #define SMC_DEBUG 0 |
wdenk | 8bf3b00 | 2003-12-06 23:20:41 +0000 | [diff] [blame] | 75 | |
| 76 | #if SMC_DEBUG > 1 |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 77 | static const char version[] = |
| 78 | "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n"; |
wdenk | 8bf3b00 | 2003-12-06 23:20:41 +0000 | [diff] [blame] | 79 | #endif |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 80 | |
wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 81 | /* Autonegotiation timeout in seconds */ |
| 82 | #ifndef CONFIG_SMC_AUTONEG_TIMEOUT |
| 83 | #define CONFIG_SMC_AUTONEG_TIMEOUT 10 |
| 84 | #endif |
| 85 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 86 | /*------------------------------------------------------------------------ |
| 87 | . |
| 88 | . Configuration options, for the experienced user to change. |
| 89 | . |
| 90 | -------------------------------------------------------------------------*/ |
| 91 | |
| 92 | /* |
| 93 | . Wait time for memory to be free. This probably shouldn't be |
| 94 | . tuned that much, as waiting for this means nothing else happens |
| 95 | . in the system |
| 96 | */ |
| 97 | #define MEMORY_WAIT_TIME 16 |
| 98 | |
| 99 | |
| 100 | #if (SMC_DEBUG > 2 ) |
| 101 | #define PRINTK3(args...) printf(args) |
| 102 | #else |
| 103 | #define PRINTK3(args...) |
| 104 | #endif |
| 105 | |
| 106 | #if SMC_DEBUG > 1 |
| 107 | #define PRINTK2(args...) printf(args) |
| 108 | #else |
| 109 | #define PRINTK2(args...) |
| 110 | #endif |
| 111 | |
| 112 | #ifdef SMC_DEBUG |
| 113 | #define PRINTK(args...) printf(args) |
| 114 | #else |
| 115 | #define PRINTK(args...) |
| 116 | #endif |
| 117 | |
| 118 | |
| 119 | /*------------------------------------------------------------------------ |
| 120 | . |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 121 | . The internal workings of the driver. If you are changing anything |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 122 | . here with the SMC stuff, you should have the datasheet and know |
| 123 | . what you are doing. |
| 124 | . |
| 125 | -------------------------------------------------------------------------*/ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 126 | |
| 127 | /* Memory sizing constant */ |
| 128 | #define LAN91C111_MEMORY_MULTIPLIER (1024*2) |
| 129 | |
| 130 | #ifndef CONFIG_SMC91111_BASE |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 131 | #error "SMC91111 Base address must be passed to initialization funciton" |
| 132 | /* #define CONFIG_SMC91111_BASE 0x20000300 */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 133 | #endif |
| 134 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 135 | #define SMC_DEV_NAME "SMC91111" |
| 136 | #define SMC_PHY_ADDR 0x0000 |
| 137 | #define SMC_ALLOC_MAX_TRY 5 |
| 138 | #define SMC_TX_TIMEOUT 30 |
| 139 | |
| 140 | #define SMC_PHY_CLOCK_DELAY 1000 |
| 141 | |
| 142 | #define ETH_ZLEN 60 |
| 143 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 144 | #ifdef CONFIG_SMC_USE_32_BIT |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 145 | #define USE_32_BIT 1 |
| 146 | #else |
| 147 | #undef USE_32_BIT |
| 148 | #endif |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 149 | |
Wolfgang Denk | 0afe519 | 2006-03-12 02:10:00 +0100 | [diff] [blame] | 150 | #ifdef SHARED_RESOURCES |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 151 | extern void swap_to(int device_id); |
| 152 | #else |
| 153 | # define swap_to(x) |
Wolfgang Denk | 0afe519 | 2006-03-12 02:10:00 +0100 | [diff] [blame] | 154 | #endif |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 155 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 156 | #ifndef CONFIG_SMC91111_EXT_PHY |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 157 | static void smc_phy_configure(struct eth_device *dev); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 158 | #endif /* !CONFIG_SMC91111_EXT_PHY */ |
| 159 | |
| 160 | /* |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 161 | ------------------------------------------------------------ |
| 162 | . |
| 163 | . Internal routines |
| 164 | . |
| 165 | ------------------------------------------------------------ |
| 166 | */ |
| 167 | |
wdenk | c3c7f86 | 2004-06-09 14:47:54 +0000 | [diff] [blame] | 168 | #ifdef CONFIG_SMC_USE_IOFUNCS |
| 169 | /* |
| 170 | * input and output functions |
| 171 | * |
| 172 | * Implemented due to inx,outx macros accessing the device improperly |
| 173 | * and putting the device into an unkown state. |
| 174 | * |
| 175 | * For instance, on Sharp LPD7A400 SDK, affects were chip memory |
| 176 | * could not be free'd (hence the alloc failures), duplicate packets, |
| 177 | * packets being corrupt (shifted) on the wire, etc. Switching to the |
| 178 | * inx,outx functions fixed this problem. |
| 179 | */ |
wdenk | c3c7f86 | 2004-06-09 14:47:54 +0000 | [diff] [blame] | 180 | |
| 181 | #define barrier() __asm__ __volatile__("": : :"memory") |
| 182 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 183 | static inline word SMC_inw(struct eth_device *dev, dword offset) |
wdenk | c3c7f86 | 2004-06-09 14:47:54 +0000 | [diff] [blame] | 184 | { |
| 185 | word v; |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 186 | v = *((volatile word*)(dev->iobase + offset)); |
wdenk | c3c7f86 | 2004-06-09 14:47:54 +0000 | [diff] [blame] | 187 | barrier(); *(volatile u32*)(0xc0000000); |
| 188 | return v; |
| 189 | } |
| 190 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 191 | static inline void SMC_outw(struct eth_device *dev, word value, dword offset) |
wdenk | c3c7f86 | 2004-06-09 14:47:54 +0000 | [diff] [blame] | 192 | { |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 193 | *((volatile word*)(dev->iobase + offset)) = value; |
wdenk | c3c7f86 | 2004-06-09 14:47:54 +0000 | [diff] [blame] | 194 | barrier(); *(volatile u32*)(0xc0000000); |
| 195 | } |
| 196 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 197 | static inline byte SMC_inb(struct eth_device *dev, dword offset) |
wdenk | c3c7f86 | 2004-06-09 14:47:54 +0000 | [diff] [blame] | 198 | { |
| 199 | word _w; |
| 200 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 201 | _w = SMC_inw(dev, offset & ~((dword)1)); |
wdenk | c3c7f86 | 2004-06-09 14:47:54 +0000 | [diff] [blame] | 202 | return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w); |
| 203 | } |
| 204 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 205 | static inline void SMC_outb(struct eth_device *dev, byte value, dword offset) |
wdenk | c3c7f86 | 2004-06-09 14:47:54 +0000 | [diff] [blame] | 206 | { |
| 207 | word _w; |
| 208 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 209 | _w = SMC_inw(dev, offset & ~((dword)1)); |
wdenk | c3c7f86 | 2004-06-09 14:47:54 +0000 | [diff] [blame] | 210 | if (offset & 1) |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 211 | *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) = |
| 212 | (value<<8) | (_w & 0x00ff); |
wdenk | c3c7f86 | 2004-06-09 14:47:54 +0000 | [diff] [blame] | 213 | else |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 214 | *((volatile word*)(dev->iobase + offset)) = |
| 215 | value | (_w & 0xff00); |
wdenk | c3c7f86 | 2004-06-09 14:47:54 +0000 | [diff] [blame] | 216 | } |
| 217 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 218 | static inline void SMC_insw(struct eth_device *dev, dword offset, |
| 219 | volatile uchar* buf, dword len) |
wdenk | c3c7f86 | 2004-06-09 14:47:54 +0000 | [diff] [blame] | 220 | { |
Wolfgang Denk | d52fb7e | 2006-03-11 22:53:33 +0100 | [diff] [blame] | 221 | volatile word *p = (volatile word *)buf; |
| 222 | |
wdenk | c3c7f86 | 2004-06-09 14:47:54 +0000 | [diff] [blame] | 223 | while (len-- > 0) { |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 224 | *p++ = SMC_inw(dev, offset); |
Wolfgang Denk | d52fb7e | 2006-03-11 22:53:33 +0100 | [diff] [blame] | 225 | barrier(); |
| 226 | *((volatile u32*)(0xc0000000)); |
wdenk | c3c7f86 | 2004-06-09 14:47:54 +0000 | [diff] [blame] | 227 | } |
| 228 | } |
| 229 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 230 | static inline void SMC_outsw(struct eth_device *dev, dword offset, |
| 231 | uchar* buf, dword len) |
wdenk | c3c7f86 | 2004-06-09 14:47:54 +0000 | [diff] [blame] | 232 | { |
Wolfgang Denk | d52fb7e | 2006-03-11 22:53:33 +0100 | [diff] [blame] | 233 | volatile word *p = (volatile word *)buf; |
| 234 | |
wdenk | c3c7f86 | 2004-06-09 14:47:54 +0000 | [diff] [blame] | 235 | while (len-- > 0) { |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 236 | SMC_outw(dev, *p++, offset); |
Wolfgang Denk | d52fb7e | 2006-03-11 22:53:33 +0100 | [diff] [blame] | 237 | barrier(); |
| 238 | *(volatile u32*)(0xc0000000); |
wdenk | c3c7f86 | 2004-06-09 14:47:54 +0000 | [diff] [blame] | 239 | } |
| 240 | } |
| 241 | #endif /* CONFIG_SMC_USE_IOFUNCS */ |
| 242 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 243 | /* |
| 244 | . A rather simple routine to print out a packet for debugging purposes. |
| 245 | */ |
| 246 | #if SMC_DEBUG > 2 |
| 247 | static void print_packet( byte *, int ); |
| 248 | #endif |
| 249 | |
| 250 | #define tx_done(dev) 1 |
| 251 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 252 | static int poll4int (struct eth_device *dev, byte mask, int timeout) |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 253 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 254 | int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ; |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 255 | int is_timeout = 0; |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 256 | word old_bank = SMC_inw (dev, BSR_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 257 | |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 258 | PRINTK2 ("Polling...\n"); |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 259 | SMC_SELECT_BANK (dev, 2); |
| 260 | while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) { |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 261 | if (get_timer (0) >= tmo) { |
| 262 | is_timeout = 1; |
| 263 | break; |
| 264 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 265 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 266 | |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 267 | /* restore old bank selection */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 268 | SMC_SELECT_BANK (dev, old_bank); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 269 | |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 270 | if (is_timeout) |
| 271 | return 1; |
| 272 | else |
| 273 | return 0; |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 274 | } |
| 275 | |
wdenk | 487778b | 2003-06-06 11:20:01 +0000 | [diff] [blame] | 276 | /* Only one release command at a time, please */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 277 | static inline void smc_wait_mmu_release_complete (struct eth_device *dev) |
wdenk | 487778b | 2003-06-06 11:20:01 +0000 | [diff] [blame] | 278 | { |
| 279 | int count = 0; |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 280 | |
wdenk | 487778b | 2003-06-06 11:20:01 +0000 | [diff] [blame] | 281 | /* assume bank 2 selected */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 282 | while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 283 | udelay (1); /* Wait until not busy */ |
| 284 | if (++count > 200) |
| 285 | break; |
wdenk | 487778b | 2003-06-06 11:20:01 +0000 | [diff] [blame] | 286 | } |
| 287 | } |
| 288 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 289 | /* |
| 290 | . Function: smc_reset( void ) |
| 291 | . Purpose: |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 292 | . This sets the SMC91111 chip to its normal state, hopefully from whatever |
| 293 | . mess that any other DOS driver has put it in. |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 294 | . |
| 295 | . Maybe I should reset more registers to defaults in here? SOFTRST should |
| 296 | . do that for me. |
| 297 | . |
| 298 | . Method: |
| 299 | . 1. send a SOFT RESET |
| 300 | . 2. wait for it to finish |
| 301 | . 3. enable autorelease mode |
| 302 | . 4. reset the memory management unit |
| 303 | . 5. clear all interrupts |
| 304 | . |
| 305 | */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 306 | static void smc_reset (struct eth_device *dev) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 307 | { |
wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 308 | PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 309 | |
| 310 | /* This resets the registers mostly to defaults, but doesn't |
| 311 | affect EEPROM. That seems unnecessary */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 312 | SMC_SELECT_BANK (dev, 0); |
| 313 | SMC_outw (dev, RCR_SOFTRST, RCR_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 314 | |
| 315 | /* Setup the Configuration Register */ |
| 316 | /* This is necessary because the CONFIG_REG is not affected */ |
| 317 | /* by a soft reset */ |
| 318 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 319 | SMC_SELECT_BANK (dev, 1); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 320 | #if defined(CONFIG_SMC91111_EXT_PHY) |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 321 | SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 322 | #else |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 323 | SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 324 | #endif |
| 325 | |
| 326 | |
| 327 | /* Release from possible power-down state */ |
| 328 | /* Configuration register is not affected by Soft Reset */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 329 | SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN, |
| 330 | CONFIG_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 331 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 332 | SMC_SELECT_BANK (dev, 0); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 333 | |
| 334 | /* this should pause enough for the chip to be happy */ |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 335 | udelay (10); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 336 | |
| 337 | /* Disable transmit and receive functionality */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 338 | SMC_outw (dev, RCR_CLEAR, RCR_REG); |
| 339 | SMC_outw (dev, TCR_CLEAR, TCR_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 340 | |
| 341 | /* set the control register */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 342 | SMC_SELECT_BANK (dev, 1); |
| 343 | SMC_outw (dev, CTL_DEFAULT, CTL_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 344 | |
| 345 | /* Reset the MMU */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 346 | SMC_SELECT_BANK (dev, 2); |
| 347 | smc_wait_mmu_release_complete (dev); |
| 348 | SMC_outw (dev, MC_RESET, MMU_CMD_REG); |
| 349 | while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 350 | udelay (1); /* Wait until not busy */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 351 | |
| 352 | /* Note: It doesn't seem that waiting for the MMU busy is needed here, |
| 353 | but this is a place where future chipsets _COULD_ break. Be wary |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 354 | of issuing another MMU command right after this */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 355 | |
| 356 | /* Disable all interrupts */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 357 | SMC_outb (dev, 0, IM_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 358 | } |
| 359 | |
| 360 | /* |
| 361 | . Function: smc_enable |
| 362 | . Purpose: let the chip talk to the outside work |
| 363 | . Method: |
| 364 | . 1. Enable the transmitter |
| 365 | . 2. Enable the receiver |
| 366 | . 3. Enable interrupts |
| 367 | */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 368 | static void smc_enable(struct eth_device *dev) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 369 | { |
wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 370 | PRINTK2("%s: smc_enable\n", SMC_DEV_NAME); |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 371 | SMC_SELECT_BANK( dev, 0 ); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 372 | /* see the header file for options in TCR/RCR DEFAULT*/ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 373 | SMC_outw( dev, TCR_DEFAULT, TCR_REG ); |
| 374 | SMC_outw( dev, RCR_DEFAULT, RCR_REG ); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 375 | |
| 376 | /* clear MII_DIS */ |
| 377 | /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */ |
| 378 | } |
| 379 | |
| 380 | /* |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 381 | . Function: smc_halt |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 382 | . Purpose: closes down the SMC91xxx chip. |
| 383 | . Method: |
| 384 | . 1. zero the interrupt mask |
| 385 | . 2. clear the enable receive flag |
| 386 | . 3. clear the enable xmit flags |
| 387 | . |
| 388 | . TODO: |
| 389 | . (1) maybe utilize power down mode. |
| 390 | . Why not yet? Because while the chip will go into power down mode, |
| 391 | . the manual says that it will wake up in response to any I/O requests |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 392 | . in the register space. Empirical results do not show this working. |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 393 | */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 394 | static void smc_halt(struct eth_device *dev) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 395 | { |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 396 | PRINTK2("%s: smc_halt\n", SMC_DEV_NAME); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 397 | |
| 398 | /* no more interrupts for me */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 399 | SMC_SELECT_BANK( dev, 2 ); |
| 400 | SMC_outb( dev, 0, IM_REG ); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 401 | |
| 402 | /* and tell the card to stay away from that nasty outside world */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 403 | SMC_SELECT_BANK( dev, 0 ); |
| 404 | SMC_outb( dev, RCR_CLEAR, RCR_REG ); |
| 405 | SMC_outb( dev, TCR_CLEAR, TCR_REG ); |
| 406 | |
Wolfgang Denk | 0afe519 | 2006-03-12 02:10:00 +0100 | [diff] [blame] | 407 | swap_to(FLASH); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 408 | } |
| 409 | |
| 410 | |
| 411 | /* |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 412 | . Function: smc_send(struct net_device * ) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 413 | . Purpose: |
| 414 | . This sends the actual packet to the SMC9xxx chip. |
| 415 | . |
| 416 | . Algorithm: |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 417 | . First, see if a saved_skb is available. |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 418 | . ( this should NOT be called if there is no 'saved_skb' |
| 419 | . Now, find the packet number that the chip allocated |
| 420 | . Point the data pointers at it in memory |
| 421 | . Set the length word in the chip's memory |
| 422 | . Dump the packet to chip memory |
| 423 | . Check if a last byte is needed ( odd length packet ) |
| 424 | . if so, set the control flag right |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 425 | . Tell the card to send it |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 426 | . Enable the transmit interrupt, so I know if it failed |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 427 | . Free the kernel data if I actually sent it. |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 428 | */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 429 | static int smc_send(struct eth_device *dev, volatile void *packet, |
| 430 | int packet_length) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 431 | { |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 432 | byte packet_no; |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 433 | byte *buf; |
| 434 | int length; |
| 435 | int numPages; |
| 436 | int try = 0; |
| 437 | int time_out; |
| 438 | byte status; |
wdenk | 518e2e1 | 2004-03-25 14:59:05 +0000 | [diff] [blame] | 439 | byte saved_pnr; |
| 440 | word saved_ptr; |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 441 | |
wdenk | 518e2e1 | 2004-03-25 14:59:05 +0000 | [diff] [blame] | 442 | /* save PTR and PNR registers before manipulation */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 443 | SMC_SELECT_BANK (dev, 2); |
| 444 | saved_pnr = SMC_inb( dev, PN_REG ); |
| 445 | saved_ptr = SMC_inw( dev, PTR_REG ); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 446 | |
wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 447 | PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 448 | |
| 449 | length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN; |
| 450 | |
| 451 | /* allocate memory |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 452 | ** The MMU wants the number of pages to be the number of 256 bytes |
| 453 | ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) ) |
| 454 | ** |
| 455 | ** The 91C111 ignores the size bits, but the code is left intact |
| 456 | ** for backwards and future compatibility. |
| 457 | ** |
| 458 | ** Pkt size for allocating is data length +6 (for additional status |
| 459 | ** words, length and ctl!) |
| 460 | ** |
| 461 | ** If odd size then last byte is included in this header. |
| 462 | */ |
| 463 | numPages = ((length & 0xfffe) + 6); |
| 464 | numPages >>= 8; /* Divide by 256 */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 465 | |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 466 | if (numPages > 7) { |
| 467 | printf ("%s: Far too big packet error. \n", SMC_DEV_NAME); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 468 | return 0; |
| 469 | } |
| 470 | |
| 471 | /* now, try to allocate the memory */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 472 | SMC_SELECT_BANK (dev, 2); |
| 473 | SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 474 | |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 475 | /* FIXME: the ALLOC_INT bit never gets set * |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 476 | * so the following will always give a * |
| 477 | * memory allocation error. * |
| 478 | * same code works in armboot though * |
wdenk | dc7c9a1 | 2003-03-26 06:55:25 +0000 | [diff] [blame] | 479 | * -ro |
| 480 | */ |
| 481 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 482 | again: |
| 483 | try++; |
| 484 | time_out = MEMORY_WAIT_TIME; |
| 485 | do { |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 486 | status = SMC_inb (dev, SMC91111_INT_REG); |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 487 | if (status & IM_ALLOC_INT) { |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 488 | /* acknowledge the interrupt */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 489 | SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 490 | break; |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 491 | } |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 492 | } while (--time_out); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 493 | |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 494 | if (!time_out) { |
| 495 | PRINTK2 ("%s: memory allocation, try %d failed ...\n", |
| 496 | SMC_DEV_NAME, try); |
| 497 | if (try < SMC_ALLOC_MAX_TRY) |
| 498 | goto again; |
| 499 | else |
| 500 | return 0; |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 501 | } |
| 502 | |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 503 | PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", |
| 504 | SMC_DEV_NAME, try); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 505 | |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 506 | buf = (byte *) packet; |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 507 | |
| 508 | /* If I get here, I _know_ there is a packet slot waiting for me */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 509 | packet_no = SMC_inb (dev, AR_REG); |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 510 | if (packet_no & AR_FAILED) { |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 511 | /* or isn't there? BAD CHIP! */ |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 512 | printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 513 | return 0; |
| 514 | } |
| 515 | |
| 516 | /* we have a packet address, so tell the card to use it */ |
wdenk | 1f6d425 | 2004-11-02 13:00:33 +0000 | [diff] [blame] | 517 | #ifndef CONFIG_XAENIAX |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 518 | SMC_outb (dev, packet_no, PN_REG); |
wdenk | 1f6d425 | 2004-11-02 13:00:33 +0000 | [diff] [blame] | 519 | #else |
| 520 | /* On Xaeniax board, we can't use SMC_outb here because that way |
| 521 | * the Allocate MMU command will end up written to the command register |
| 522 | * as well, which will lead to a problem. |
| 523 | */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 524 | SMC_outl (dev, packet_no << 16, 0); |
wdenk | 1f6d425 | 2004-11-02 13:00:33 +0000 | [diff] [blame] | 525 | #endif |
wdenk | b79a11c | 2004-03-25 15:14:43 +0000 | [diff] [blame] | 526 | /* do not write new ptr value if Write data fifo not empty */ |
| 527 | while ( saved_ptr & PTR_NOTEMPTY ) |
wdenk | 518e2e1 | 2004-03-25 14:59:05 +0000 | [diff] [blame] | 528 | printf ("Write data fifo not empty!\n"); |
| 529 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 530 | /* point to the beginning of the packet */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 531 | SMC_outw (dev, PTR_AUTOINC, PTR_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 532 | |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 533 | PRINTK3 ("%s: Trying to xmit packet of length %x\n", |
| 534 | SMC_DEV_NAME, length); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 535 | |
| 536 | #if SMC_DEBUG > 2 |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 537 | printf ("Transmitting Packet\n"); |
| 538 | print_packet (buf, length); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 539 | #endif |
| 540 | |
| 541 | /* send the packet length ( +6 for status, length and ctl byte ) |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 542 | and the status word ( set to zeros ) */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 543 | #ifdef USE_32_BIT |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 544 | SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 545 | #else |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 546 | SMC_outw (dev, 0, SMC91111_DATA_REG); |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 547 | /* send the packet length ( +6 for status words, length, and ctl */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 548 | SMC_outw (dev, (length + 6), SMC91111_DATA_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 549 | #endif |
| 550 | |
| 551 | /* send the actual data |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 552 | . I _think_ it's faster to send the longs first, and then |
| 553 | . mop up by sending the last word. It depends heavily |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 554 | . on alignment, at least on the 486. Maybe it would be |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 555 | . a good idea to check which is optimal? But that could take |
| 556 | . almost as much time as is saved? |
| 557 | */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 558 | #ifdef USE_32_BIT |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 559 | SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2); |
wdenk | bb310d4 | 2004-11-22 22:20:07 +0000 | [diff] [blame] | 560 | #ifndef CONFIG_XAENIAX |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 561 | if (length & 0x2) |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 562 | SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))), |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 563 | SMC91111_DATA_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 564 | #else |
wdenk | bb310d4 | 2004-11-22 22:20:07 +0000 | [diff] [blame] | 565 | /* On XANEIAX, we can only use 32-bit writes, so we need to handle |
| 566 | * unaligned tail part specially. The standard code doesn't work. |
| 567 | */ |
| 568 | if ((length & 3) == 3) { |
| 569 | u16 * ptr = (u16*) &buf[length-3]; |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 570 | SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16), |
wdenk | bb310d4 | 2004-11-22 22:20:07 +0000 | [diff] [blame] | 571 | SMC91111_DATA_REG); |
| 572 | } else if ((length & 2) == 2) { |
| 573 | u16 * ptr = (u16*) &buf[length-2]; |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 574 | SMC_outl(dev, *ptr, SMC91111_DATA_REG); |
wdenk | bb310d4 | 2004-11-22 22:20:07 +0000 | [diff] [blame] | 575 | } else if (length & 1) { |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 576 | SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG); |
wdenk | bb310d4 | 2004-11-22 22:20:07 +0000 | [diff] [blame] | 577 | } else { |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 578 | SMC_outl(dev, 0, SMC91111_DATA_REG); |
wdenk | bb310d4 | 2004-11-22 22:20:07 +0000 | [diff] [blame] | 579 | } |
| 580 | #endif |
| 581 | #else |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 582 | SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 583 | #endif /* USE_32_BIT */ |
| 584 | |
wdenk | bb310d4 | 2004-11-22 22:20:07 +0000 | [diff] [blame] | 585 | #ifndef CONFIG_XAENIAX |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 586 | /* Send the last byte, if there is one. */ |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 587 | if ((length & 1) == 0) { |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 588 | SMC_outw (dev, 0, SMC91111_DATA_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 589 | } else { |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 590 | SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 591 | } |
wdenk | bb310d4 | 2004-11-22 22:20:07 +0000 | [diff] [blame] | 592 | #endif |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 593 | |
| 594 | /* and let the chipset deal with it */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 595 | SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 596 | |
| 597 | /* poll for TX INT */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 598 | /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */ |
wdenk | 518e2e1 | 2004-03-25 14:59:05 +0000 | [diff] [blame] | 599 | /* poll for TX_EMPTY INT - autorelease enabled */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 600 | if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) { |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 601 | /* sending failed */ |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 602 | PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 603 | |
| 604 | /* release packet */ |
wdenk | 518e2e1 | 2004-03-25 14:59:05 +0000 | [diff] [blame] | 605 | /* no need to release, MMU does that now */ |
wdenk | 1f6d425 | 2004-11-02 13:00:33 +0000 | [diff] [blame] | 606 | #ifdef CONFIG_XAENIAX |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 607 | SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); |
wdenk | 1f6d425 | 2004-11-02 13:00:33 +0000 | [diff] [blame] | 608 | #endif |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 609 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 610 | /* wait for MMU getting ready (low) */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 611 | while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 612 | udelay (10); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 613 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 614 | |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 615 | PRINTK2 ("MMU ready\n"); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 616 | |
| 617 | |
| 618 | return 0; |
| 619 | } else { |
| 620 | /* ack. int */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 621 | SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG); |
wdenk | 518e2e1 | 2004-03-25 14:59:05 +0000 | [diff] [blame] | 622 | /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */ |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 623 | PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, |
| 624 | length); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 625 | |
| 626 | /* release packet */ |
wdenk | 518e2e1 | 2004-03-25 14:59:05 +0000 | [diff] [blame] | 627 | /* no need to release, MMU does that now */ |
wdenk | 1f6d425 | 2004-11-02 13:00:33 +0000 | [diff] [blame] | 628 | #ifdef CONFIG_XAENIAX |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 629 | SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); |
wdenk | 1f6d425 | 2004-11-02 13:00:33 +0000 | [diff] [blame] | 630 | #endif |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 631 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 632 | /* wait for MMU getting ready (low) */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 633 | while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 634 | udelay (10); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 635 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 636 | |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 637 | PRINTK2 ("MMU ready\n"); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 638 | |
| 639 | |
| 640 | } |
| 641 | |
wdenk | 518e2e1 | 2004-03-25 14:59:05 +0000 | [diff] [blame] | 642 | /* restore previously saved registers */ |
wdenk | 1f6d425 | 2004-11-02 13:00:33 +0000 | [diff] [blame] | 643 | #ifndef CONFIG_XAENIAX |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 644 | SMC_outb( dev, saved_pnr, PN_REG ); |
wdenk | 1f6d425 | 2004-11-02 13:00:33 +0000 | [diff] [blame] | 645 | #else |
| 646 | /* On Xaeniax board, we can't use SMC_outb here because that way |
| 647 | * the Allocate MMU command will end up written to the command register |
| 648 | * as well, which will lead to a problem. |
| 649 | */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 650 | SMC_outl(dev, saved_pnr << 16, 0); |
wdenk | 1f6d425 | 2004-11-02 13:00:33 +0000 | [diff] [blame] | 651 | #endif |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 652 | SMC_outw( dev, saved_ptr, PTR_REG ); |
wdenk | 518e2e1 | 2004-03-25 14:59:05 +0000 | [diff] [blame] | 653 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 654 | return length; |
| 655 | } |
| 656 | |
Thomas Chou | 1ca6d0d | 2010-10-06 09:16:10 +0800 | [diff] [blame] | 657 | static int smc_write_hwaddr(struct eth_device *dev) |
| 658 | { |
| 659 | int i; |
| 660 | |
| 661 | swap_to(ETHERNET); |
| 662 | SMC_SELECT_BANK (dev, 1); |
| 663 | #ifdef USE_32_BIT |
| 664 | for (i = 0; i < 6; i += 2) { |
| 665 | word address; |
| 666 | |
| 667 | address = dev->enetaddr[i + 1] << 8; |
| 668 | address |= dev->enetaddr[i]; |
| 669 | SMC_outw(dev, address, (ADDR0_REG + i)); |
| 670 | } |
| 671 | #else |
| 672 | for (i = 0; i < 6; i++) |
| 673 | SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i)); |
| 674 | #endif |
| 675 | swap_to(FLASH); |
| 676 | return 0; |
| 677 | } |
| 678 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 679 | /* |
| 680 | * Open and Initialize the board |
| 681 | * |
| 682 | * Set up everything, reset the card, etc .. |
| 683 | * |
| 684 | */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 685 | static int smc_init(struct eth_device *dev, bd_t *bd) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 686 | { |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 687 | swap_to(ETHERNET); |
| 688 | |
| 689 | PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 690 | |
| 691 | /* reset the hardware */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 692 | smc_reset (dev); |
| 693 | smc_enable (dev); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 694 | |
| 695 | /* Configure the PHY */ |
| 696 | #ifndef CONFIG_SMC91111_EXT_PHY |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 697 | smc_phy_configure (dev); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 698 | #endif |
| 699 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 700 | /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 701 | /* SMC_SELECT_BANK(dev, 0); */ |
| 702 | /* SMC_outw(dev, 0, RPC_REG); */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 703 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 704 | printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr); |
| 705 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 706 | return 0; |
| 707 | } |
| 708 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 709 | /*------------------------------------------------------------- |
| 710 | . |
| 711 | . smc_rcv - receive a packet from the card |
| 712 | . |
| 713 | . There is ( at least ) a packet waiting to be read from |
| 714 | . chip-memory. |
| 715 | . |
| 716 | . o Read the status |
| 717 | . o If an error, record it |
| 718 | . o otherwise, read in the packet |
| 719 | -------------------------------------------------------------- |
| 720 | */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 721 | static int smc_rcv(struct eth_device *dev) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 722 | { |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 723 | int packet_number; |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 724 | word status; |
| 725 | word packet_length; |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 726 | int is_error = 0; |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 727 | #ifdef USE_32_BIT |
| 728 | dword stat_len; |
| 729 | #endif |
wdenk | 518e2e1 | 2004-03-25 14:59:05 +0000 | [diff] [blame] | 730 | byte saved_pnr; |
| 731 | word saved_ptr; |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 732 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 733 | SMC_SELECT_BANK(dev, 2); |
wdenk | 518e2e1 | 2004-03-25 14:59:05 +0000 | [diff] [blame] | 734 | /* save PTR and PTR registers */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 735 | saved_pnr = SMC_inb( dev, PN_REG ); |
| 736 | saved_ptr = SMC_inw( dev, PTR_REG ); |
wdenk | 518e2e1 | 2004-03-25 14:59:05 +0000 | [diff] [blame] | 737 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 738 | packet_number = SMC_inw( dev, RXFIFO_REG ); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 739 | |
| 740 | if ( packet_number & RXFIFO_REMPTY ) { |
| 741 | |
| 742 | return 0; |
| 743 | } |
| 744 | |
wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 745 | PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 746 | /* start reading from the start of the packet */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 747 | SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG ); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 748 | |
| 749 | /* First two words are status and packet_length */ |
| 750 | #ifdef USE_32_BIT |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 751 | stat_len = SMC_inl(dev, SMC91111_DATA_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 752 | status = stat_len & 0xffff; |
| 753 | packet_length = stat_len >> 16; |
| 754 | #else |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 755 | status = SMC_inw( dev, SMC91111_DATA_REG ); |
| 756 | packet_length = SMC_inw( dev, SMC91111_DATA_REG ); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 757 | #endif |
| 758 | |
| 759 | packet_length &= 0x07ff; /* mask off top bits */ |
| 760 | |
| 761 | PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length ); |
| 762 | |
| 763 | if ( !(status & RS_ERRORS ) ){ |
| 764 | /* Adjust for having already read the first two words */ |
| 765 | packet_length -= 4; /*4; */ |
| 766 | |
| 767 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 768 | /* set odd length for bug in LAN91C111, */ |
| 769 | /* which never sets RS_ODDFRAME */ |
| 770 | /* TODO ? */ |
| 771 | |
| 772 | |
| 773 | #ifdef USE_32_BIT |
| 774 | PRINTK3(" Reading %d dwords (and %d bytes) \n", |
| 775 | packet_length >> 2, packet_length & 3 ); |
| 776 | /* QUESTION: Like in the TX routine, do I want |
| 777 | to send the DWORDs or the bytes first, or some |
| 778 | mixture. A mixture might improve already slow PIO |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 779 | performance */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 780 | SMC_insl( dev, SMC91111_DATA_REG, NetRxPackets[0], |
| 781 | packet_length >> 2 ); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 782 | /* read the left over bytes */ |
| 783 | if (packet_length & 3) { |
| 784 | int i; |
| 785 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 786 | byte *tail = (byte *)(NetRxPackets[0] + |
| 787 | (packet_length & ~3)); |
| 788 | dword leftover = SMC_inl(dev, SMC91111_DATA_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 789 | for (i=0; i<(packet_length & 3); i++) |
| 790 | *tail++ = (byte) (leftover >> (8*i)) & 0xff; |
| 791 | } |
| 792 | #else |
| 793 | PRINTK3(" Reading %d words and %d byte(s) \n", |
| 794 | (packet_length >> 1 ), packet_length & 1 ); |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 795 | SMC_insw(dev, SMC91111_DATA_REG , NetRxPackets[0], |
| 796 | packet_length >> 1); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 797 | |
| 798 | #endif /* USE_32_BIT */ |
| 799 | |
| 800 | #if SMC_DEBUG > 2 |
| 801 | printf("Receiving Packet\n"); |
| 802 | print_packet( NetRxPackets[0], packet_length ); |
| 803 | #endif |
| 804 | } else { |
| 805 | /* error ... */ |
| 806 | /* TODO ? */ |
| 807 | is_error = 1; |
| 808 | } |
| 809 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 810 | while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 811 | udelay(1); /* Wait until not busy */ |
| 812 | |
| 813 | /* error or good, tell the card to get rid of this packet */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 814 | SMC_outw( dev, MC_RELEASE, MMU_CMD_REG ); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 815 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 816 | while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 817 | udelay(1); /* Wait until not busy */ |
| 818 | |
wdenk | 518e2e1 | 2004-03-25 14:59:05 +0000 | [diff] [blame] | 819 | /* restore saved registers */ |
wdenk | 1f6d425 | 2004-11-02 13:00:33 +0000 | [diff] [blame] | 820 | #ifndef CONFIG_XAENIAX |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 821 | SMC_outb( dev, saved_pnr, PN_REG ); |
wdenk | 1f6d425 | 2004-11-02 13:00:33 +0000 | [diff] [blame] | 822 | #else |
| 823 | /* On Xaeniax board, we can't use SMC_outb here because that way |
| 824 | * the Allocate MMU command will end up written to the command register |
| 825 | * as well, which will lead to a problem. |
| 826 | */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 827 | SMC_outl( dev, saved_pnr << 16, 0); |
wdenk | 1f6d425 | 2004-11-02 13:00:33 +0000 | [diff] [blame] | 828 | #endif |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 829 | SMC_outw( dev, saved_ptr, PTR_REG ); |
wdenk | 518e2e1 | 2004-03-25 14:59:05 +0000 | [diff] [blame] | 830 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 831 | if (!is_error) { |
| 832 | /* Pass the packet up to the protocol layers. */ |
| 833 | NetReceive(NetRxPackets[0], packet_length); |
| 834 | return packet_length; |
| 835 | } else { |
| 836 | return 0; |
| 837 | } |
| 838 | |
| 839 | } |
| 840 | |
| 841 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 842 | #if 0 |
| 843 | /*------------------------------------------------------------ |
| 844 | . Modify a bit in the LAN91C111 register set |
| 845 | .-------------------------------------------------------------*/ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 846 | static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 847 | unsigned int bit, int val) |
| 848 | { |
| 849 | word regval; |
| 850 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 851 | SMC_SELECT_BANK( dev, bank ); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 852 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 853 | regval = SMC_inw( dev, reg ); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 854 | if (val) |
| 855 | regval |= bit; |
| 856 | else |
| 857 | regval &= ~bit; |
| 858 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 859 | SMC_outw( dev, regval, 0 ); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 860 | return(regval); |
| 861 | } |
| 862 | |
| 863 | |
| 864 | /*------------------------------------------------------------ |
| 865 | . Retrieve a bit in the LAN91C111 register set |
| 866 | .-------------------------------------------------------------*/ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 867 | static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 868 | { |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 869 | SMC_SELECT_BANK( dev, bank ); |
| 870 | if ( SMC_inw( dev, reg ) & bit) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 871 | return(1); |
| 872 | else |
| 873 | return(0); |
| 874 | } |
| 875 | |
| 876 | |
| 877 | /*------------------------------------------------------------ |
| 878 | . Modify a LAN91C111 register (word access only) |
| 879 | .-------------------------------------------------------------*/ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 880 | static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 881 | { |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 882 | SMC_SELECT_BANK( dev, bank ); |
| 883 | SMC_outw( dev, val, reg ); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 884 | } |
| 885 | |
| 886 | |
| 887 | /*------------------------------------------------------------ |
| 888 | . Retrieve a LAN91C111 register (word access only) |
| 889 | .-------------------------------------------------------------*/ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 890 | static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 891 | { |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 892 | SMC_SELECT_BANK( dev, bank ); |
| 893 | return(SMC_inw( dev, reg )); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 894 | } |
| 895 | |
| 896 | #endif /* 0 */ |
| 897 | |
| 898 | /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */ |
| 899 | |
| 900 | #if (SMC_DEBUG > 2 ) |
| 901 | |
| 902 | /*------------------------------------------------------------ |
| 903 | . Debugging function for viewing MII Management serial bitstream |
| 904 | .-------------------------------------------------------------*/ |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 905 | static void smc_dump_mii_stream (byte * bits, int size) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 906 | { |
| 907 | int i; |
| 908 | |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 909 | printf ("BIT#:"); |
| 910 | for (i = 0; i < size; ++i) { |
| 911 | printf ("%d", i % 10); |
| 912 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 913 | |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 914 | printf ("\nMDOE:"); |
| 915 | for (i = 0; i < size; ++i) { |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 916 | if (bits[i] & MII_MDOE) |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 917 | printf ("1"); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 918 | else |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 919 | printf ("0"); |
| 920 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 921 | |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 922 | printf ("\nMDO :"); |
| 923 | for (i = 0; i < size; ++i) { |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 924 | if (bits[i] & MII_MDO) |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 925 | printf ("1"); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 926 | else |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 927 | printf ("0"); |
| 928 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 929 | |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 930 | printf ("\nMDI :"); |
| 931 | for (i = 0; i < size; ++i) { |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 932 | if (bits[i] & MII_MDI) |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 933 | printf ("1"); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 934 | else |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 935 | printf ("0"); |
| 936 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 937 | |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 938 | printf ("\n"); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 939 | } |
| 940 | #endif |
| 941 | |
| 942 | /*------------------------------------------------------------ |
| 943 | . Reads a register from the MII Management serial interface |
| 944 | .-------------------------------------------------------------*/ |
| 945 | #ifndef CONFIG_SMC91111_EXT_PHY |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 946 | static word smc_read_phy_register (struct eth_device *dev, byte phyreg) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 947 | { |
| 948 | int oldBank; |
| 949 | int i; |
| 950 | byte mask; |
| 951 | word mii_reg; |
| 952 | byte bits[64]; |
| 953 | int clk_idx = 0; |
| 954 | int input_idx; |
| 955 | word phydata; |
| 956 | byte phyaddr = SMC_PHY_ADDR; |
| 957 | |
| 958 | /* 32 consecutive ones on MDO to establish sync */ |
| 959 | for (i = 0; i < 32; ++i) |
| 960 | bits[clk_idx++] = MII_MDOE | MII_MDO; |
| 961 | |
| 962 | /* Start code <01> */ |
| 963 | bits[clk_idx++] = MII_MDOE; |
| 964 | bits[clk_idx++] = MII_MDOE | MII_MDO; |
| 965 | |
| 966 | /* Read command <10> */ |
| 967 | bits[clk_idx++] = MII_MDOE | MII_MDO; |
| 968 | bits[clk_idx++] = MII_MDOE; |
| 969 | |
| 970 | /* Output the PHY address, msb first */ |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 971 | mask = (byte) 0x10; |
| 972 | for (i = 0; i < 5; ++i) { |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 973 | if (phyaddr & mask) |
| 974 | bits[clk_idx++] = MII_MDOE | MII_MDO; |
| 975 | else |
| 976 | bits[clk_idx++] = MII_MDOE; |
| 977 | |
| 978 | /* Shift to next lowest bit */ |
| 979 | mask >>= 1; |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 980 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 981 | |
| 982 | /* Output the phy register number, msb first */ |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 983 | mask = (byte) 0x10; |
| 984 | for (i = 0; i < 5; ++i) { |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 985 | if (phyreg & mask) |
| 986 | bits[clk_idx++] = MII_MDOE | MII_MDO; |
| 987 | else |
| 988 | bits[clk_idx++] = MII_MDOE; |
| 989 | |
| 990 | /* Shift to next lowest bit */ |
| 991 | mask >>= 1; |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 992 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 993 | |
| 994 | /* Tristate and turnaround (2 bit times) */ |
| 995 | bits[clk_idx++] = 0; |
| 996 | /*bits[clk_idx++] = 0; */ |
| 997 | |
| 998 | /* Input starts at this bit time */ |
| 999 | input_idx = clk_idx; |
| 1000 | |
| 1001 | /* Will input 16 bits */ |
| 1002 | for (i = 0; i < 16; ++i) |
| 1003 | bits[clk_idx++] = 0; |
| 1004 | |
| 1005 | /* Final clock bit */ |
| 1006 | bits[clk_idx++] = 0; |
| 1007 | |
| 1008 | /* Save the current bank */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1009 | oldBank = SMC_inw (dev, BANK_SELECT); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1010 | |
| 1011 | /* Select bank 3 */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1012 | SMC_SELECT_BANK (dev, 3); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1013 | |
| 1014 | /* Get the current MII register value */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1015 | mii_reg = SMC_inw (dev, MII_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1016 | |
| 1017 | /* Turn off all MII Interface bits */ |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1018 | mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1019 | |
| 1020 | /* Clock all 64 cycles */ |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1021 | for (i = 0; i < sizeof bits; ++i) { |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1022 | /* Clock Low - output data */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1023 | SMC_outw (dev, mii_reg | bits[i], MII_REG); |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1024 | udelay (SMC_PHY_CLOCK_DELAY); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1025 | |
| 1026 | |
| 1027 | /* Clock Hi - input data */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1028 | SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1029 | udelay (SMC_PHY_CLOCK_DELAY); |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1030 | bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1031 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1032 | |
| 1033 | /* Return to idle state */ |
| 1034 | /* Set clock to low, data to low, and output tristated */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1035 | SMC_outw (dev, mii_reg, MII_REG); |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1036 | udelay (SMC_PHY_CLOCK_DELAY); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1037 | |
| 1038 | /* Restore original bank select */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1039 | SMC_SELECT_BANK (dev, oldBank); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1040 | |
| 1041 | /* Recover input data */ |
| 1042 | phydata = 0; |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1043 | for (i = 0; i < 16; ++i) { |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1044 | phydata <<= 1; |
| 1045 | |
| 1046 | if (bits[input_idx++] & MII_MDI) |
| 1047 | phydata |= 0x0001; |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1048 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1049 | |
| 1050 | #if (SMC_DEBUG > 2 ) |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1051 | printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1052 | phyaddr, phyreg, phydata); |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1053 | smc_dump_mii_stream (bits, sizeof bits); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1054 | #endif |
| 1055 | |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1056 | return (phydata); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1057 | } |
| 1058 | |
| 1059 | |
| 1060 | /*------------------------------------------------------------ |
| 1061 | . Writes a register to the MII Management serial interface |
| 1062 | .-------------------------------------------------------------*/ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1063 | static void smc_write_phy_register (struct eth_device *dev, byte phyreg, |
| 1064 | word phydata) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1065 | { |
| 1066 | int oldBank; |
| 1067 | int i; |
| 1068 | word mask; |
| 1069 | word mii_reg; |
| 1070 | byte bits[65]; |
| 1071 | int clk_idx = 0; |
| 1072 | byte phyaddr = SMC_PHY_ADDR; |
| 1073 | |
| 1074 | /* 32 consecutive ones on MDO to establish sync */ |
| 1075 | for (i = 0; i < 32; ++i) |
| 1076 | bits[clk_idx++] = MII_MDOE | MII_MDO; |
| 1077 | |
| 1078 | /* Start code <01> */ |
| 1079 | bits[clk_idx++] = MII_MDOE; |
| 1080 | bits[clk_idx++] = MII_MDOE | MII_MDO; |
| 1081 | |
| 1082 | /* Write command <01> */ |
| 1083 | bits[clk_idx++] = MII_MDOE; |
| 1084 | bits[clk_idx++] = MII_MDOE | MII_MDO; |
| 1085 | |
| 1086 | /* Output the PHY address, msb first */ |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1087 | mask = (byte) 0x10; |
| 1088 | for (i = 0; i < 5; ++i) { |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1089 | if (phyaddr & mask) |
| 1090 | bits[clk_idx++] = MII_MDOE | MII_MDO; |
| 1091 | else |
| 1092 | bits[clk_idx++] = MII_MDOE; |
| 1093 | |
| 1094 | /* Shift to next lowest bit */ |
| 1095 | mask >>= 1; |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1096 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1097 | |
| 1098 | /* Output the phy register number, msb first */ |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1099 | mask = (byte) 0x10; |
| 1100 | for (i = 0; i < 5; ++i) { |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1101 | if (phyreg & mask) |
| 1102 | bits[clk_idx++] = MII_MDOE | MII_MDO; |
| 1103 | else |
| 1104 | bits[clk_idx++] = MII_MDOE; |
| 1105 | |
| 1106 | /* Shift to next lowest bit */ |
| 1107 | mask >>= 1; |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1108 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1109 | |
| 1110 | /* Tristate and turnaround (2 bit times) */ |
| 1111 | bits[clk_idx++] = 0; |
| 1112 | bits[clk_idx++] = 0; |
| 1113 | |
| 1114 | /* Write out 16 bits of data, msb first */ |
| 1115 | mask = 0x8000; |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1116 | for (i = 0; i < 16; ++i) { |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1117 | if (phydata & mask) |
| 1118 | bits[clk_idx++] = MII_MDOE | MII_MDO; |
| 1119 | else |
| 1120 | bits[clk_idx++] = MII_MDOE; |
| 1121 | |
| 1122 | /* Shift to next lowest bit */ |
| 1123 | mask >>= 1; |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1124 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1125 | |
| 1126 | /* Final clock bit (tristate) */ |
| 1127 | bits[clk_idx++] = 0; |
| 1128 | |
| 1129 | /* Save the current bank */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1130 | oldBank = SMC_inw (dev, BANK_SELECT); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1131 | |
| 1132 | /* Select bank 3 */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1133 | SMC_SELECT_BANK (dev, 3); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1134 | |
| 1135 | /* Get the current MII register value */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1136 | mii_reg = SMC_inw (dev, MII_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1137 | |
| 1138 | /* Turn off all MII Interface bits */ |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1139 | mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1140 | |
| 1141 | /* Clock all cycles */ |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1142 | for (i = 0; i < sizeof bits; ++i) { |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1143 | /* Clock Low - output data */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1144 | SMC_outw (dev, mii_reg | bits[i], MII_REG); |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1145 | udelay (SMC_PHY_CLOCK_DELAY); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1146 | |
| 1147 | |
| 1148 | /* Clock Hi - input data */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1149 | SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1150 | udelay (SMC_PHY_CLOCK_DELAY); |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1151 | bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1152 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1153 | |
| 1154 | /* Return to idle state */ |
| 1155 | /* Set clock to low, data to low, and output tristated */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1156 | SMC_outw (dev, mii_reg, MII_REG); |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1157 | udelay (SMC_PHY_CLOCK_DELAY); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1158 | |
| 1159 | /* Restore original bank select */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1160 | SMC_SELECT_BANK (dev, oldBank); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1161 | |
| 1162 | #if (SMC_DEBUG > 2 ) |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1163 | printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1164 | phyaddr, phyreg, phydata); |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1165 | smc_dump_mii_stream (bits, sizeof bits); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1166 | #endif |
| 1167 | } |
| 1168 | #endif /* !CONFIG_SMC91111_EXT_PHY */ |
| 1169 | |
| 1170 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1171 | /*------------------------------------------------------------ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1172 | . Configures the specified PHY using Autonegotiation. Calls |
| 1173 | . smc_phy_fixed() if the user has requested a certain config. |
| 1174 | .-------------------------------------------------------------*/ |
| 1175 | #ifndef CONFIG_SMC91111_EXT_PHY |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1176 | static void smc_phy_configure (struct eth_device *dev) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1177 | { |
| 1178 | int timeout; |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1179 | word my_phy_caps; /* My PHY capabilities */ |
| 1180 | word my_ad_caps; /* My Advertised capabilities */ |
| 1181 | word status = 0; /*;my status = 0 */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1182 | |
wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 1183 | PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1184 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1185 | /* Reset the PHY, setting all other bits to zero */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1186 | smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1187 | |
| 1188 | /* Wait for the reset to complete, or time out */ |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1189 | timeout = 6; /* Wait up to 3 seconds */ |
| 1190 | while (timeout--) { |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1191 | if (!(smc_read_phy_register (dev, PHY_CNTL_REG) |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1192 | & PHY_CNTL_RST)) { |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1193 | /* reset complete */ |
| 1194 | break; |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1195 | } |
| 1196 | |
Mike Frysinger | 6502949 | 2012-03-05 13:46:51 +0000 | [diff] [blame] | 1197 | mdelay(500); /* wait 500 millisecs */ |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1198 | } |
| 1199 | |
| 1200 | if (timeout < 1) { |
| 1201 | printf ("%s:PHY reset timed out\n", SMC_DEV_NAME); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1202 | goto smc_phy_configure_exit; |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1203 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1204 | |
| 1205 | /* Read PHY Register 18, Status Output */ |
| 1206 | /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */ |
| 1207 | |
| 1208 | /* Enable PHY Interrupts (for register 18) */ |
| 1209 | /* Interrupts listed here are disabled */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1210 | smc_write_phy_register (dev, PHY_MASK_REG, 0xffff); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1211 | |
| 1212 | /* Configure the Receive/Phy Control register */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1213 | SMC_SELECT_BANK (dev, 0); |
| 1214 | SMC_outw (dev, RPC_DEFAULT, RPC_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1215 | |
| 1216 | /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1217 | my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG); |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1218 | my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1219 | |
| 1220 | if (my_phy_caps & PHY_STAT_CAP_T4) |
| 1221 | my_ad_caps |= PHY_AD_T4; |
| 1222 | |
| 1223 | if (my_phy_caps & PHY_STAT_CAP_TXF) |
| 1224 | my_ad_caps |= PHY_AD_TX_FDX; |
| 1225 | |
| 1226 | if (my_phy_caps & PHY_STAT_CAP_TXH) |
| 1227 | my_ad_caps |= PHY_AD_TX_HDX; |
| 1228 | |
| 1229 | if (my_phy_caps & PHY_STAT_CAP_TF) |
| 1230 | my_ad_caps |= PHY_AD_10_FDX; |
| 1231 | |
| 1232 | if (my_phy_caps & PHY_STAT_CAP_TH) |
| 1233 | my_ad_caps |= PHY_AD_10_HDX; |
| 1234 | |
| 1235 | /* Update our Auto-Neg Advertisement Register */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1236 | smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1237 | |
wdenk | 518e2e1 | 2004-03-25 14:59:05 +0000 | [diff] [blame] | 1238 | /* Read the register back. Without this, it appears that when */ |
| 1239 | /* auto-negotiation is restarted, sometimes it isn't ready and */ |
| 1240 | /* the link does not come up. */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1241 | smc_read_phy_register(dev, PHY_AD_REG); |
wdenk | 518e2e1 | 2004-03-25 14:59:05 +0000 | [diff] [blame] | 1242 | |
wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 1243 | PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps); |
| 1244 | PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1245 | |
| 1246 | /* Restart auto-negotiation process in order to advertise my caps */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1247 | smc_write_phy_register (dev, PHY_CNTL_REG, |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1248 | PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1249 | |
| 1250 | /* Wait for the auto-negotiation to complete. This may take from */ |
| 1251 | /* 2 to 3 seconds. */ |
| 1252 | /* Wait for the reset to complete, or time out */ |
wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 1253 | timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2; |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1254 | while (timeout--) { |
wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 1255 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1256 | status = smc_read_phy_register (dev, PHY_STAT_REG); |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1257 | if (status & PHY_STAT_ANEG_ACK) { |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1258 | /* auto-negotiate complete */ |
| 1259 | break; |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1260 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1261 | |
Mike Frysinger | 6502949 | 2012-03-05 13:46:51 +0000 | [diff] [blame] | 1262 | mdelay(500); /* wait 500 millisecs */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1263 | |
| 1264 | /* Restart auto-negotiation if remote fault */ |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1265 | if (status & PHY_STAT_REM_FLT) { |
wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 1266 | printf ("%s: PHY remote fault detected\n", |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1267 | SMC_DEV_NAME); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1268 | |
| 1269 | /* Restart auto-negotiation */ |
wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 1270 | printf ("%s: PHY restarting auto-negotiation\n", |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1271 | SMC_DEV_NAME); |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1272 | smc_write_phy_register (dev, PHY_CNTL_REG, |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1273 | PHY_CNTL_ANEG_EN | |
| 1274 | PHY_CNTL_ANEG_RST | |
| 1275 | PHY_CNTL_SPEED | |
| 1276 | PHY_CNTL_DPLX); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1277 | } |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1278 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1279 | |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1280 | if (timeout < 1) { |
wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 1281 | printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME); |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1282 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1283 | |
| 1284 | /* Fail if we detected an auto-negotiate remote fault */ |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1285 | if (status & PHY_STAT_REM_FLT) { |
wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 1286 | printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME); |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1287 | } |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1288 | |
| 1289 | /* Re-Configure the Receive/Phy Control register */ |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1290 | SMC_outw (dev, RPC_DEFAULT, RPC_REG); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1291 | |
wdenk | 2623813 | 2004-07-09 22:51:01 +0000 | [diff] [blame] | 1292 | smc_phy_configure_exit: ; |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1293 | |
| 1294 | } |
| 1295 | #endif /* !CONFIG_SMC91111_EXT_PHY */ |
| 1296 | |
| 1297 | |
| 1298 | #if SMC_DEBUG > 2 |
| 1299 | static void print_packet( byte * buf, int length ) |
| 1300 | { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 1301 | int i; |
| 1302 | int remainder; |
| 1303 | int lines; |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1304 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 1305 | printf("Packet of length %d \n", length ); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1306 | |
| 1307 | #if SMC_DEBUG > 3 |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 1308 | lines = length / 16; |
| 1309 | remainder = length % 16; |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1310 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 1311 | for ( i = 0; i < lines ; i ++ ) { |
| 1312 | int cur; |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1313 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 1314 | for ( cur = 0; cur < 8; cur ++ ) { |
| 1315 | byte a, b; |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1316 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 1317 | a = *(buf ++ ); |
| 1318 | b = *(buf ++ ); |
| 1319 | printf("%02x%02x ", a, b ); |
| 1320 | } |
| 1321 | printf("\n"); |
| 1322 | } |
| 1323 | for ( i = 0; i < remainder/2 ; i++ ) { |
| 1324 | byte a, b; |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1325 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 1326 | a = *(buf ++ ); |
| 1327 | b = *(buf ++ ); |
| 1328 | printf("%02x%02x ", a, b ); |
| 1329 | } |
| 1330 | printf("\n"); |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1331 | #endif |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1332 | } |
| 1333 | #endif |
| 1334 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1335 | int smc91111_initialize(u8 dev_num, int base_addr) |
wdenk | 0b97ab1 | 2003-06-19 23:58:30 +0000 | [diff] [blame] | 1336 | { |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1337 | struct smc91111_priv *priv; |
| 1338 | struct eth_device *dev; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 1339 | int i; |
wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 1340 | |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1341 | priv = malloc(sizeof(*priv)); |
| 1342 | if (!priv) |
| 1343 | return 0; |
| 1344 | dev = malloc(sizeof(*dev)); |
| 1345 | if (!dev) { |
| 1346 | free(priv); |
| 1347 | return 0; |
wdenk | b56ddc6 | 2003-09-15 21:14:37 +0000 | [diff] [blame] | 1348 | } |
wdenk | f39748a | 2004-06-09 13:37:52 +0000 | [diff] [blame] | 1349 | |
Thomas Chou | 1ca6d0d | 2010-10-06 09:16:10 +0800 | [diff] [blame] | 1350 | memset(dev, 0, sizeof(*dev)); |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1351 | priv->dev_num = dev_num; |
| 1352 | dev->priv = priv; |
| 1353 | dev->iobase = base_addr; |
| 1354 | |
| 1355 | swap_to(ETHERNET); |
| 1356 | SMC_SELECT_BANK(dev, 1); |
| 1357 | for (i = 0; i < 6; ++i) |
| 1358 | dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i)); |
| 1359 | swap_to(FLASH); |
| 1360 | |
| 1361 | dev->init = smc_init; |
| 1362 | dev->halt = smc_halt; |
| 1363 | dev->send = smc_send; |
| 1364 | dev->recv = smc_rcv; |
Thomas Chou | 1ca6d0d | 2010-10-06 09:16:10 +0800 | [diff] [blame] | 1365 | dev->write_hwaddr = smc_write_hwaddr; |
Ben Warren | 7194ab8 | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 1366 | sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num); |
| 1367 | |
| 1368 | eth_register(dev); |
| 1369 | return 0; |
wdenk | 0b97ab1 | 2003-06-19 23:58:30 +0000 | [diff] [blame] | 1370 | } |