| Jagan Teki | 2a8481e | 2023-01-30 20:27:46 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. |
| 4 | */ |
| 5 | |
| 6 | #include "rockchip-u-boot.dtsi" |
| 7 | #include "rk3588s-u-boot.dtsi" |
| Joseph Chen | b8bae82 | 2023-05-29 13:01:34 +0300 | [diff] [blame] | 8 | |
| 9 | / { |
| 10 | usbdrd3_1: usbdrd3_1 { |
| 11 | compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; |
| 12 | clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, |
| 13 | <&cru ACLK_USB3OTG1>; |
| 14 | clock-names = "ref", "suspend", "bus"; |
| 15 | #address-cells = <2>; |
| 16 | #size-cells = <2>; |
| 17 | ranges; |
| 18 | status = "disabled"; |
| 19 | |
| 20 | usbdrd_dwc3_1: usb@fc400000 { |
| 21 | compatible = "snps,dwc3"; |
| 22 | reg = <0x0 0xfc400000 0x0 0x400000>; |
| 23 | interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; |
| 24 | power-domains = <&power RK3588_PD_USB>; |
| 25 | resets = <&cru SRST_A_USB3OTG1>; |
| 26 | reset-names = "usb3-otg"; |
| 27 | dr_mode = "host"; |
| 28 | phys = <&u2phy1_otg>, <&usbdp_phy1_u3>; |
| 29 | phy-names = "usb2-phy", "usb3-phy"; |
| 30 | phy_type = "utmi_wide"; |
| 31 | snps,dis_enblslpm_quirk; |
| 32 | snps,dis-u2-freeclk-exists-quirk; |
| 33 | snps,dis-del-phy-power-chg-quirk; |
| 34 | snps,dis-tx-ipgap-linecheck-quirk; |
| 35 | }; |
| 36 | }; |
| 37 | |
| 38 | usbdpphy1_grf: syscon@fd5cc000 { |
| 39 | compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; |
| 40 | reg = <0x0 0xfd5cc000 0x0 0x4000>; |
| 41 | }; |
| 42 | |
| 43 | usb2phy1_grf: syscon@fd5d4000 { |
| 44 | compatible = "rockchip,rk3588-usb2phy-grf", "syscon", |
| 45 | "simple-mfd"; |
| 46 | reg = <0x0 0xfd5d4000 0x0 0x4000>; |
| 47 | #address-cells = <1>; |
| 48 | #size-cells = <1>; |
| 49 | |
| 50 | u2phy1: usb2-phy@4000 { |
| 51 | compatible = "rockchip,rk3588-usb2phy"; |
| 52 | reg = <0x4000 0x10>; |
| 53 | interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>; |
| 54 | resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; |
| 55 | reset-names = "phy", "apb"; |
| 56 | clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; |
| 57 | clock-names = "phyclk"; |
| 58 | clock-output-names = "usb480m_phy1"; |
| 59 | #clock-cells = <0>; |
| 60 | rockchip,usbctrl-grf = <&usb_grf>; |
| 61 | status = "disabled"; |
| 62 | |
| 63 | u2phy1_otg: otg-port { |
| 64 | #phy-cells = <0>; |
| 65 | status = "disabled"; |
| 66 | }; |
| 67 | }; |
| 68 | }; |
| 69 | |
| 70 | usbdp_phy1: phy@fed90000 { |
| 71 | compatible = "rockchip,rk3588-usbdp-phy"; |
| 72 | reg = <0x0 0xfed90000 0x0 0x10000>; |
| 73 | rockchip,u2phy-grf = <&usb2phy1_grf>; |
| 74 | rockchip,usb-grf = <&usb_grf>; |
| 75 | rockchip,usbdpphy-grf = <&usbdpphy1_grf>; |
| 76 | rockchip,vo-grf = <&vo0_grf>; |
| 77 | clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, |
| 78 | <&cru CLK_USBDP_PHY1_IMMORTAL>, |
| 79 | <&cru PCLK_USBDPPHY1>, |
| 80 | <&u2phy1>; |
| 81 | clock-names = "refclk", "immortal", "pclk", "utmi"; |
| 82 | resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, |
| 83 | <&cru SRST_USBDP_COMBO_PHY1_CMN>, |
| 84 | <&cru SRST_USBDP_COMBO_PHY1_LANE>, |
| 85 | <&cru SRST_USBDP_COMBO_PHY1_PCS>, |
| 86 | <&cru SRST_P_USBDPPHY1>; |
| 87 | reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; |
| 88 | status = "disabled"; |
| 89 | |
| 90 | usbdp_phy1_dp: dp-port { |
| 91 | #phy-cells = <0>; |
| 92 | status = "disabled"; |
| 93 | }; |
| 94 | |
| 95 | usbdp_phy1_u3: usb3-port { |
| 96 | #phy-cells = <0>; |
| 97 | status = "disabled"; |
| 98 | }; |
| 99 | }; |
| 100 | }; |