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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Jon Loeliger7237c032006-10-19 11:02:16 -05002/*
Timur Tabi92477a62009-09-04 16:28:35 -05003 * Copyright 2006,2009 Freescale Semiconductor, Inc.
Jon Loeliger7237c032006-10-19 11:02:16 -05004 *
Heiko Schocher00f792e2012-10-24 13:48:22 +02005 * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 * Changes for multibus/multiadapter I2C support.
Jon Loeliger7237c032006-10-19 11:02:16 -05007 */
8
Jon Loeliger7237c032006-10-19 11:02:16 -05009#include <common.h>
Jon Loeliger4d45f692006-10-19 12:02:24 -050010#include <command.h>
Jon Loeliger20476722006-10-20 15:50:15 -050011#include <i2c.h> /* Functional interface */
Simon Glass6887c5b2019-11-14 12:57:26 -070012#include <time.h>
Jon Loeliger7237c032006-10-19 11:02:16 -050013#include <asm/io.h>
Jon Loeliger20476722006-10-20 15:50:15 -050014#include <asm/fsl_i2c.h> /* HW definitions */
Mario Sixe5c762f2018-03-28 14:37:44 +020015#include <clk.h>
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +020016#include <dm.h>
17#include <mapmem.h>
Jon Loeliger7237c032006-10-19 11:02:16 -050018
Timur Tabi92477a62009-09-04 16:28:35 -050019/* The maximum number of microseconds we will wait until another master has
20 * released the bus. If not defined in the board header file, then use a
21 * generic value.
22 */
23#ifndef CONFIG_I2C_MBB_TIMEOUT
24#define CONFIG_I2C_MBB_TIMEOUT 100000
25#endif
26
27/* The maximum number of microseconds we will wait for a read or write
28 * operation to complete. If not defined in the board header file, then use a
29 * generic value.
30 */
31#ifndef CONFIG_I2C_TIMEOUT
Shaveta Leekha6dd38cc2014-11-03 10:43:14 +053032#define CONFIG_I2C_TIMEOUT 100000
Timur Tabi92477a62009-09-04 16:28:35 -050033#endif
Jon Loeliger7237c032006-10-19 11:02:16 -050034
Joakim Tjernlund1939d962006-11-28 16:17:27 -060035#define I2C_READ_BIT 1
36#define I2C_WRITE_BIT 0
37
Timur Tabid8c82db2008-03-14 17:45:29 -050038DECLARE_GLOBAL_DATA_PTR;
39
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +020040#ifndef CONFIG_DM_I2C
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +020041static const struct fsl_i2c_base *i2c_base[4] = {
42 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
Heiko Schocher00f792e2012-10-24 13:48:22 +020043#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +020044 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
Shengzhou Liua17fd102014-07-07 12:17:48 +080045#endif
46#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +020047 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
Shengzhou Liua17fd102014-07-07 12:17:48 +080048#endif
49#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +020050 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
Timur Tabibe5e6182006-11-03 19:15:00 -060051#endif
52};
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +020053#endif
Jon Loeliger7237c032006-10-19 11:02:16 -050054
Timur Tabid8c82db2008-03-14 17:45:29 -050055/* I2C speed map for a DFSR value of 1 */
56
Tom Rini645cb462017-02-09 15:40:16 -050057#ifdef __M68K__
Timur Tabid8c82db2008-03-14 17:45:29 -050058/*
59 * Map I2C frequency dividers to FDR and DFSR values
60 *
61 * This structure is used to define the elements of a table that maps I2C
62 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
63 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
64 * Sampling Rate (DFSR) registers.
65 *
66 * The actual table should be defined in the board file, and it must be called
67 * fsl_i2c_speed_map[].
68 *
69 * The last entry of the table must have a value of {-1, X}, where X is same
70 * FDR/DFSR values as the second-to-last entry. This guarantees that any
71 * search through the array will always find a match.
72 *
73 * The values of the divider must be in increasing numerical order, i.e.
74 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
75 *
76 * For this table, the values are based on a value of 1 for the DFSR
77 * register. See the application note AN2919 "Determining the I2C Frequency
78 * Divider Ratio for SCL"
TsiChung Liew5d9a5ef2008-08-19 00:56:46 +060079 *
80 * ColdFire I2C frequency dividers for FDR values are different from
81 * PowerPC. The protocol to use the I2C module is still the same.
82 * A different table is defined and are based on MCF5xxx user manual.
83 *
Timur Tabid8c82db2008-03-14 17:45:29 -050084 */
85static const struct {
86 unsigned short divider;
Timur Tabid8c82db2008-03-14 17:45:29 -050087 u8 fdr;
88} fsl_i2c_speed_map[] = {
TsiChung Liew5d9a5ef2008-08-19 00:56:46 +060089 {20, 32}, {22, 33}, {24, 34}, {26, 35},
90 {28, 0}, {28, 36}, {30, 1}, {32, 37},
91 {34, 2}, {36, 38}, {40, 3}, {40, 39},
92 {44, 4}, {48, 5}, {48, 40}, {56, 6},
93 {56, 41}, {64, 42}, {68, 7}, {72, 43},
94 {80, 8}, {80, 44}, {88, 9}, {96, 41},
95 {104, 10}, {112, 42}, {128, 11}, {128, 43},
96 {144, 12}, {160, 13}, {160, 48}, {192, 14},
97 {192, 49}, {224, 50}, {240, 15}, {256, 51},
98 {288, 16}, {320, 17}, {320, 52}, {384, 18},
99 {384, 53}, {448, 54}, {480, 19}, {512, 55},
100 {576, 20}, {640, 21}, {640, 56}, {768, 22},
101 {768, 57}, {960, 23}, {896, 58}, {1024, 59},
102 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
103 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
104 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
105 {-1, 31}
Timur Tabid8c82db2008-03-14 17:45:29 -0500106};
Tom Rini645cb462017-02-09 15:40:16 -0500107#endif
Timur Tabid8c82db2008-03-14 17:45:29 -0500108
109/**
110 * Set the I2C bus speed for a given I2C device
111 *
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200112 * @param base: the I2C device registers
Timur Tabid8c82db2008-03-14 17:45:29 -0500113 * @i2c_clk: I2C bus clock frequency
114 * @speed: the desired speed of the bus
115 *
116 * The I2C device must be stopped before calling this function.
117 *
118 * The return value is the actual bus speed that is set.
119 */
Mario Sixa059de12018-01-15 11:08:07 +0100120static uint set_i2c_bus_speed(const struct fsl_i2c_base *base,
121 uint i2c_clk, uint speed)
Timur Tabid8c82db2008-03-14 17:45:29 -0500122{
Mario Sixa059de12018-01-15 11:08:07 +0100123 ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX);
Timur Tabid8c82db2008-03-14 17:45:29 -0500124
125 /*
126 * We want to choose an FDR/DFSR that generates an I2C bus speed that
127 * is equal to or lower than the requested speed. That means that we
128 * want the first divider that is equal to or greater than the
129 * calculated divider.
130 */
Joakim Tjernlund99404202009-09-17 11:07:17 +0200131#ifdef __PPC__
132 u8 dfsr, fdr = 0x31; /* Default if no FDR found */
133 /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
Mario Sixa059de12018-01-15 11:08:07 +0100134 ushort a, b, ga, gb;
135 ulong c_div, est_div;
Joakim Tjernlund99404202009-09-17 11:07:17 +0200136
137#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
138 dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
139#else
140 /* Condition 1: dfsr <= 50/T */
141 dfsr = (5 * (i2c_clk / 1000)) / 100000;
142#endif
143#ifdef CONFIG_FSL_I2C_CUSTOM_FDR
144 fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
145 speed = i2c_clk / divider; /* Fake something */
146#else
147 debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
148 if (!dfsr)
149 dfsr = 1;
150
151 est_div = ~0;
152 for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
153 for (gb = 0; gb < 8; gb++) {
154 b = 16 << gb;
Mario Sixa059de12018-01-15 11:08:07 +0100155 c_div = b * (a + ((3 * dfsr) / b) * 2);
156 if (c_div > divider && c_div < est_div) {
157 ushort bin_gb, bin_ga;
Joakim Tjernlund99404202009-09-17 11:07:17 +0200158
159 est_div = c_div;
160 bin_gb = gb << 2;
161 bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
162 fdr = bin_gb | bin_ga;
163 speed = i2c_clk / est_div;
Mario Sixa059de12018-01-15 11:08:07 +0100164
165 debug("FDR: 0x%.2x, ", fdr);
166 debug("div: %ld, ", est_div);
167 debug("ga: 0x%x, gb: 0x%x, ", ga, gb);
168 debug("a: %d, b: %d, speed: %d\n", a, b, speed);
169
Joakim Tjernlund99404202009-09-17 11:07:17 +0200170 /* Condition 2 not accounted for */
171 debug("Tr <= %d ns\n",
172 (b - 3 * dfsr) * 1000000 /
173 (i2c_clk / 1000));
174 }
175 }
176 if (a == 20)
177 a += 2;
178 if (a == 24)
179 a += 4;
180 }
Mario Sixa059de12018-01-15 11:08:07 +0100181 debug("divider: %d, est_div: %ld, DFSR: %d\n", divider, est_div, dfsr);
182 debug("FDR: 0x%.2x, speed: %d\n", fdr, speed);
Joakim Tjernlund99404202009-09-17 11:07:17 +0200183#endif
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200184 writeb(dfsr, &base->dfsrr); /* set default filter */
185 writeb(fdr, &base->fdr); /* set bus speed */
Joakim Tjernlund99404202009-09-17 11:07:17 +0200186#else
Mario Sixa059de12018-01-15 11:08:07 +0100187 uint i;
Timur Tabid8c82db2008-03-14 17:45:29 -0500188
189 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
190 if (fsl_i2c_speed_map[i].divider >= divider) {
TsiChung Liew5d9a5ef2008-08-19 00:56:46 +0600191 u8 fdr;
Joakim Tjernlund99404202009-09-17 11:07:17 +0200192
Joakim Tjernlundd01ee4d2009-09-17 11:07:16 +0200193 fdr = fsl_i2c_speed_map[i].fdr;
194 speed = i2c_clk / fsl_i2c_speed_map[i].divider;
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200195 writeb(fdr, &base->fdr); /* set bus speed */
Joakim Tjernlundd01ee4d2009-09-17 11:07:16 +0200196
Timur Tabid8c82db2008-03-14 17:45:29 -0500197 break;
198 }
Joakim Tjernlund99404202009-09-17 11:07:17 +0200199#endif
Timur Tabid8c82db2008-03-14 17:45:29 -0500200 return speed;
201}
202
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +0200203#ifndef CONFIG_DM_I2C
Mario Sixa059de12018-01-15 11:08:07 +0100204static uint get_i2c_clock(int bus)
Jerry Huangc9a8b252011-10-26 15:29:38 +0000205{
206 if (bus)
Simon Glass609e6ec2012-12-13 20:48:49 +0000207 return gd->arch.i2c2_clk; /* I2C2 clock */
Jerry Huangc9a8b252011-10-26 15:29:38 +0000208 else
Simon Glass609e6ec2012-12-13 20:48:49 +0000209 return gd->arch.i2c1_clk; /* I2C1 clock */
Jerry Huangc9a8b252011-10-26 15:29:38 +0000210}
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +0200211#endif
Jerry Huangc9a8b252011-10-26 15:29:38 +0000212
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200213static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800214{
215 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
216 unsigned long long timeval = 0;
217 int ret = -1;
Mario Sixa059de12018-01-15 11:08:07 +0100218 uint flags = 0;
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800219
220#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Mario Sixa059de12018-01-15 11:08:07 +0100221 uint svr = get_svr();
222
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800223 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
224 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
225 flags = I2C_CR_BIT6;
226#endif
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800227
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200228 writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr);
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800229
230 timeval = get_ticks();
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200231 while (!(readb(&base->sr) & I2C_SR_MBB)) {
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800232 if ((get_ticks() - timeval) > timeout)
233 goto err;
234 }
235
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200236 if (readb(&base->sr) & I2C_SR_MAL) {
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800237 /* SDA is stuck low */
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200238 writeb(0, &base->cr);
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800239 udelay(100);
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200240 writeb(I2C_CR_MSTA | flags, &base->cr);
241 writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr);
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800242 }
243
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200244 readb(&base->dr);
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800245
246 timeval = get_ticks();
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200247 while (!(readb(&base->sr) & I2C_SR_MIF)) {
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800248 if ((get_ticks() - timeval) > timeout)
249 goto err;
250 }
251 ret = 0;
252
253err:
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200254 writeb(I2C_CR_MEN | flags, &base->cr);
255 writeb(0, &base->sr);
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800256 udelay(100);
257
258 return ret;
259}
260
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200261static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
262 slaveadd, int i2c_clk, int busnum)
Jon Loeliger7237c032006-10-19 11:02:16 -0500263{
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800264 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
265 unsigned long long timeval;
Jon Loeliger7237c032006-10-19 11:02:16 -0500266
Heiko Schocher39df00d2009-07-09 12:04:26 +0200267#ifdef CONFIG_SYS_I2C_INIT_BOARD
Richard Retanubun26a33502010-04-12 15:08:17 -0400268 /* Call board specific i2c bus reset routine before accessing the
269 * environment, which might be in a chip on that bus. For details
270 * about this problem see doc/I2C_Edge_Conditions.
Mario Sixa059de12018-01-15 11:08:07 +0100271 */
Heiko Schocher39df00d2009-07-09 12:04:26 +0200272 i2c_init_board();
273#endif
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200274 writeb(0, &base->cr); /* stop I2C controller */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200275 udelay(5); /* let it shutdown in peace */
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200276 set_i2c_bus_speed(base, i2c_clk, speed);
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200277 writeb(slaveadd << 1, &base->adr);/* write slave address */
278 writeb(0x0, &base->sr); /* clear status register */
279 writeb(I2C_CR_MEN, &base->cr); /* start I2C controller */
Richard Retanubun26a33502010-04-12 15:08:17 -0400280
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800281 timeval = get_ticks();
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200282 while (readb(&base->sr) & I2C_SR_MBB) {
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800283 if ((get_ticks() - timeval) < timeout)
284 continue;
285
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200286 if (fsl_i2c_fixup(base))
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800287 debug("i2c_init: BUS#%d failed to init\n",
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200288 busnum);
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800289
290 break;
291 }
Jon Loeliger7237c032006-10-19 11:02:16 -0500292}
293
Mario Sixa059de12018-01-15 11:08:07 +0100294static int i2c_wait4bus(const struct fsl_i2c_base *base)
Jon Loeliger7237c032006-10-19 11:02:16 -0500295{
Stefan Roesef2302d42008-08-06 14:05:38 +0200296 unsigned long long timeval = get_ticks();
Timur Tabi92477a62009-09-04 16:28:35 -0500297 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
Jon Loeliger7237c032006-10-19 11:02:16 -0500298
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200299 while (readb(&base->sr) & I2C_SR_MBB) {
Timur Tabi92477a62009-09-04 16:28:35 -0500300 if ((get_ticks() - timeval) > timeout)
Jon Loeliger7237c032006-10-19 11:02:16 -0500301 return -1;
Jon Loeliger7237c032006-10-19 11:02:16 -0500302 }
303
304 return 0;
305}
306
Mario Sixd4f422f2018-01-15 11:08:08 +0100307static int i2c_wait(const struct fsl_i2c_base *base, int write)
Jon Loeliger7237c032006-10-19 11:02:16 -0500308{
309 u32 csr;
Stefan Roesef2302d42008-08-06 14:05:38 +0200310 unsigned long long timeval = get_ticks();
Timur Tabi92477a62009-09-04 16:28:35 -0500311 const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
Jon Loeliger7237c032006-10-19 11:02:16 -0500312
313 do {
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200314 csr = readb(&base->sr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500315 if (!(csr & I2C_SR_MIF))
316 continue;
Joakim Tjernlund21f4cbb2009-09-17 11:07:15 +0200317 /* Read again to allow register to stabilise */
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200318 csr = readb(&base->sr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500319
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200320 writeb(0x0, &base->sr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500321
322 if (csr & I2C_SR_MAL) {
Mario Sixa059de12018-01-15 11:08:07 +0100323 debug("%s: MAL\n", __func__);
Jon Loeliger7237c032006-10-19 11:02:16 -0500324 return -1;
325 }
326
327 if (!(csr & I2C_SR_MCF)) {
Mario Sixa059de12018-01-15 11:08:07 +0100328 debug("%s: unfinished\n", __func__);
Jon Loeliger7237c032006-10-19 11:02:16 -0500329 return -1;
330 }
331
Joakim Tjernlund1939d962006-11-28 16:17:27 -0600332 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
Mario Sixa059de12018-01-15 11:08:07 +0100333 debug("%s: No RXACK\n", __func__);
Jon Loeliger7237c032006-10-19 11:02:16 -0500334 return -1;
335 }
336
337 return 0;
Timur Tabi92477a62009-09-04 16:28:35 -0500338 } while ((get_ticks() - timeval) < timeout);
Jon Loeliger7237c032006-10-19 11:02:16 -0500339
Mario Sixa059de12018-01-15 11:08:07 +0100340 debug("%s: timed out\n", __func__);
Jon Loeliger7237c032006-10-19 11:02:16 -0500341 return -1;
342}
343
Mario Sixd4f422f2018-01-15 11:08:08 +0100344static int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev,
345 u8 dir, int rsta)
Jon Loeliger7237c032006-10-19 11:02:16 -0500346{
347 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
348 | (rsta ? I2C_CR_RSTA : 0),
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200349 &base->cr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500350
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200351 writeb((dev << 1) | dir, &base->dr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500352
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200353 if (i2c_wait(base, I2C_WRITE_BIT) < 0)
Jon Loeliger7237c032006-10-19 11:02:16 -0500354 return 0;
355
356 return 1;
357}
358
Mario Sixd4f422f2018-01-15 11:08:08 +0100359static int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data,
360 int length)
Jon Loeliger7237c032006-10-19 11:02:16 -0500361{
362 int i;
363
Jon Loeliger7237c032006-10-19 11:02:16 -0500364 for (i = 0; i < length; i++) {
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200365 writeb(data[i], &base->dr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500366
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200367 if (i2c_wait(base, I2C_WRITE_BIT) < 0)
Jon Loeliger7237c032006-10-19 11:02:16 -0500368 break;
369 }
370
371 return i;
372}
373
Mario Sixd4f422f2018-01-15 11:08:08 +0100374static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data,
375 int length)
Jon Loeliger7237c032006-10-19 11:02:16 -0500376{
377 int i;
378
379 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200380 &base->cr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500381
382 /* dummy read */
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200383 readb(&base->dr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500384
385 for (i = 0; i < length; i++) {
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200386 if (i2c_wait(base, I2C_READ_BIT) < 0)
Jon Loeliger7237c032006-10-19 11:02:16 -0500387 break;
388
389 /* Generate ack on last next to last byte */
390 if (i == length - 2)
391 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200392 &base->cr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500393
Joakim Tjernlundd1c9e5b2009-09-22 13:40:44 +0200394 /* Do not generate stop on last byte */
Jon Loeliger7237c032006-10-19 11:02:16 -0500395 if (i == length - 1)
Joakim Tjernlundd1c9e5b2009-09-22 13:40:44 +0200396 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200397 &base->cr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500398
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200399 data[i] = readb(&base->dr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500400 }
401
402 return i;
403}
404
Mario Sixa059de12018-01-15 11:08:07 +0100405static int __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset,
406 int olen, u8 *data, int dlen)
Jon Loeliger7237c032006-10-19 11:02:16 -0500407{
mario.six@gdsys.cc2b21e962016-04-25 08:31:02 +0200408 int ret = -1; /* signal error */
Jon Loeliger7237c032006-10-19 11:02:16 -0500409
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200410 if (i2c_wait4bus(base) < 0)
Reinhard Pfaub778c1b2013-06-26 15:55:14 +0200411 return -1;
412
mario.six@gdsys.cc386b2762016-04-25 08:31:03 +0200413 /* Some drivers use offset lengths in excess of 4 bytes. These drivers
414 * adhere to the following convention:
415 * - the offset length is passed as negative (that is, the absolute
416 * value of olen is the actual offset length)
417 * - the offset itself is passed in data, which is overwritten by the
418 * subsequent read operation
Shaveta Leekhaa4057642014-04-24 14:51:23 +0530419 */
mario.six@gdsys.cc2b21e962016-04-25 08:31:02 +0200420 if (olen < 0) {
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200421 if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0)
422 ret = __i2c_write_data(base, data, -olen);
Joakim Tjernlundf6f5f702007-01-31 11:04:19 +0100423
mario.six@gdsys.cc03a112a2016-04-25 08:31:04 +0200424 if (ret != -olen)
Shaveta Leekhaa4057642014-04-24 14:51:23 +0530425 return -1;
426
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200427 if (dlen && i2c_write_addr(base, chip_addr,
mario.six@gdsys.cc2b21e962016-04-25 08:31:02 +0200428 I2C_READ_BIT, 1) != 0)
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200429 ret = __i2c_read_data(base, data, dlen);
Shaveta Leekhaa4057642014-04-24 14:51:23 +0530430 } else {
mario.six@gdsys.cc2b21e962016-04-25 08:31:02 +0200431 if ((!dlen || olen > 0) &&
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200432 i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
433 __i2c_write_data(base, offset, olen) == olen)
mario.six@gdsys.cc2b21e962016-04-25 08:31:02 +0200434 ret = 0; /* No error so far */
Shaveta Leekhaa4057642014-04-24 14:51:23 +0530435
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200436 if (dlen && i2c_write_addr(base, chip_addr, I2C_READ_BIT,
mario.six@gdsys.cc2b21e962016-04-25 08:31:02 +0200437 olen ? 1 : 0) != 0)
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200438 ret = __i2c_read_data(base, data, dlen);
Shaveta Leekhaa4057642014-04-24 14:51:23 +0530439 }
Jon Loeliger7237c032006-10-19 11:02:16 -0500440
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200441 writeb(I2C_CR_MEN, &base->cr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500442
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200443 if (i2c_wait4bus(base)) /* Wait until STOP */
Joakim Tjernlundd1c9e5b2009-09-22 13:40:44 +0200444 debug("i2c_read: wait4bus timed out\n");
445
mario.six@gdsys.cc2b21e962016-04-25 08:31:02 +0200446 if (ret == dlen)
447 return 0;
Jon Loeliger4d45f692006-10-19 12:02:24 -0500448
449 return -1;
Jon Loeliger7237c032006-10-19 11:02:16 -0500450}
451
Mario Sixa059de12018-01-15 11:08:07 +0100452static int __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr,
453 u8 *offset, int olen, u8 *data, int dlen)
Jon Loeliger7237c032006-10-19 11:02:16 -0500454{
mario.six@gdsys.cc2b21e962016-04-25 08:31:02 +0200455 int ret = -1; /* signal error */
Jon Loeliger7237c032006-10-19 11:02:16 -0500456
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200457 if (i2c_wait4bus(base) < 0)
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800458 return -1;
459
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200460 if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
461 __i2c_write_data(base, offset, olen) == olen) {
462 ret = __i2c_write_data(base, data, dlen);
Jon Loeliger4d45f692006-10-19 12:02:24 -0500463 }
Jon Loeliger7237c032006-10-19 11:02:16 -0500464
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200465 writeb(I2C_CR_MEN, &base->cr);
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200466 if (i2c_wait4bus(base)) /* Wait until STOP */
Joakim Tjernlund21f4cbb2009-09-17 11:07:15 +0200467 debug("i2c_write: wait4bus timed out\n");
Jon Loeliger7237c032006-10-19 11:02:16 -0500468
mario.six@gdsys.cc2b21e962016-04-25 08:31:02 +0200469 if (ret == dlen)
470 return 0;
Jon Loeliger4d45f692006-10-19 12:02:24 -0500471
472 return -1;
Jon Loeliger7237c032006-10-19 11:02:16 -0500473}
474
Mario Sixa059de12018-01-15 11:08:07 +0100475static int __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip)
Jon Loeliger7237c032006-10-19 11:02:16 -0500476{
Mario Sixa059de12018-01-15 11:08:07 +0100477 /* For unknown reason the controller will ACK when
Joakim Tjernlundf6f5f702007-01-31 11:04:19 +0100478 * probing for a slave with the same address, so skip
479 * it.
Jon Loeliger7237c032006-10-19 11:02:16 -0500480 */
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200481 if (chip == (readb(&base->adr) >> 1))
Joakim Tjernlundf6f5f702007-01-31 11:04:19 +0100482 return -1;
Jon Loeliger7237c032006-10-19 11:02:16 -0500483
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200484 return __i2c_read(base, chip, 0, 0, NULL, 0);
Jon Loeliger7237c032006-10-19 11:02:16 -0500485}
486
Mario Sixa059de12018-01-15 11:08:07 +0100487static uint __i2c_set_bus_speed(const struct fsl_i2c_base *base,
488 uint speed, int i2c_clk)
Timur Tabibe5e6182006-11-03 19:15:00 -0600489{
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200490 writeb(0, &base->cr); /* stop controller */
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200491 set_i2c_bus_speed(base, i2c_clk, speed);
mario.six@gdsys.ccec2c81c2016-04-25 08:31:01 +0200492 writeb(I2C_CR_MEN, &base->cr); /* start controller */
Timur Tabid8c82db2008-03-14 17:45:29 -0500493
494 return 0;
Timur Tabibe5e6182006-11-03 19:15:00 -0600495}
496
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +0200497#ifndef CONFIG_DM_I2C
mario.six@gdsys.ccad7e6572016-04-25 08:31:07 +0200498static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
499{
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200500 __i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd,
501 get_i2c_clock(adap->hwadapnr), adap->hwadapnr);
mario.six@gdsys.ccad7e6572016-04-25 08:31:07 +0200502}
503
Mario Sixa059de12018-01-15 11:08:07 +0100504static int fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
mario.six@gdsys.ccad7e6572016-04-25 08:31:07 +0200505{
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200506 return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip);
mario.six@gdsys.ccad7e6572016-04-25 08:31:07 +0200507}
508
Mario Sixa059de12018-01-15 11:08:07 +0100509static int fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset,
510 int olen, u8 *data, int dlen)
mario.six@gdsys.ccad7e6572016-04-25 08:31:07 +0200511{
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200512 u8 *o = (u8 *)&offset;
Mario Sixa059de12018-01-15 11:08:07 +0100513
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200514 return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
515 olen, data, dlen);
mario.six@gdsys.ccad7e6572016-04-25 08:31:07 +0200516}
517
Mario Sixa059de12018-01-15 11:08:07 +0100518static int fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset,
519 int olen, u8 *data, int dlen)
mario.six@gdsys.ccad7e6572016-04-25 08:31:07 +0200520{
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200521 u8 *o = (u8 *)&offset;
Mario Sixa059de12018-01-15 11:08:07 +0100522
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200523 return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
524 olen, data, dlen);
mario.six@gdsys.ccad7e6572016-04-25 08:31:07 +0200525}
526
Mario Sixa059de12018-01-15 11:08:07 +0100527static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
mario.six@gdsys.ccad7e6572016-04-25 08:31:07 +0200528{
mario.six@gdsys.ccecf591e2016-04-25 08:31:08 +0200529 return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed,
530 get_i2c_clock(adap->hwadapnr));
mario.six@gdsys.ccad7e6572016-04-25 08:31:07 +0200531}
532
Heiko Schocher00f792e2012-10-24 13:48:22 +0200533/*
534 * Register fsl i2c adapters
535 */
mario.six@gdsys.cc16579ec2016-04-25 08:31:05 +0200536U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
Heiko Schocher00f792e2012-10-24 13:48:22 +0200537 fsl_i2c_write, fsl_i2c_set_bus_speed,
538 CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
539 0)
540#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
mario.six@gdsys.cc16579ec2016-04-25 08:31:05 +0200541U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
Heiko Schocher00f792e2012-10-24 13:48:22 +0200542 fsl_i2c_write, fsl_i2c_set_bus_speed,
543 CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
544 1)
Heiko Schocherc1bce4f2009-02-24 11:30:37 +0100545#endif
Shengzhou Liua17fd102014-07-07 12:17:48 +0800546#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
mario.six@gdsys.cc16579ec2016-04-25 08:31:05 +0200547U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
Shengzhou Liua17fd102014-07-07 12:17:48 +0800548 fsl_i2c_write, fsl_i2c_set_bus_speed,
549 CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
550 2)
551#endif
552#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
mario.six@gdsys.cc16579ec2016-04-25 08:31:05 +0200553U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
Shengzhou Liua17fd102014-07-07 12:17:48 +0800554 fsl_i2c_write, fsl_i2c_set_bus_speed,
555 CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
556 3)
557#endif
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +0200558#else /* CONFIG_DM_I2C */
559static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
560 u32 chip_flags)
561{
562 struct fsl_i2c_dev *dev = dev_get_priv(bus);
Mario Sixa059de12018-01-15 11:08:07 +0100563
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +0200564 return __i2c_probe_chip(dev->base, chip_addr);
565}
566
Mario Sixa059de12018-01-15 11:08:07 +0100567static int fsl_i2c_set_bus_speed(struct udevice *bus, uint speed)
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +0200568{
569 struct fsl_i2c_dev *dev = dev_get_priv(bus);
Mario Sixa059de12018-01-15 11:08:07 +0100570
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +0200571 return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk);
572}
573
574static int fsl_i2c_ofdata_to_platdata(struct udevice *bus)
575{
576 struct fsl_i2c_dev *dev = dev_get_priv(bus);
Mario Sixe5c762f2018-03-28 14:37:44 +0200577 struct clk clock;
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +0200578
Mario Sixd9348322018-03-28 14:37:43 +0200579 dev->base = map_sysmem(dev_read_addr(bus), sizeof(struct fsl_i2c_base));
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +0200580
581 if (!dev->base)
582 return -ENOMEM;
583
Mario Six84a4d342018-01-15 11:08:09 +0100584 dev->index = dev_read_u32_default(bus, "cell-index", -1);
585 dev->slaveadd = dev_read_u32_default(bus, "u-boot,i2c-slave-addr",
586 0x7f);
587 dev->speed = dev_read_u32_default(bus, "clock-frequency", 400000);
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +0200588
Mario Sixe5c762f2018-03-28 14:37:44 +0200589 if (!clk_get_by_index(bus, 0, &clock))
590 dev->i2c_clk = clk_get_rate(&clock);
591 else
592 dev->i2c_clk = dev->index ? gd->arch.i2c2_clk :
593 gd->arch.i2c1_clk;
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +0200594
595 return 0;
596}
597
598static int fsl_i2c_probe(struct udevice *bus)
599{
600 struct fsl_i2c_dev *dev = dev_get_priv(bus);
Mario Sixa059de12018-01-15 11:08:07 +0100601
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +0200602 __i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk,
603 dev->index);
604 return 0;
605}
606
607static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
608{
609 struct fsl_i2c_dev *dev = dev_get_priv(bus);
610 struct i2c_msg *dmsg, *omsg, dummy;
611
612 memset(&dummy, 0, sizeof(struct i2c_msg));
613
614 /* We expect either two messages (one with an offset and one with the
Mario Sixa059de12018-01-15 11:08:07 +0100615 * actual data) or one message (just data)
616 */
mario.six@gdsys.ccdbc82ce2016-04-25 08:31:09 +0200617 if (nmsgs > 2 || nmsgs == 0) {
618 debug("%s: Only one or two messages are supported.", __func__);
619 return -1;
620 }
621
622 omsg = nmsgs == 1 ? &dummy : msg;
623 dmsg = nmsgs == 1 ? msg : msg + 1;
624
625 if (dmsg->flags & I2C_M_RD)
626 return __i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len,
627 dmsg->buf, dmsg->len);
628 else
629 return __i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len,
630 dmsg->buf, dmsg->len);
631}
632
633static const struct dm_i2c_ops fsl_i2c_ops = {
634 .xfer = fsl_i2c_xfer,
635 .probe_chip = fsl_i2c_probe_chip,
636 .set_bus_speed = fsl_i2c_set_bus_speed,
637};
638
639static const struct udevice_id fsl_i2c_ids[] = {
640 { .compatible = "fsl-i2c", },
641 { /* sentinel */ }
642};
643
644U_BOOT_DRIVER(i2c_fsl) = {
645 .name = "i2c_fsl",
646 .id = UCLASS_I2C,
647 .of_match = fsl_i2c_ids,
648 .probe = fsl_i2c_probe,
649 .ofdata_to_platdata = fsl_i2c_ofdata_to_platdata,
650 .priv_auto_alloc_size = sizeof(struct fsl_i2c_dev),
651 .ops = &fsl_i2c_ops,
652};
653
654#endif /* CONFIG_DM_I2C */