blob: 8160b28f784aed7fd2a1990845886e6923fbb46a [file] [log] [blame]
Jon Loeliger9553df82007-10-16 15:26:51 -05001/*
Timur Tabiba8e76b2011-04-11 14:18:22 -05002 * Copyright 2007-2011 Freescale Semiconductor, Inc.
Jon Loeliger9553df82007-10-16 15:26:51 -05003 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9/*
10 * MPC8610HPCD board configuration file
Jon Loeliger9553df82007-10-16 15:26:51 -050011 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
York Sun9ae14ca2015-08-18 12:35:52 -070016#define CONFIG_DISPLAY_BOARDINFO
17
Jon Loeliger9553df82007-10-16 15:26:51 -050018/* High Level Configuration Options */
Jon Loeliger9553df82007-10-16 15:26:51 -050019#define CONFIG_MPC8610 1 /* MPC8610 specific */
20#define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */
Jon Loeliger9553df82007-10-16 15:26:51 -050021#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
22
Wolfgang Denk2ae18242010-10-06 09:05:45 +020023#define CONFIG_SYS_TEXT_BASE 0xfff00000
24
York Sun070ba562007-10-31 14:59:04 -050025
26/* video */
Timur Tabiba8e76b2011-04-11 14:18:22 -050027#define CONFIG_FSL_DIU_FB
28
Timur Tabi7d3053f2011-02-15 17:09:19 -060029#ifdef CONFIG_FSL_DIU_FB
30#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
31#define CONFIG_VIDEO
Timur Tabie69e5202010-08-31 19:56:43 -050032#define CONFIG_CMD_BMP
York Sun070ba562007-10-31 14:59:04 -050033#define CONFIG_CFB_CONSOLE
Timur Tabi7d3053f2011-02-15 17:09:19 -060034#define CONFIG_VIDEO_SW_CURSOR
York Sun070ba562007-10-31 14:59:04 -050035#define CONFIG_VGA_AS_SINGLE_DEVICE
Timur Tabie69e5202010-08-31 19:56:43 -050036#define CONFIG_VIDEO_LOGO
37#define CONFIG_VIDEO_BMP_LOGO
York Sun070ba562007-10-31 14:59:04 -050038#endif
39
Jon Loeliger9553df82007-10-16 15:26:51 -050040#ifdef RUN_DIAG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_DIAG_ADDR 0xff800000
Jon Loeliger9553df82007-10-16 15:26:51 -050042#endif
43
Becky Bruce1266df82008-11-03 15:44:01 -060044/*
45 * virtual address to be used for temporary mappings. There
46 * should be 128k free at this VA.
47 */
48#define CONFIG_SYS_SCRATCH_VA 0xc0000000
49
Jon Loeliger9553df82007-10-16 15:26:51 -050050#define CONFIG_PCI 1 /* Enable PCI/PCIE*/
51#define CONFIG_PCI1 1 /* PCI controler 1 */
52#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
53#define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
54#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000055#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala8ba93f62008-10-21 18:06:15 -050056#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Becky Bruce031976f2008-01-23 16:31:02 -060057#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Jon Loeliger9553df82007-10-16 15:26:51 -050058
59#define CONFIG_ENV_OVERWRITE
Jon Loeliger9553df82007-10-16 15:26:51 -050060#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
61
Peter Tyser4bbfd3e2010-10-07 22:32:48 -050062#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
Becky Bruce31d82672008-05-08 19:02:12 -050063#define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */
Jon Loeliger9553df82007-10-16 15:26:51 -050064#define CONFIG_ALTIVEC 1
65
66/*
67 * L2CR setup -- make sure this is right for your board!
68 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_L2
Jon Loeliger9553df82007-10-16 15:26:51 -050070#define L2_INIT 0
York Suna8778802007-10-29 13:58:39 -050071#define L2_ENABLE (L2CR_L2E |0x00100000 )
Jon Loeliger9553df82007-10-16 15:26:51 -050072
73#ifndef CONFIG_SYS_CLK_FREQ
74#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
75#endif
76
77#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
York Suna8778802007-10-29 13:58:39 -050078#define CONFIG_MISC_INIT_R 1
Jon Loeliger9553df82007-10-16 15:26:51 -050079
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
81#define CONFIG_SYS_MEMTEST_END 0x00400000
Jon Loeliger9553df82007-10-16 15:26:51 -050082
83/*
84 * Base addresses -- Note these are effective addresses where the
85 * actual resources get mapped (not physical addresses)
86 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
88#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
89#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Jon Loeliger9553df82007-10-16 15:26:51 -050090
Jon Loeligerf6987382008-11-20 14:02:56 -060091#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
92#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
Kumar Galaad19e7a2009-08-05 07:59:35 -050093#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
Jon Loeligerf6987382008-11-20 14:02:56 -060094
Jon Loeliger39aa1a72008-08-26 15:01:36 -050095/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -070096#define CONFIG_SYS_FSL_DDR2
Jon Loeliger39aa1a72008-08-26 15:01:36 -050097#undef CONFIG_FSL_DDR_INTERACTIVE
98#define CONFIG_SPD_EEPROM /* Use SPD for DDR */
99#define CONFIG_DDR_SPD
100
101#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
102#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
105#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Becky Bruce1266df82008-11-03 15:44:01 -0600106#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
Jon Loeliger9553df82007-10-16 15:26:51 -0500107#define CONFIG_VERY_BIG_RAM
108
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500109#define CONFIG_NUM_DDR_CONTROLLERS 1
110#define CONFIG_DIMM_SLOTS_PER_CTLR 1
111#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Jon Loeliger9553df82007-10-16 15:26:51 -0500112
Kumar Galac39f44d2011-01-31 22:18:47 -0600113#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500114
115/* These are used when DDR doesn't use SPD. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
Jon Loeliger9553df82007-10-16 15:26:51 -0500117
118#if 0 /* TODO */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
120#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
121#define CONFIG_SYS_DDR_TIMING_3 0x00000000
122#define CONFIG_SYS_DDR_TIMING_0 0x00260802
123#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
124#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
125#define CONFIG_SYS_DDR_MODE_1 0x00480432
126#define CONFIG_SYS_DDR_MODE_2 0x00000000
127#define CONFIG_SYS_DDR_INTERVAL 0x06180100
128#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
129#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
130#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
131#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
132#define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
133#define CONFIG_SYS_DDR_CONTROL2 0x04400010
Jon Loeliger9553df82007-10-16 15:26:51 -0500134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
136#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
137#define CONFIG_SYS_DDR_SBE 0x000f0000
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500138
Jon Loeliger9553df82007-10-16 15:26:51 -0500139#endif
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500140
Jon Loeliger9553df82007-10-16 15:26:51 -0500141
Jon Loeligerad8f8682008-01-15 13:42:41 -0600142#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_I2C_EEPROM_NXID
Jean-Christophe PLAGNIOL-VILLARD32628c52008-08-30 23:54:58 +0200144#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
146#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
Jon Loeliger9553df82007-10-16 15:26:51 -0500147
148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */
150#define CONFIG_SYS_FLASH_BASE2 0xf8000000
Jon Loeliger9553df82007-10-16 15:26:51 -0500151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
Jon Loeliger9553df82007-10-16 15:26:51 -0500153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */
155#define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/
Jon Loeliger9553df82007-10-16 15:26:51 -0500156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */
158#define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */
Jon Loeliger9553df82007-10-16 15:26:51 -0500159#if 0 /* TODO */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_BR2_PRELIM 0xf0000000
161#define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */
Jon Loeliger9553df82007-10-16 15:26:51 -0500162#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */
164#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
Jon Loeliger9553df82007-10-16 15:26:51 -0500165
166
Jason Jin761421c2007-10-29 19:26:21 +0800167#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
Jon Loeliger9553df82007-10-16 15:26:51 -0500168#define PIXIS_BASE 0xe8000000 /* PIXIS registers */
169#define PIXIS_ID 0x0 /* Board ID at offset 0 */
170#define PIXIS_VER 0x1 /* Board version at offset 1 */
171#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
172#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
173#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */
174#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
York Suna8778802007-10-29 13:58:39 -0500175#define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/
Jon Loeliger9553df82007-10-16 15:26:51 -0500176#define PIXIS_VCTL 0x10 /* VELA Control Register */
177#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
178#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
179#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
180#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
181#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
182#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
183#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Timur Tabi2feb4af2010-03-31 17:44:13 -0500184#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */
Jon Loeliger9553df82007-10-16 15:26:51 -0500185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
187#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
Jon Loeliger9553df82007-10-16 15:26:51 -0500188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#undef CONFIG_SYS_FLASH_CHECKSUM
190#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
191#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200192#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Becky Brucebf9a8c32008-11-05 14:55:35 -0600193#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
Jon Loeliger9553df82007-10-16 15:26:51 -0500194
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200195#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_FLASH_CFI
197#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeliger9553df82007-10-16 15:26:51 -0500198
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
200#define CONFIG_SYS_RAMBOOT
Jon Loeliger9553df82007-10-16 15:26:51 -0500201#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#undef CONFIG_SYS_RAMBOOT
Jon Loeliger9553df82007-10-16 15:26:51 -0500203#endif
204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#if defined(CONFIG_SYS_RAMBOOT)
Jon Loeliger9553df82007-10-16 15:26:51 -0500206#undef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_SDRAM_SIZE 256
Jon Loeliger9553df82007-10-16 15:26:51 -0500208#endif
209
210#undef CONFIG_CLOCKS_IN_MHZ
211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_INIT_RAM_LOCK 1
213#ifndef CONFIG_SYS_INIT_RAM_LOCK
214#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Jon Loeliger9553df82007-10-16 15:26:51 -0500215#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */
Jon Loeliger9553df82007-10-16 15:26:51 -0500217#endif
Wolfgang Denk553f0982010-10-26 13:32:32 +0200218#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Jon Loeliger9553df82007-10-16 15:26:51 -0500219
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200220#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeliger9553df82007-10-16 15:26:51 -0500222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
224#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
Jon Loeliger9553df82007-10-16 15:26:51 -0500225
226/* Serial Port */
227#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_NS16550_SERIAL
229#define CONFIG_SYS_NS16550_REG_SIZE 1
230#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeliger9553df82007-10-16 15:26:51 -0500231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeliger9553df82007-10-16 15:26:51 -0500233 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
234
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
236#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeliger9553df82007-10-16 15:26:51 -0500237
238/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_HUSH_PARSER
Jon Loeliger9553df82007-10-16 15:26:51 -0500240
241/*
242 * Pass open firmware flat tree to kernel
243 */
Jon Loeliger1df170f2008-01-04 12:07:27 -0600244#define CONFIG_OF_LIBFDT 1
245#define CONFIG_OF_BOARD_SETUP 1
246#define CONFIG_OF_STDOUT_VIA_ALIAS 1
247
Jon Loeliger9553df82007-10-16 15:26:51 -0500248
249/* maximum size of the flat tree (8K) */
250#define OF_FLAT_TREE_MAX_SIZE 8192
251
Jon Loeliger9553df82007-10-16 15:26:51 -0500252/*
253 * I2C
254 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200255#define CONFIG_SYS_I2C
256#define CONFIG_SYS_I2C_FSL
257#define CONFIG_SYS_FSL_I2C_SPEED 400000
258#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
259#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
260#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Jon Loeliger9553df82007-10-16 15:26:51 -0500261
262/*
263 * General PCI
264 * Addresses are mapped 1-1.
265 */
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600266#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
267#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
268#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600270#define CONFIG_SYS_PCI1_IO_BUS 0x0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600272#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Jon Loeliger9553df82007-10-16 15:26:51 -0500274
Jon Loeliger9553df82007-10-16 15:26:51 -0500275/* controller 1, Base address 0xa000 */
Kumar Galab8526212010-12-17 10:42:33 -0600276#define CONFIG_SYS_PCIE1_NAME "ULI"
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600277#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
278#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600280#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
282#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
Jon Loeliger9553df82007-10-16 15:26:51 -0500283
284/* controller 2, Base Address 0x9000 */
Kumar Galab8526212010-12-17 10:42:33 -0600285#define CONFIG_SYS_PCIE2_NAME "Slot 1"
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600286#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
287#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600289#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
291#define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */
Jon Loeliger9553df82007-10-16 15:26:51 -0500292
293
294#if defined(CONFIG_PCI)
295
296#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
297
Jon Loeliger9553df82007-10-16 15:26:51 -0500298#define CONFIG_PCI_PNP /* do pci plug-and-play */
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600299#define CONFIG_CMD_REGINFO
Jon Loeliger9553df82007-10-16 15:26:51 -0500300
Roy Zang7c2221e2008-01-15 16:38:38 +0800301#define CONFIG_ULI526X
302#ifdef CONFIG_ULI526X
Roy Zang1d8a49e2007-09-13 18:52:28 +0800303#endif
Jon Loeliger9553df82007-10-16 15:26:51 -0500304
Jon Loeliger9553df82007-10-16 15:26:51 -0500305/************************************************************
306 * USB support
307 ************************************************************/
York Sun070ba562007-10-31 14:59:04 -0500308#define CONFIG_PCI_OHCI 1
309#define CONFIG_USB_OHCI_NEW 1
Jon Loeliger9553df82007-10-16 15:26:51 -0500310#define CONFIG_USB_KEYBOARD 1
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +0200311#define CONFIG_SYS_STDIO_DEREGISTER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_USB_EVENT_POLL 1
313#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
314#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
315#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
Jon Loeliger9553df82007-10-16 15:26:51 -0500316
317#if !defined(CONFIG_PCI_PNP)
318#define PCI_ENET0_IOADDR 0xe0000000
319#define PCI_ENET0_MEMADDR 0xe0000000
320#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
321#endif
322
323#define CONFIG_DOS_PARTITION
324#define CONFIG_SCSI_AHCI
325
326#ifdef CONFIG_SCSI_AHCI
Rob Herring344ca0b2013-08-24 10:10:54 -0500327#define CONFIG_LIBATA
Jon Loeliger9553df82007-10-16 15:26:51 -0500328#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
330#define CONFIG_SYS_SCSI_MAX_LUN 1
331#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
332#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Jon Loeliger9553df82007-10-16 15:26:51 -0500333#endif
334
335#endif /* CONFIG_PCI */
336
337/*
338 * BAT0 2G Cacheable, non-guarded
339 * 0x0000_0000 2G DDR
340 */
Timur Tabi9ff32d82010-03-29 12:51:07 -0500341#define CONFIG_SYS_DBAT0L (BATL_PP_RW)
342#define CONFIG_SYS_IBAT0L (BATL_PP_RW)
Jon Loeliger9553df82007-10-16 15:26:51 -0500343
344/*
345 * BAT1 1G Cache-inhibited, guarded
346 * 0x8000_0000 256M PCI-1 Memory
347 * 0xa000_0000 256M PCI-Express 1 Memory
348 * 0x9000_0000 256M PCI-Express 2 Memory
349 */
350
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500352 | BATL_GUARDEDSTORAGE)
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600353#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
355#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
Jon Loeliger9553df82007-10-16 15:26:51 -0500356
357/*
Jason Jinf3bceaa2007-10-26 18:31:59 +0800358 * BAT2 16M Cache-inhibited, guarded
Jon Loeliger9553df82007-10-16 15:26:51 -0500359 * 0xe100_0000 1M PCI-1 I/O
Jon Loeliger9553df82007-10-16 15:26:51 -0500360 */
361
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500363 | BATL_GUARDEDSTORAGE)
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600364#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
366#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
Jon Loeliger9553df82007-10-16 15:26:51 -0500367
368/*
Becky Bruce104992f2008-11-02 18:19:32 -0600369 * BAT3 4M Cache-inhibited, guarded
370 * 0xe000_0000 4M CCSR
371 */
372
373#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
374 | BATL_GUARDEDSTORAGE)
375#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
376#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
377#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
378
Jon Loeligerf6987382008-11-20 14:02:56 -0600379#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
380#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
381 | BATL_PP_RW | BATL_CACHEINHIBIT \
382 | BATL_GUARDEDSTORAGE)
383#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
384 | BATU_BL_1M | BATU_VS | BATU_VP)
385#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
386 | BATL_PP_RW | BATL_CACHEINHIBIT)
387#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
388#endif
389
Becky Bruce104992f2008-11-02 18:19:32 -0600390/*
391 * BAT4 32M Cache-inhibited, guarded
Jason Jinf3bceaa2007-10-26 18:31:59 +0800392 * 0xe200_0000 1M PCI-Express 2 I/O
Jon Loeliger9553df82007-10-16 15:26:51 -0500393 * 0xe300_0000 1M PCI-Express 1 I/O
Jon Loeliger9553df82007-10-16 15:26:51 -0500394 */
395
Becky Bruce104992f2008-11-02 18:19:32 -0600396#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500397 | BATL_GUARDEDSTORAGE)
Becky Bruce104992f2008-11-02 18:19:32 -0600398#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
399#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
Jon Loeliger9553df82007-10-16 15:26:51 -0500401
Becky Bruce104992f2008-11-02 18:19:32 -0600402
Jon Loeliger9553df82007-10-16 15:26:51 -0500403/*
404 * BAT5 128K Cacheable, non-guarded
405 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
406 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
408#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
409#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
410#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
Jon Loeliger9553df82007-10-16 15:26:51 -0500411
412/*
413 * BAT6 256M Cache-inhibited, guarded
414 * 0xf000_0000 256M FLASH
415 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500417 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
419#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
420#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
Jon Loeliger9553df82007-10-16 15:26:51 -0500421
Becky Brucebf9a8c32008-11-05 14:55:35 -0600422/* Map the last 1M of flash where we're running from reset */
423#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
424 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200425#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
Becky Brucebf9a8c32008-11-05 14:55:35 -0600426#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
427 | BATL_MEMCOHERENCE)
428#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
429
Jon Loeliger9553df82007-10-16 15:26:51 -0500430/*
431 * BAT7 4M Cache-inhibited, guarded
432 * 0xe800_0000 4M PIXIS
433 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500435 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
437#define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
438#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
Jon Loeliger9553df82007-10-16 15:26:51 -0500439
440
441/*
442 * Environment
443 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200445#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200447#define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */
448#define CONFIG_ENV_SIZE 0x2000
Jon Loeliger9553df82007-10-16 15:26:51 -0500449#else
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200450#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200452#define CONFIG_ENV_SIZE 0x2000
Jon Loeliger9553df82007-10-16 15:26:51 -0500453#endif
454
455#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeliger9553df82007-10-16 15:26:51 -0500457
458
459/*
460 * BOOTP options
461 */
462#define CONFIG_BOOTP_BOOTFILESIZE
463#define CONFIG_BOOTP_BOOTPATH
464#define CONFIG_BOOTP_GATEWAY
465#define CONFIG_BOOTP_HOSTNAME
466
467
468/*
469 * Command line configuration.
470 */
Jon Loeliger9553df82007-10-16 15:26:51 -0500471#define CONFIG_CMD_PING
472#define CONFIG_CMD_I2C
473#define CONFIG_CMD_MII
474
Jon Loeliger9553df82007-10-16 15:26:51 -0500475#if defined(CONFIG_PCI)
476#define CONFIG_CMD_PCI
477#define CONFIG_CMD_SCSI
478#define CONFIG_CMD_EXT2
York Sun070ba562007-10-31 14:59:04 -0500479#define CONFIG_CMD_USB
Jon Loeliger9553df82007-10-16 15:26:51 -0500480#endif
481
482
Jason Jin3473ab72008-05-13 11:50:36 +0800483#define CONFIG_WATCHDOG /* watchdog enabled */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200484#define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
Jon Loeliger9553df82007-10-16 15:26:51 -0500485
486/*
487 * Miscellaneous configurable options
488 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489#define CONFIG_SYS_LONGHELP /* undef to save memory */
Timur Tabi6bee7642008-01-16 15:48:12 -0600490#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jon Loeliger9553df82007-10-16 15:26:51 -0500492
493#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200494#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jon Loeliger9553df82007-10-16 15:26:51 -0500495#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200496#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jon Loeliger9553df82007-10-16 15:26:51 -0500497#endif
498
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
500#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
501#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Jon Loeliger9553df82007-10-16 15:26:51 -0500502
503/*
504 * For booting Linux, the board info and command line data
505 * have to be in the first 8 MB of memory, since this is
506 * the maximum mapped by the Linux kernel during initialization.
507 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200508#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Jon Loeliger9553df82007-10-16 15:26:51 -0500509
Jon Loeliger9553df82007-10-16 15:26:51 -0500510#if defined(CONFIG_CMD_KGDB)
511#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Jon Loeliger9553df82007-10-16 15:26:51 -0500512#endif
513
514/*
515 * Environment Configuration
516 */
517#define CONFIG_IPADDR 192.168.1.100
518
519#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000520#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000521#define CONFIG_BOOTFILE "uImage"
Jon Loeliger9553df82007-10-16 15:26:51 -0500522#define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin
523
524#define CONFIG_SERVERIP 192.168.1.1
525#define CONFIG_GATEWAYIP 192.168.1.1
526#define CONFIG_NETMASK 255.255.255.0
527
528/* default location for tftp and bootm */
529#define CONFIG_LOADADDR 1000000
530
531#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
532#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
533
534#define CONFIG_BAUDRATE 115200
535
536#if defined(CONFIG_PCI1)
537#define PCI_ENV \
538 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
539 "echo e;md ${a}e00 9\0" \
540 "pci1regs=setenv a e0008; run pcireg\0" \
541 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
542 "pci d.w $b.0 56 1\0" \
543 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
544 "pci w.w $b.0 56 ffff\0" \
545 "pci1err=setenv a e0008; run pcierr\0" \
546 "pci1errc=setenv a e0008; run pcierrc\0"
547#else
548#define PCI_ENV ""
549#endif
550
551#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
552#define PCIE_ENV \
553 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
554 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
555 "pcie1regs=setenv a e000a; run pciereg\0" \
556 "pcie2regs=setenv a e0009; run pciereg\0" \
557 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
558 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
559 "pci d $b.0 130 1\0" \
560 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
561 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
562 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
563 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
564 "pcie1err=setenv a e000a; run pcieerr\0" \
565 "pcie2err=setenv a e0009; run pcieerr\0" \
566 "pcie1errc=setenv a e000a; run pcieerrc\0" \
567 "pcie2errc=setenv a e0009; run pcieerrc\0"
568#else
569#define PCIE_ENV ""
570#endif
571
572#define DMA_ENV \
573 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
574 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
575 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
576 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
577 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
578 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
579 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
580 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
581
York Sun18153382007-10-29 13:57:53 -0500582#ifdef ENV_DEBUG
Jon Loeliger9553df82007-10-16 15:26:51 -0500583#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200584"netdev=eth0\0" \
585"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
586"tftpflash=tftpboot $loadaddr $uboot; " \
587 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
588 " +$filesize; " \
589 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
590 " +$filesize; " \
591 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
592 " $filesize; " \
593 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
594 " +$filesize; " \
595 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
596 " $filesize\0" \
597"consoledev=ttyS0\0" \
598"ramdiskaddr=2000000\0" \
599"ramdiskfile=8610hpcd/ramdisk.uboot\0" \
600"fdtaddr=c00000\0" \
601"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
602"bdev=sda3\0" \
603"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
604"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
605"maxcpus=1" \
606"eoi=mw e00400b0 0\0" \
607"iack=md e00400a0 1\0" \
608"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
Jon Loeliger9553df82007-10-16 15:26:51 -0500609 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
610 "md ${a}f00 5\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200611"ddr1regs=setenv a e0002; run ddrreg\0" \
612"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
Jon Loeliger9553df82007-10-16 15:26:51 -0500613 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
614 "md ${a}e60 1; md ${a}ef0 1d\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200615"guregs=setenv a e00e0; run gureg\0" \
616"mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
617"mcmregs=setenv a e0001; run mcmreg\0" \
618"diuregs=md e002c000 1d\0" \
619"dium=mw e002c01c\0" \
620"diuerr=md e002c014 1\0" \
621"pmregs=md e00e1000 2b\0" \
622"lawregs=md e0000c08 4b\0" \
623"lbcregs=md e0005000 36\0" \
624"dma0regs=md e0021100 12\0" \
625"dma1regs=md e0021180 12\0" \
626"dma2regs=md e0021200 12\0" \
627"dma3regs=md e0021280 12\0" \
Jon Loeliger9553df82007-10-16 15:26:51 -0500628 PCI_ENV \
629 PCIE_ENV \
630 DMA_ENV
York Sun18153382007-10-29 13:57:53 -0500631#else
Marek Vasut5368c552012-09-23 17:41:24 +0200632#define CONFIG_EXTRA_ENV_SETTINGS \
633 "netdev=eth0\0" \
634 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
635 "consoledev=ttyS0\0" \
636 "ramdiskaddr=2000000\0" \
637 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
638 "fdtaddr=c00000\0" \
639 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
640 "bdev=sda3\0"
York Sun18153382007-10-29 13:57:53 -0500641#endif
Jon Loeliger9553df82007-10-16 15:26:51 -0500642
643#define CONFIG_NFSBOOTCOMMAND \
644 "setenv bootargs root=/dev/nfs rw " \
645 "nfsroot=$serverip:$rootpath " \
646 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
647 "console=$consoledev,$baudrate $othbootargs;" \
648 "tftp $loadaddr $bootfile;" \
Jon Loeliger1df170f2008-01-04 12:07:27 -0600649 "tftp $fdtaddr $fdtfile;" \
650 "bootm $loadaddr - $fdtaddr"
Jon Loeliger9553df82007-10-16 15:26:51 -0500651
652#define CONFIG_RAMBOOTCOMMAND \
653 "setenv bootargs root=/dev/ram rw " \
654 "console=$consoledev,$baudrate $othbootargs;" \
655 "tftp $ramdiskaddr $ramdiskfile;" \
656 "tftp $loadaddr $bootfile;" \
Jon Loeliger1df170f2008-01-04 12:07:27 -0600657 "tftp $fdtaddr $fdtfile;" \
658 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeliger9553df82007-10-16 15:26:51 -0500659
660#define CONFIG_BOOTCOMMAND \
661 "setenv bootargs root=/dev/$bdev rw " \
662 "console=$consoledev,$baudrate $othbootargs;" \
663 "tftp $loadaddr $bootfile;" \
Jon Loeliger1df170f2008-01-04 12:07:27 -0600664 "tftp $fdtaddr $fdtfile;" \
665 "bootm $loadaddr - $fdtaddr"
Jon Loeliger9553df82007-10-16 15:26:51 -0500666
667#endif /* __CONFIG_H */