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Rafal Jaworowski8993e542007-07-27 14:43:59 +02001/*
Wolfgang Denk3b74e7e2009-05-16 10:47:45 +02002 * (C) Copyright 2007-2009 DENX Software Engineering
Rafal Jaworowski8993e542007-07-27 14:43:59 +02003 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
Rafal Jaworowski8993e542007-07-27 14:43:59 +02005 */
6
7/*
Wolfgang Denk72601d02009-05-16 10:47:41 +02008 * MPC5121ADS board configuration file
Rafal Jaworowski8993e542007-07-27 14:43:59 +02009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Wolfgang Denk72601d02009-05-16 10:47:41 +020014#define CONFIG_MPC5121ADS 1
Anatolij Gustschin10e99d82014-10-21 13:46:59 +020015#define CONFIG_DISPLAY_BOARDINFO
Anatolij Gustschin10e99d82014-10-21 13:46:59 +020016
Rafal Jaworowski8993e542007-07-27 14:43:59 +020017/*
Wolfgang Denk72601d02009-05-16 10:47:41 +020018 * Memory map for the MPC5121ADS board:
Rafal Jaworowski8993e542007-07-27 14:43:59 +020019 *
20 * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB)
21 * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
22 * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
23 * 0x8200_0000 - 0x8200_001F CPLD (32 B)
John Rigby5f91db72008-02-26 09:38:14 -070024 * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB)
25 * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB)
26 * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
Rafal Jaworowski8993e542007-07-27 14:43:59 +020027 * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
28 */
29
30/*
31 * High Level Configuration Options
32 */
33#define CONFIG_E300 1 /* E300 Family */
York Sun0e1bad42008-05-05 10:20:01 -050034
Wolfgang Denk2ae18242010-10-06 09:05:45 +020035#define CONFIG_SYS_TEXT_BASE 0xFFF00000
36
York Sun0e1bad42008-05-05 10:20:01 -050037/* video */
Timur Tabi7d3053f2011-02-15 17:09:19 -060038#ifdef CONFIG_FSL_DIU_FB
39#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100)
40#define CONFIG_VIDEO
Timur Tabie69e5202010-08-31 19:56:43 -050041#define CONFIG_CMD_BMP
York Sun0e1bad42008-05-05 10:20:01 -050042#define CONFIG_CFB_CONSOLE
Timur Tabi7d3053f2011-02-15 17:09:19 -060043#define CONFIG_VIDEO_SW_CURSOR
York Sun0e1bad42008-05-05 10:20:01 -050044#define CONFIG_VGA_AS_SINGLE_DEVICE
Timur Tabie69e5202010-08-31 19:56:43 -050045#define CONFIG_VIDEO_LOGO
46#define CONFIG_VIDEO_BMP_LOGO
York Sun0e1bad42008-05-05 10:20:01 -050047#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +020048
John Rigby5f91db72008-02-26 09:38:14 -070049/* CONFIG_PCI is defined at config time */
Rafal Jaworowski8993e542007-07-27 14:43:59 +020050
Wolfgang Denk72601d02009-05-16 10:47:41 +020051#ifdef CONFIG_MPC5121ADS_REV2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */
Martha Marxf31c49d2008-05-29 14:23:25 -040053#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
Martha Marxf31c49d2008-05-29 14:23:25 -040055#define CONFIG_PCI
56#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +020057
58#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
York Sun0e1bad42008-05-05 10:20:01 -050059#define CONFIG_MISC_INIT_R
Rafal Jaworowski8993e542007-07-27 14:43:59 +020060
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_IMMR 0x80000000
Rafal Jaworowski8993e542007-07-27 14:43:59 +020062
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
64#define CONFIG_SYS_MEMTEST_END 0x00400000
Rafal Jaworowski8993e542007-07-27 14:43:59 +020065
66/*
67 * DDR Setup - manually set all parameters as there's no SPD etc.
68 */
Wolfgang Denk72601d02009-05-16 10:47:41 +020069#ifdef CONFIG_MPC5121ADS_REV2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Martha Marxf31c49d2008-05-29 14:23:25 -040071#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_DDR_SIZE 512 /* MB */
Martha Marxf31c49d2008-05-29 14:23:25 -040073#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
75#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Anatolij Gustschinb9947bb2010-04-24 19:27:08 +020076#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
Rafal Jaworowski8993e542007-07-27 14:43:59 +020077
Anatolij Gustschin5d937e82010-04-24 19:27:07 +020078#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036
79
Rafal Jaworowski8993e542007-07-27 14:43:59 +020080/* DDR Controller Configuration
Wolfgang Denkb1b54e32007-08-02 21:27:46 +020081 *
82 * SYS_CFG:
83 * [31:31] MDDRC Soft Reset: Diabled
84 * [30:30] DRAM CKE pin: Enabled
85 * [29:29] DRAM CLK: Enabled
86 * [28:28] Command Mode: Enabled (For initialization only)
87 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
88 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
89 * [20:19] Read Test: DON'T USE
90 * [18:18] Self Refresh: Enabled
91 * [17:17] 16bit Mode: Disabled
92 * [16:13] Ready Delay: 2
93 * [12:12] Half DQS Delay: Disabled
94 * [11:11] Quarter DQS Delay: Disabled
95 * [10:08] Write Delay: 2
96 * [07:07] Early ODT: Disabled
97 * [06:06] On DIE Termination: Disabled
98 * [05:05] FIFO Overflow Clear: DON'T USE here
99 * [04:04] FIFO Underflow Clear: DON'T USE here
100 * [03:03] FIFO Overflow Pending: DON'T USE here
101 * [02:02] FIFO Underlfow Pending: DON'T USE here
102 * [01:01] FIFO Overlfow Enabled: Enabled
103 * [00:00] FIFO Underflow Enabled: Enabled
104 * TIME_CFG0
105 * [31:16] DRAM Refresh Time: 0 CSB clocks
106 * [15:8] DRAM Command Time: 0 CSB clocks
107 * [07:00] DRAM Precharge Time: 0 CSB clocks
108 * TIME_CFG1
109 * [31:26] DRAM tRFC:
110 * [25:21] DRAM tWR1:
111 * [20:17] DRAM tWRT1:
112 * [16:11] DRAM tDRR:
113 * [10:05] DRAM tRC:
114 * [04:00] DRAM tRAS:
115 * TIME_CFG2
116 * [31:28] DRAM tRCD:
117 * [27:23] DRAM tFAW:
118 * [22:19] DRAM tRTW1:
119 * [18:15] DRAM tCCD:
120 * [14:10] DRAM tRTP:
121 * [09:05] DRAM tRP:
122 * [04:00] DRAM tRPA
123 */
Wolfgang Denk72601d02009-05-16 10:47:41 +0200124#ifdef CONFIG_MPC5121ADS_REV2
Martha M Stan054197b2009-09-21 14:07:14 -0400125#define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168
127#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864
Martha Marxf31c49d2008-05-29 14:23:25 -0400128#else
Martha M Stan054197b2009-09-21 14:07:14 -0400129#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00
130#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
131#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
Martha Marxf31c49d2008-05-29 14:23:25 -0400132#endif
Martha M Stan054197b2009-09-21 14:07:14 -0400133#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200134
Martha M Stana5aa3992009-09-21 14:08:00 -0400135#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xEA802B00
136#define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189
137#define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35310864
138
Martha M Stan054197b2009-09-21 14:07:14 -0400139#define CONFIG_SYS_DDRCMD_NOP 0x01380000
140#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
141#define CONFIG_SYS_DDRCMD_EM2 0x01020000
142#define CONFIG_SYS_DDRCMD_EM3 0x01030000
143#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000
144#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
Martha M Stana5aa3992009-09-21 14:08:00 -0400145
146#define DDRCMD_EMR_OCD(pr, ohm) ( \
147 (1 << 24) | /* MDDRC Command Request */ \
148 (1 << 16) | /* MODE Reg BA[2:0] */ \
149 (0 << 12) | /* Outputs 0=Enabled */ \
150 (0 << 11) | /* RDQS */ \
151 (1 << 10) | /* DQS# */ \
152 (pr << 7) | /* OCD prog 7=deflt,0=exit */ \
153 /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \
154 ((ohm & 0x2) << 5)| /* Rtt1 */ \
155 (0 << 3) | /* additive posted CAS# */ \
156 ((ohm & 0x1) << 2)| /* Rtt0 */ \
157 (0 << 0) | /* Output Drive Strength */ \
158 (0 << 0)) /* DLL Enable 0=Normal */
159
160#define CONFIG_SYS_DDRCMD_OCD_DEFAULT DDRCMD_EMR_OCD(7, 0)
161#define CONFIG_SYS_ELPIDA_OCD_EXIT DDRCMD_EMR_OCD(0, 0)
162
163#define DDRCMD_MODE_REG(cas, wr) ( \
164 (1 << 24) | /* MDDRC Command Request */ \
165 (0 << 16) | /* MODE Reg BA[2:0] */ \
166 ((wr-1) << 9)| /* Write Recovery */ \
167 (cas << 4) | /* CAS */ \
168 (0 << 3) | /* Burst Type:0=Sequential,1=Interleaved */ \
169 (2 << 0)) /* 4 or 8 Burst Length:0x2=4 0x3=8 */
170
171#define CONFIG_SYS_MICRON_INIT_DEV_OP DDRCMD_MODE_REG(3, 3)
172#define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDRCMD_MODE_REG(4, 4)
173#define CONFIG_SYS_ELPIDA_RES_DLL (DDRCMD_MODE_REG(4, 4) | (1 << 8))
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200174
175/* DDR Priority Manager Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
177#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
178#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
179#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
180#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
181#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
182#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
183#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
184#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
185#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
186#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
187#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
188#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
189#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
190#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
191#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
192#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
193#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
194#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
195#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
196#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
197#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
198#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200199
200/*
201 * NOR FLASH on the Local Bus
202 */
Martha Marxf31c49d2008-05-29 14:23:25 -0400203#undef CONFIG_BKUP_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200205#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Martha Marxf31c49d2008-05-29 14:23:25 -0400206#ifdef CONFIG_BKUP_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
208#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* max flash size in bytes */
Martha Marxf31c49d2008-05-29 14:23:25 -0400209#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */
211#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size in bytes */
Martha Marxf31c49d2008-05-29 14:23:25 -0400212#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
214#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
215#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
216#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#undef CONFIG_SYS_FLASH_CHECKSUM
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200219
220/*
Stefan Roese229549a2009-06-09 16:57:47 +0200221 * NAND FLASH
Wolfgang Denk13946922009-06-14 20:58:50 +0200222 * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
Stefan Roese229549a2009-06-09 16:57:47 +0200223 */
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200224#define CONFIG_CMD_NAND /* enable NAND support */
225#define CONFIG_JFFS2_NAND /* with JFFS2 on it */
Stefan Roese229549a2009-06-09 16:57:47 +0200226#define CONFIG_NAND_MPC5121_NFC
227#define CONFIG_SYS_NAND_BASE 0x40000000
228
229#define CONFIG_SYS_MAX_NAND_DEVICE 2
Stefan Roese229549a2009-06-09 16:57:47 +0200230#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
231
232/*
233 * Configuration parameters for MPC5121 NAND driver
234 */
235#define CONFIG_FSL_NFC_WIDTH 1
236#define CONFIG_FSL_NFC_WRITE_SIZE 2048
237#define CONFIG_FSL_NFC_SPARE_SIZE 64
238#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
239
240/*
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200241 * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
242 * window is 64KB
243 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_CPLD_BASE 0x82000000
245#define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */
Anatolij Gustschin676c6692013-02-08 00:03:44 +0000246#define CONFIG_SYS_CS2_START CONFIG_SYS_CPLD_BASE
247#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_CPLD_SIZE
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_SRAM_BASE 0x30000000
250#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
253#define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
254#define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200255
256/* Use SRAM for initial stack */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200258#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE /* Size of used area in RAM */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200259
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200260#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200262
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200263#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */
Stefan Roese229549a2009-06-09 16:57:47 +0200264#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
York Sun0e1bad42008-05-05 10:20:01 -0500265#ifdef CONFIG_FSL_DIU_FB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
York Sun0e1bad42008-05-05 10:20:01 -0500267#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
York Sun0e1bad42008-05-05 10:20:01 -0500269#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200270
271/*
272 * Serial Port
273 */
274#define CONFIG_CONS_INDEX 1
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200275
276/*
277 * Serial console configuration
278 */
279#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
Marek Vasutbfb31272012-09-16 16:07:24 +0200280#define CONFIG_SYS_PSC3
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200281#if CONFIG_PSC_CONSOLE != 3
282#error CONFIG_PSC_CONSOLE must be 3
283#endif
284#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_BAUDRATE_TABLE \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200286 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
287
288#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
289#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
290#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
291#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
292
293#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
294/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_HUSH_PARSER
296#ifdef CONFIG_SYS_HUSH_PARSER
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200297#endif
298
John Rigby5f91db72008-02-26 09:38:14 -0700299/*
Anatolij Gustschine5f53862013-02-08 00:03:45 +0000300 * Clocks in use
301 */
302#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
303 CLOCK_SCCR1_DDR_EN | \
304 CLOCK_SCCR1_FEC_EN | \
305 CLOCK_SCCR1_LPC_EN | \
306 CLOCK_SCCR1_NFC_EN | \
307 CLOCK_SCCR1_PATA_EN | \
308 CLOCK_SCCR1_PCI_EN | \
309 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
310 CLOCK_SCCR1_PSCFIFO_EN | \
311 CLOCK_SCCR1_TPR_EN)
312
313#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \
314 CLOCK_SCCR2_I2C_EN | \
315 CLOCK_SCCR2_MEM_EN | \
316 CLOCK_SCCR2_SPDIF_EN | \
317 CLOCK_SCCR2_USB1_EN | \
318 CLOCK_SCCR2_USB2_EN)
319
320/*
John Rigby5f91db72008-02-26 09:38:14 -0700321 * PCI
322 */
323#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000324#define CONFIG_PCI_INDIRECT_BRIDGE
John Rigby5f91db72008-02-26 09:38:14 -0700325
326/*
327 * General PCI
328 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
330#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
331#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
332#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
333#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
334#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
335#define CONFIG_SYS_PCI_IO_BASE 0x00000000
336#define CONFIG_SYS_PCI_IO_PHYS 0x84000000
337#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */
John Rigby5f91db72008-02-26 09:38:14 -0700338
339
340#define CONFIG_PCI_PNP /* do pci plug-and-play */
341
342#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
343
344#endif
345
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200346/* I2C */
347#define CONFIG_HARD_I2C /* I2C with hardware support */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200348#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
350#define CONFIG_SYS_I2C_SLAVE 0x7F
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200351#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200353#endif
354
355/*
Martha Marxabfbd0ae2009-01-26 10:45:07 -0700356 * IIM - IC Identification Module
357 */
Benoît Thébaudeau83306922013-04-23 10:17:42 +0000358#undef CONFIG_FSL_IIM
Martha Marxabfbd0ae2009-01-26 10:45:07 -0700359
360/*
Grzegorz Bernacki80020122007-10-09 13:58:24 +0200361 * EEPROM configuration
362 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
364#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
365#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
366#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
Grzegorz Bernacki80020122007-10-09 13:58:24 +0200367
368/*
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200369 * Ethernet configuration
370 */
371#define CONFIG_MPC512x_FEC 1
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200372#define CONFIG_PHY_ADDR 0x1
373#define CONFIG_MII 1 /* MII PHY management */
Martha Marxf31c49d2008-05-29 14:23:25 -0400374#define CONFIG_FEC_AN_TIMEOUT 1
John Rigbyef11df62008-08-05 17:38:57 -0600375#define CONFIG_HAS_ETH0
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200376
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200377/*
378 * Configure on-board RTC
379 */
Martha Marxf31c49d2008-05-29 14:23:25 -0400380#define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200382
383/*
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200384 * USB Support
385 */
386#define CONFIG_CMD_USB
387
388#if defined(CONFIG_CMD_USB)
389#define CONFIG_USB_EHCI /* Enable EHCI Support */
390#define CONFIG_USB_EHCI_FSL /* On a FSL platform */
391#define CONFIG_EHCI_MMIO_BIG_ENDIAN /* With big-endian regs */
392#define CONFIG_EHCI_DESC_BIG_ENDIAN
393#define CONFIG_EHCI_IS_TDI
394#define CONFIG_USB_STORAGE
395#endif
396
397/*
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200398 * Environment
399 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200400#define CONFIG_ENV_IS_IN_FLASH 1
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200401/* This has to be a multiple of the Flash sector size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200403#define CONFIG_ENV_SIZE 0x2000
Martha Marxf31c49d2008-05-29 14:23:25 -0400404#ifdef CONFIG_BKUP_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200405#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */
Martha Marxf31c49d2008-05-29 14:23:25 -0400406#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200407#define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
Martha Marxf31c49d2008-05-29 14:23:25 -0400408#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200409
410/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200411#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
412#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200413
414#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200416
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200417#define CONFIG_CMD_ASKENV
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200418#define CONFIG_CMD_DATE
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200419#define CONFIG_CMD_DHCP
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200420#define CONFIG_CMD_EEPROM
421#define CONFIG_CMD_EXT2
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200422#define CONFIG_CMD_I2C
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200423#define CONFIG_CMD_IDE
424#define CONFIG_CMD_JFFS2
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200425#define CONFIG_CMD_MII
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200426#define CONFIG_CMD_PING
427#define CONFIG_CMD_REGINFO
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200428
Martha Marxabfbd0ae2009-01-26 10:45:07 -0700429#undef CONFIG_CMD_FUSE
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200430
431#if defined(CONFIG_PCI)
432#define CONFIG_CMD_PCI
433#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200434
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200435/*
436 * Dynamic MTD partition support
437 */
438#define CONFIG_CMD_MTDPARTS
439#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
440#define CONFIG_FLASH_CFI_MTD
441#define MTDIDS_DEFAULT "nor0=fc000000.flash,nand0=mpc5121.nand"
442
443/*
444 * NOR flash layout:
445 *
446 * FC000000 - FEABFFFF 42.75 MiB User Data
447 * FEAC0000 - FFABFFFF 16 MiB Root File System
448 * FFAC0000 - FFEBFFFF 4 MiB Linux Kernel
449 * FFEC0000 - FFEFFFFF 256 KiB Device Tree
450 * FFF00000 - FFFFFFFF 1 MiB U-Boot (up to 512 KiB) and 2 x * env
451 *
452 * NAND flash layout: one big partition
453 */
454#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:43776k(user)," \
455 "16m(rootfs)," \
456 "4m(kernel)," \
457 "256k(dtb)," \
458 "1m(u-boot);" \
459 "mpc5121.nand:-(data)"
460
461
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200462#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
463
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700464#define CONFIG_DOS_PARTITION
465#define CONFIG_MAC_PARTITION
466#define CONFIG_ISO_PARTITION
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200467
468#define CONFIG_CMD_FAT
469#define CONFIG_SUPPORT_VFAT
470
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700471#endif /* defined(CONFIG_CMD_IDE) */
472
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200473/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474 * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
475 * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200476 * to 0xFFFF, watchdog timeouts after about 64s. For details refer
477 * to chapter 36 of the MPC5121e Reference Manual.
478 */
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100479/* #define CONFIG_WATCHDOG */ /* enable watchdog */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200481
482 /*
483 * Miscellaneous configurable options
484 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#define CONFIG_SYS_LONGHELP /* undef to save memory */
486#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200487
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200488#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200490#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200492#endif
493
494
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200495#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
496#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
497#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200498
499/*
500 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700501 * have to be in the first 256 MB of memory, since this is
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200502 * the maximum mapped by the Linux kernel during initialization.
503 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700504#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200505
506/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200507#define CONFIG_SYS_DCACHE_SIZE 32768
508#define CONFIG_SYS_CACHELINE_SIZE 32
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200509#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200510#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200511#endif
512
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200513#define CONFIG_SYS_HID0_INIT 0x000000000
Wolfgang Denke2b66fe2009-03-26 10:00:57 +0100514#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200515#define CONFIG_SYS_HID2 HID2_HBE
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200516
Becky Bruce31d82672008-05-08 19:02:12 -0500517#define CONFIG_HIGH_BATS 1 /* High BATs supported */
518
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200519#ifdef CONFIG_CMD_KGDB
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200520#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200521#endif
522
523/*
524 * Environment Configuration
525 */
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100526#define CONFIG_TIMESTAMP
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200527
Wolfgang Denk72601d02009-05-16 10:47:41 +0200528#define CONFIG_HOSTNAME mpc5121ads
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000529#define CONFIG_BOOTFILE "mpc5121ads/uImage"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000530#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200531
Wolfgang Denk8d103072008-01-13 23:37:50 +0100532#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200533
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200534#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200535#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
536
537#define CONFIG_BAUDRATE 115200
538
539#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100540 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200541 "echo"
542
543#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100544 "u-boot_addr_r=200000\0" \
Wolfgang Denk51e46e22008-08-26 15:01:28 +0200545 "kernel_addr_r=600000\0" \
546 "fdt_addr_r=880000\0" \
547 "ramdisk_addr_r=900000\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100548 "u-boot_addr=FFF00000\0" \
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200549 "kernel_addr=FFAC0000\0" \
Wolfgang Denk51e46e22008-08-26 15:01:28 +0200550 "fdt_addr=FFEC0000\0" \
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200551 "ramdisk_addr=FEAC0000\0" \
Wolfgang Denk72601d02009-05-16 10:47:41 +0200552 "ramdiskfile=mpc5121ads/uRamdisk\0" \
553 "u-boot=mpc5121ads/u-boot.bin\0" \
554 "bootfile=mpc5121ads/uImage\0" \
555 "fdtfile=mpc5121ads/mpc5121ads.dtb\0" \
Wolfgang Denk51e46e22008-08-26 15:01:28 +0200556 "rootpath=/opt/eldk/ppc_6xx\n" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200557 "netdev=eth0\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100558 "consdev=ttyPSC0\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200559 "nfsargs=setenv bootargs root=/dev/nfs rw " \
560 "nfsroot=${serverip}:${rootpath}\0" \
561 "ramargs=setenv bootargs root=/dev/ram rw\0" \
562 "addip=setenv bootargs ${bootargs} " \
563 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
564 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100565 "addtty=setenv bootargs ${bootargs} " \
566 "console=${consdev},${baudrate}\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200567 "flash_nfs=run nfsargs addip addtty;" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200568 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200569 "flash_self=run ramargs addip addtty;" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100570 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
571 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
572 "tftp ${fdt_addr_r} ${fdtfile};" \
573 "run nfsargs addip addtty;" \
574 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
575 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
576 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200577 "tftp ${fdt_addr_r} ${fdtfile};" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100578 "run ramargs addip addtty;" \
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100579 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
Detlev Zundela99715b2008-04-18 14:50:01 +0200580 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100581 "update=protect off ${u-boot_addr} +${filesize};" \
582 "era ${u-boot_addr} +${filesize};" \
583 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
584 "upd=run load update\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200585 ""
586
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200587#define CONFIG_BOOTCOMMAND "run flash_self"
588
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100589#define CONFIG_OF_LIBFDT 1
590#define CONFIG_OF_BOARD_SETUP 1
John Rigbyef11df62008-08-05 17:38:57 -0600591#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100592
593#define OF_CPU "PowerPC,5121@0"
John Rigbyef11df62008-08-05 17:38:57 -0600594#define OF_SOC_COMPAT "fsl,mpc5121-immr"
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100595#define OF_TBCLK (bd->bi_busfreq / 4)
John Rigbyac915282008-01-30 13:36:57 -0700596#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100597
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700598/*-----------------------------------------------------------------------
599 * IDE/ATA stuff
600 *-----------------------------------------------------------------------
601 */
602
603#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
604#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
605#undef CONFIG_IDE_LED /* LED for IDE not supported */
606
607#define CONFIG_IDE_RESET /* reset for IDE supported */
608#define CONFIG_IDE_PREINIT
609
610#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
611#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
612
613#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Wolfgang Denk3b74e7e2009-05-16 10:47:45 +0200614#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base()
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700615
616/* Offset for data I/O RefMan MPC5121EE Table 28-10 */
617#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
618
619/* Offset for normal register accesses */
620#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
621
622/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
623#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
624
625/* Interval between registers */
626#define CONFIG_SYS_ATA_STRIDE 4
627
Wolfgang Denk3b74e7e2009-05-16 10:47:45 +0200628#define ATA_BASE_ADDR get_pata_base()
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700629
630/*
631 * Control register bit definitions
632 */
633#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
634#define FSL_ATA_CTRL_ATA_RST_B 0x40000000
635#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
636#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
637#define FSL_ATA_CTRL_DMA_PENDING 0x08000000
638#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
639#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
640#define FSL_ATA_CTRL_IORDY_EN 0x01000000
641
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200642#endif /* __CONFIG_H */