blob: d621f2a9f96cc661612bdc568963a117af444a8f [file] [log] [blame]
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +02001/*
Hans de Goedebdcdf842014-11-29 23:54:25 +01002 * AXP221 and AXP223 driver
3 *
4 * IMPORTANT when making changes to this file check that the registers
5 * used are the same for the axp221 and axp223.
6 *
7 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +02008 * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#include <common.h>
14#include <errno.h>
Hans de Goede1d624a42015-04-25 14:07:37 +020015#include <asm/arch/pmic_bus.h>
Hans de Goede6944aff2015-10-03 15:18:33 +020016#include <axp_pmic.h>
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020017
18static u8 axp221_mvolt_to_cfg(int mvolt, int min, int max, int div)
19{
20 if (mvolt < min)
21 mvolt = min;
22 else if (mvolt > max)
23 mvolt = max;
24
25 return (mvolt - min) / div;
26}
27
Hans de Goede6944aff2015-10-03 15:18:33 +020028int axp_set_dcdc1(unsigned int mvolt)
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020029{
30 int ret;
31 u8 cfg = axp221_mvolt_to_cfg(mvolt, 1600, 3400, 100);
32
Hans de Goede50e0d5e2014-12-13 14:02:38 +010033 if (mvolt == 0)
Hans de Goede1d624a42015-04-25 14:07:37 +020034 return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1,
35 AXP221_OUTPUT_CTRL1_DCDC1_EN);
Hans de Goede50e0d5e2014-12-13 14:02:38 +010036
Hans de Goedebdcdf842014-11-29 23:54:25 +010037 ret = pmic_bus_write(AXP221_DCDC1_CTRL, cfg);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020038 if (ret)
39 return ret;
40
Hans de Goede1d624a42015-04-25 14:07:37 +020041 ret = pmic_bus_setbits(AXP221_OUTPUT_CTRL2,
42 AXP221_OUTPUT_CTRL2_DCDC1SW_EN);
Hans de Goede50e0d5e2014-12-13 14:02:38 +010043 if (ret)
44 return ret;
45
Hans de Goede1d624a42015-04-25 14:07:37 +020046 return pmic_bus_setbits(AXP221_OUTPUT_CTRL1,
47 AXP221_OUTPUT_CTRL1_DCDC1_EN);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020048}
49
Hans de Goede6944aff2015-10-03 15:18:33 +020050int axp_set_dcdc2(unsigned int mvolt)
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020051{
Hans de Goede50e0d5e2014-12-13 14:02:38 +010052 int ret;
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020053 u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20);
54
Hans de Goede50e0d5e2014-12-13 14:02:38 +010055 if (mvolt == 0)
Hans de Goede1d624a42015-04-25 14:07:37 +020056 return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1,
57 AXP221_OUTPUT_CTRL1_DCDC2_EN);
Hans de Goede50e0d5e2014-12-13 14:02:38 +010058
59 ret = pmic_bus_write(AXP221_DCDC2_CTRL, cfg);
60 if (ret)
61 return ret;
62
Hans de Goede1d624a42015-04-25 14:07:37 +020063 return pmic_bus_setbits(AXP221_OUTPUT_CTRL1,
64 AXP221_OUTPUT_CTRL1_DCDC2_EN);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020065}
66
Hans de Goede6944aff2015-10-03 15:18:33 +020067int axp_set_dcdc3(unsigned int mvolt)
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020068{
Hans de Goede50e0d5e2014-12-13 14:02:38 +010069 int ret;
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020070 u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1860, 20);
71
Hans de Goede50e0d5e2014-12-13 14:02:38 +010072 if (mvolt == 0)
Hans de Goede1d624a42015-04-25 14:07:37 +020073 return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1,
74 AXP221_OUTPUT_CTRL1_DCDC3_EN);
Hans de Goede50e0d5e2014-12-13 14:02:38 +010075
76 ret = pmic_bus_write(AXP221_DCDC3_CTRL, cfg);
77 if (ret)
78 return ret;
79
Hans de Goede1d624a42015-04-25 14:07:37 +020080 return pmic_bus_setbits(AXP221_OUTPUT_CTRL1,
81 AXP221_OUTPUT_CTRL1_DCDC3_EN);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020082}
83
Hans de Goede6944aff2015-10-03 15:18:33 +020084int axp_set_dcdc4(unsigned int mvolt)
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020085{
Hans de Goede50e0d5e2014-12-13 14:02:38 +010086 int ret;
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020087 u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20);
88
Hans de Goede50e0d5e2014-12-13 14:02:38 +010089 if (mvolt == 0)
Hans de Goede1d624a42015-04-25 14:07:37 +020090 return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1,
91 AXP221_OUTPUT_CTRL1_DCDC4_EN);
Hans de Goede50e0d5e2014-12-13 14:02:38 +010092
93 ret = pmic_bus_write(AXP221_DCDC4_CTRL, cfg);
94 if (ret)
95 return ret;
96
Hans de Goede1d624a42015-04-25 14:07:37 +020097 return pmic_bus_setbits(AXP221_OUTPUT_CTRL1,
98 AXP221_OUTPUT_CTRL1_DCDC4_EN);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020099}
100
Hans de Goede6944aff2015-10-03 15:18:33 +0200101int axp_set_dcdc5(unsigned int mvolt)
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200102{
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100103 int ret;
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200104 u8 cfg = axp221_mvolt_to_cfg(mvolt, 1000, 2550, 50);
105
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100106 if (mvolt == 0)
Hans de Goede1d624a42015-04-25 14:07:37 +0200107 return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1,
108 AXP221_OUTPUT_CTRL1_DCDC5_EN);
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100109
110 ret = pmic_bus_write(AXP221_DCDC5_CTRL, cfg);
111 if (ret)
112 return ret;
113
Hans de Goede1d624a42015-04-25 14:07:37 +0200114 return pmic_bus_setbits(AXP221_OUTPUT_CTRL1,
115 AXP221_OUTPUT_CTRL1_DCDC5_EN);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200116}
117
Hans de Goede6944aff2015-10-03 15:18:33 +0200118int axp_set_dldo1(unsigned int mvolt)
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200119{
120 int ret;
121 u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
122
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100123 if (mvolt == 0)
Hans de Goede1d624a42015-04-25 14:07:37 +0200124 return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2,
125 AXP221_OUTPUT_CTRL2_DLDO1_EN);
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100126
Hans de Goedebdcdf842014-11-29 23:54:25 +0100127 ret = pmic_bus_write(AXP221_DLDO1_CTRL, cfg);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200128 if (ret)
129 return ret;
130
Hans de Goede1d624a42015-04-25 14:07:37 +0200131 return pmic_bus_setbits(AXP221_OUTPUT_CTRL2,
132 AXP221_OUTPUT_CTRL2_DLDO1_EN);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200133}
134
Hans de Goede6944aff2015-10-03 15:18:33 +0200135int axp_set_dldo2(unsigned int mvolt)
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200136{
137 int ret;
138 u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
139
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100140 if (mvolt == 0)
Hans de Goede1d624a42015-04-25 14:07:37 +0200141 return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2,
142 AXP221_OUTPUT_CTRL2_DLDO2_EN);
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100143
Hans de Goedebdcdf842014-11-29 23:54:25 +0100144 ret = pmic_bus_write(AXP221_DLDO2_CTRL, cfg);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200145 if (ret)
146 return ret;
147
Hans de Goede1d624a42015-04-25 14:07:37 +0200148 return pmic_bus_setbits(AXP221_OUTPUT_CTRL2,
149 AXP221_OUTPUT_CTRL2_DLDO2_EN);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200150}
151
Hans de Goede6944aff2015-10-03 15:18:33 +0200152int axp_set_dldo3(unsigned int mvolt)
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200153{
154 int ret;
155 u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
156
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100157 if (mvolt == 0)
Hans de Goede1d624a42015-04-25 14:07:37 +0200158 return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2,
159 AXP221_OUTPUT_CTRL2_DLDO3_EN);
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100160
Hans de Goedebdcdf842014-11-29 23:54:25 +0100161 ret = pmic_bus_write(AXP221_DLDO3_CTRL, cfg);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200162 if (ret)
163 return ret;
164
Hans de Goede1d624a42015-04-25 14:07:37 +0200165 return pmic_bus_setbits(AXP221_OUTPUT_CTRL2,
166 AXP221_OUTPUT_CTRL2_DLDO3_EN);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200167}
168
Hans de Goede6944aff2015-10-03 15:18:33 +0200169int axp_set_dldo4(unsigned int mvolt)
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200170{
171 int ret;
172 u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
173
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100174 if (mvolt == 0)
Hans de Goede1d624a42015-04-25 14:07:37 +0200175 return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2,
176 AXP221_OUTPUT_CTRL2_DLDO4_EN);
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100177
Hans de Goedebdcdf842014-11-29 23:54:25 +0100178 ret = pmic_bus_write(AXP221_DLDO4_CTRL, cfg);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200179 if (ret)
180 return ret;
181
Hans de Goede1d624a42015-04-25 14:07:37 +0200182 return pmic_bus_setbits(AXP221_OUTPUT_CTRL2,
183 AXP221_OUTPUT_CTRL2_DLDO4_EN);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200184}
185
Hans de Goede6944aff2015-10-03 15:18:33 +0200186int axp_set_aldo1(unsigned int mvolt)
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200187{
188 int ret;
189 u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
190
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100191 if (mvolt == 0)
Hans de Goede1d624a42015-04-25 14:07:37 +0200192 return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1,
193 AXP221_OUTPUT_CTRL1_ALDO1_EN);
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100194
Hans de Goedebdcdf842014-11-29 23:54:25 +0100195 ret = pmic_bus_write(AXP221_ALDO1_CTRL, cfg);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200196 if (ret)
197 return ret;
198
Hans de Goede1d624a42015-04-25 14:07:37 +0200199 return pmic_bus_setbits(AXP221_OUTPUT_CTRL1,
200 AXP221_OUTPUT_CTRL1_ALDO1_EN);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200201}
202
Hans de Goede6944aff2015-10-03 15:18:33 +0200203int axp_set_aldo2(unsigned int mvolt)
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200204{
205 int ret;
206 u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
207
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100208 if (mvolt == 0)
Hans de Goede1d624a42015-04-25 14:07:37 +0200209 return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1,
210 AXP221_OUTPUT_CTRL1_ALDO2_EN);
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100211
Hans de Goedebdcdf842014-11-29 23:54:25 +0100212 ret = pmic_bus_write(AXP221_ALDO2_CTRL, cfg);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200213 if (ret)
214 return ret;
215
Hans de Goede1d624a42015-04-25 14:07:37 +0200216 return pmic_bus_setbits(AXP221_OUTPUT_CTRL1,
217 AXP221_OUTPUT_CTRL1_ALDO2_EN);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200218}
219
Hans de Goede6944aff2015-10-03 15:18:33 +0200220int axp_set_aldo3(unsigned int mvolt)
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200221{
222 int ret;
223 u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
224
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100225 if (mvolt == 0)
Hans de Goede1d624a42015-04-25 14:07:37 +0200226 return pmic_bus_clrbits(AXP221_OUTPUT_CTRL3,
227 AXP221_OUTPUT_CTRL3_ALDO3_EN);
Hans de Goede50e0d5e2014-12-13 14:02:38 +0100228
Hans de Goedebdcdf842014-11-29 23:54:25 +0100229 ret = pmic_bus_write(AXP221_ALDO3_CTRL, cfg);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200230 if (ret)
231 return ret;
232
Hans de Goede1d624a42015-04-25 14:07:37 +0200233 return pmic_bus_setbits(AXP221_OUTPUT_CTRL3,
234 AXP221_OUTPUT_CTRL3_ALDO3_EN);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200235}
236
Hans de Goede6944aff2015-10-03 15:18:33 +0200237int axp_set_eldo(int eldo_num, unsigned int mvolt)
Siarhei Siamashka6906df12015-01-19 05:23:30 +0200238{
239 int ret;
240 u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
241 u8 addr, bits;
242
243 switch (eldo_num) {
244 case 3:
245 addr = AXP221_ELDO3_CTRL;
246 bits = AXP221_OUTPUT_CTRL2_ELDO3_EN;
247 break;
248 case 2:
249 addr = AXP221_ELDO2_CTRL;
250 bits = AXP221_OUTPUT_CTRL2_ELDO2_EN;
251 break;
252 case 1:
253 addr = AXP221_ELDO1_CTRL;
254 bits = AXP221_OUTPUT_CTRL2_ELDO1_EN;
255 break;
256 default:
257 return -EINVAL;
258 }
259
260 if (mvolt == 0)
Hans de Goede1d624a42015-04-25 14:07:37 +0200261 return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2, bits);
Siarhei Siamashka6906df12015-01-19 05:23:30 +0200262
263 ret = pmic_bus_write(addr, cfg);
264 if (ret)
265 return ret;
266
Hans de Goede1d624a42015-04-25 14:07:37 +0200267 return pmic_bus_setbits(AXP221_OUTPUT_CTRL2, bits);
Siarhei Siamashka6906df12015-01-19 05:23:30 +0200268}
269
Hans de Goede6944aff2015-10-03 15:18:33 +0200270int axp_init(void)
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200271{
Hans de Goede3c781192015-01-11 19:43:56 +0100272 /* This cannot be 0 because it is used in SPL before BSS is ready */
273 static int needs_init = 1;
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200274 u8 axp_chip_id;
275 int ret;
276
Hans de Goede3c781192015-01-11 19:43:56 +0100277 if (!needs_init)
278 return 0;
279
Hans de Goedebdcdf842014-11-29 23:54:25 +0100280 ret = pmic_bus_init();
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200281 if (ret)
282 return ret;
283
Hans de Goedebdcdf842014-11-29 23:54:25 +0100284 ret = pmic_bus_read(AXP221_CHIP_ID, &axp_chip_id);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200285 if (ret)
286 return ret;
287
288 if (!(axp_chip_id == 0x6 || axp_chip_id == 0x7 || axp_chip_id == 0x17))
289 return -ENODEV;
290
Hans de Goede3c781192015-01-11 19:43:56 +0100291 needs_init = 0;
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200292 return 0;
293}
Hans de Goedef3fba562014-11-25 16:37:52 +0100294
Hans de Goede6944aff2015-10-03 15:18:33 +0200295int axp_get_sid(unsigned int *sid)
Hans de Goedef3fba562014-11-25 16:37:52 +0100296{
297 u8 *dest = (u8 *)sid;
298 int i, ret;
299
Hans de Goede6944aff2015-10-03 15:18:33 +0200300 ret = pmic_bus_init();
Hans de Goedef3fba562014-11-25 16:37:52 +0100301 if (ret)
302 return ret;
303
Hans de Goedebdcdf842014-11-29 23:54:25 +0100304 ret = pmic_bus_write(AXP221_PAGE, 1);
Hans de Goedef3fba562014-11-25 16:37:52 +0100305 if (ret)
306 return ret;
307
308 for (i = 0; i < 16; i++) {
Hans de Goedebdcdf842014-11-29 23:54:25 +0100309 ret = pmic_bus_read(AXP221_SID + i, &dest[i]);
Hans de Goedef3fba562014-11-25 16:37:52 +0100310 if (ret)
311 return ret;
312 }
313
Hans de Goedebdcdf842014-11-29 23:54:25 +0100314 pmic_bus_write(AXP221_PAGE, 0);
Hans de Goedef3fba562014-11-25 16:37:52 +0100315
316 for (i = 0; i < 4; i++)
317 sid[i] = be32_to_cpu(sid[i]);
318
319 return 0;
320}