blob: 70a736cfdb8abd63bcfe96f9cae7ddf4ed5c31aa [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glassd3b7ff12015-03-05 12:25:34 -07002/*
3 * Copyright (C) 2015 Google, Inc
Simon Glassd3b7ff12015-03-05 12:25:34 -07004 */
5
6#include <common.h>
7#include <dm.h>
8#include <asm/io.h>
Bin Meng3839b4e2018-08-03 01:14:42 -07009#include <asm/test.h>
Simon Glassd3b7ff12015-03-05 12:25:34 -070010#include <dm/test.h>
Simon Glass0e1fad42020-07-19 10:15:37 -060011#include <test/test.h>
Joe Hershbergere721b882015-05-20 14:27:27 -050012#include <test/ut.h>
Simon Glassd3b7ff12015-03-05 12:25:34 -070013
14/* Test that sandbox PCI works correctly */
Joe Hershbergere721b882015-05-20 14:27:27 -050015static int dm_test_pci_base(struct unit_test_state *uts)
Simon Glassd3b7ff12015-03-05 12:25:34 -070016{
17 struct udevice *bus;
18
19 ut_assertok(uclass_get_device(UCLASS_PCI, 0, &bus));
20
21 return 0;
22}
Simon Glasse180c2b2020-07-28 19:41:12 -060023DM_TEST(dm_test_pci_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
Simon Glassd3b7ff12015-03-05 12:25:34 -070024
Bin Meng2db7f2b2018-08-03 01:14:39 -070025/* Test that sandbox PCI bus numbering and device works correctly */
26static int dm_test_pci_busdev(struct unit_test_state *uts)
Simon Glass2bb02e42015-05-10 21:08:06 -060027{
28 struct udevice *bus;
Bin Meng3839b4e2018-08-03 01:14:42 -070029 struct udevice *swap;
30 u16 vendor, device;
Simon Glass2bb02e42015-05-10 21:08:06 -060031
Bin Mengdee4d752018-08-03 01:14:41 -070032 /* Test bus#0 and its devices */
Simon Glass2bb02e42015-05-10 21:08:06 -060033 ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 0, &bus));
34
Bin Meng2db7f2b2018-08-03 01:14:39 -070035 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x00, 0), &swap));
Bin Meng3839b4e2018-08-03 01:14:42 -070036 vendor = 0;
37 ut_assertok(dm_pci_read_config16(swap, PCI_VENDOR_ID, &vendor));
38 ut_asserteq(SANDBOX_PCI_VENDOR_ID, vendor);
Bin Meng2db7f2b2018-08-03 01:14:39 -070039 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap));
Bin Meng3839b4e2018-08-03 01:14:42 -070040 device = 0;
41 ut_assertok(dm_pci_read_config16(swap, PCI_DEVICE_ID, &device));
Simon Glass34145812019-09-25 08:56:01 -060042 ut_asserteq(SANDBOX_PCI_SWAP_CASE_EMUL_ID, device);
Bin Meng2db7f2b2018-08-03 01:14:39 -070043
Bin Mengdee4d752018-08-03 01:14:41 -070044 /* Test bus#1 and its devices */
45 ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 1, &bus));
46
Bin Mengdee4d752018-08-03 01:14:41 -070047 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &swap));
Bin Meng3839b4e2018-08-03 01:14:42 -070048 vendor = 0;
49 ut_assertok(dm_pci_read_config16(swap, PCI_VENDOR_ID, &vendor));
50 ut_asserteq(SANDBOX_PCI_VENDOR_ID, vendor);
Bin Mengdee4d752018-08-03 01:14:41 -070051 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x0c, 0), &swap));
Bin Meng3839b4e2018-08-03 01:14:42 -070052 device = 0;
53 ut_assertok(dm_pci_read_config16(swap, PCI_DEVICE_ID, &device));
Simon Glass34145812019-09-25 08:56:01 -060054 ut_asserteq(SANDBOX_PCI_SWAP_CASE_EMUL_ID, device);
Bin Mengdee4d752018-08-03 01:14:41 -070055
Simon Glass2bb02e42015-05-10 21:08:06 -060056 return 0;
57}
Simon Glasse180c2b2020-07-28 19:41:12 -060058DM_TEST(dm_test_pci_busdev, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
Simon Glass2bb02e42015-05-10 21:08:06 -060059
Simon Glassd3b7ff12015-03-05 12:25:34 -070060/* Test that we can use the swapcase device correctly */
Joe Hershbergere721b882015-05-20 14:27:27 -050061static int dm_test_pci_swapcase(struct unit_test_state *uts)
Simon Glassd3b7ff12015-03-05 12:25:34 -070062{
Bin Mengdd4808f2018-08-03 01:14:38 -070063 struct udevice *swap;
Simon Glassd3b7ff12015-03-05 12:25:34 -070064 ulong io_addr, mem_addr;
65 char *ptr;
66
Bin Meng2db7f2b2018-08-03 01:14:39 -070067 /* Check that asking for the device 0 automatically fires up PCI */
68 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x00, 0), &swap));
69
70 /* First test I/O */
71 io_addr = dm_pci_read_bar32(swap, 0);
72 outb(2, io_addr);
73 ut_asserteq(2, inb(io_addr));
74
75 /*
76 * Now test memory mapping - note we must unmap and remap to cause
77 * the swapcase emulation to see our data and response.
78 */
79 mem_addr = dm_pci_read_bar32(swap, 1);
80 ptr = map_sysmem(mem_addr, 20);
81 strcpy(ptr, "This is a TesT");
82 unmap_sysmem(ptr);
83
84 ptr = map_sysmem(mem_addr, 20);
85 ut_asserteq_str("tHIS IS A tESt", ptr);
86 unmap_sysmem(ptr);
87
88 /* Check that asking for the device 1 automatically fires up PCI */
Simon Glassc0322412015-11-29 13:18:02 -070089 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap));
Simon Glassd3b7ff12015-03-05 12:25:34 -070090
91 /* First test I/O */
Simon Glassc0322412015-11-29 13:18:02 -070092 io_addr = dm_pci_read_bar32(swap, 0);
Simon Glassd3b7ff12015-03-05 12:25:34 -070093 outb(2, io_addr);
94 ut_asserteq(2, inb(io_addr));
95
96 /*
97 * Now test memory mapping - note we must unmap and remap to cause
98 * the swapcase emulation to see our data and response.
99 */
Simon Glassc0322412015-11-29 13:18:02 -0700100 mem_addr = dm_pci_read_bar32(swap, 1);
Simon Glassd3b7ff12015-03-05 12:25:34 -0700101 ptr = map_sysmem(mem_addr, 20);
102 strcpy(ptr, "This is a TesT");
103 unmap_sysmem(ptr);
104
105 ptr = map_sysmem(mem_addr, 20);
106 ut_asserteq_str("tHIS IS A tESt", ptr);
107 unmap_sysmem(ptr);
108
109 return 0;
110}
Simon Glasse180c2b2020-07-28 19:41:12 -0600111DM_TEST(dm_test_pci_swapcase, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
Bin Meng82b31042018-08-03 01:14:48 -0700112
113/* Test that we can dynamically bind the device driver correctly */
114static int dm_test_pci_drvdata(struct unit_test_state *uts)
115{
116 struct udevice *bus, *swap;
117
118 /* Check that asking for the device automatically fires up PCI */
119 ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 1, &bus));
120
121 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &swap));
122 ut_asserteq(SWAP_CASE_DRV_DATA, swap->driver_data);
Simon Glass7d14ee42020-12-19 10:40:13 -0700123 ut_assertok(dev_has_ofnode(swap));
Bin Meng82b31042018-08-03 01:14:48 -0700124 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x0c, 0), &swap));
125 ut_asserteq(SWAP_CASE_DRV_DATA, swap->driver_data);
Simon Glass7d14ee42020-12-19 10:40:13 -0700126 ut_assertok(dev_has_ofnode(swap));
Marek Vasut25db3402018-10-10 21:27:09 +0200127 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x10, 0), &swap));
128 ut_asserteq(SWAP_CASE_DRV_DATA, swap->driver_data);
Simon Glass7d14ee42020-12-19 10:40:13 -0700129 ut_assertok(!dev_has_ofnode(swap));
Bin Meng82b31042018-08-03 01:14:48 -0700130
131 return 0;
132}
Simon Glasse180c2b2020-07-28 19:41:12 -0600133DM_TEST(dm_test_pci_drvdata, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
Bin Meng3ed214a2018-08-03 01:14:50 -0700134
135/* Test that devices on PCI bus#2 can be accessed correctly */
136static int dm_test_pci_mixed(struct unit_test_state *uts)
137{
138 /* PCI bus#2 has both statically and dynamic declared devices */
139 struct udevice *bus, *swap;
140 u16 vendor, device;
141 ulong io_addr, mem_addr;
142 char *ptr;
143
144 ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 2, &bus));
145
146 /* Test the dynamic device */
147 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(2, 0x08, 0), &swap));
148 vendor = 0;
149 ut_assertok(dm_pci_read_config16(swap, PCI_VENDOR_ID, &vendor));
150 ut_asserteq(SANDBOX_PCI_VENDOR_ID, vendor);
151
152 /* First test I/O */
153 io_addr = dm_pci_read_bar32(swap, 0);
154 outb(2, io_addr);
155 ut_asserteq(2, inb(io_addr));
156
157 /*
158 * Now test memory mapping - note we must unmap and remap to cause
159 * the swapcase emulation to see our data and response.
160 */
161 mem_addr = dm_pci_read_bar32(swap, 1);
162 ptr = map_sysmem(mem_addr, 30);
163 strcpy(ptr, "This is a TesT oN dYNAMIc");
164 unmap_sysmem(ptr);
165
166 ptr = map_sysmem(mem_addr, 30);
167 ut_asserteq_str("tHIS IS A tESt On DynamiC", ptr);
168 unmap_sysmem(ptr);
169
170 /* Test the static device */
171 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(2, 0x1f, 0), &swap));
172 device = 0;
173 ut_assertok(dm_pci_read_config16(swap, PCI_DEVICE_ID, &device));
Simon Glass34145812019-09-25 08:56:01 -0600174 ut_asserteq(SANDBOX_PCI_SWAP_CASE_EMUL_ID, device);
Bin Meng3ed214a2018-08-03 01:14:50 -0700175
176 /* First test I/O */
177 io_addr = dm_pci_read_bar32(swap, 0);
178 outb(2, io_addr);
179 ut_asserteq(2, inb(io_addr));
180
181 /*
182 * Now test memory mapping - note we must unmap and remap to cause
183 * the swapcase emulation to see our data and response.
184 */
185 mem_addr = dm_pci_read_bar32(swap, 1);
186 ptr = map_sysmem(mem_addr, 30);
187 strcpy(ptr, "This is a TesT oN sTATIc");
188 unmap_sysmem(ptr);
189
190 ptr = map_sysmem(mem_addr, 30);
191 ut_asserteq_str("tHIS IS A tESt On StatiC", ptr);
192 unmap_sysmem(ptr);
193
194 return 0;
195}
Simon Glasse180c2b2020-07-28 19:41:12 -0600196DM_TEST(dm_test_pci_mixed, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
Bin Meng95e11062018-08-03 01:14:53 -0700197
198/* Test looking up PCI capability and extended capability */
199static int dm_test_pci_cap(struct unit_test_state *uts)
200{
201 struct udevice *bus, *swap;
202 int cap;
203
204 ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 0, &bus));
205 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap));
206
207 /* look up PCI_CAP_ID_EXP */
208 cap = dm_pci_find_capability(swap, PCI_CAP_ID_EXP);
209 ut_asserteq(PCI_CAP_ID_EXP_OFFSET, cap);
210
211 /* look up PCI_CAP_ID_PCIX */
212 cap = dm_pci_find_capability(swap, PCI_CAP_ID_PCIX);
213 ut_asserteq(0, cap);
214
Bin Meng7a206142018-10-15 02:21:22 -0700215 /* look up PCI_CAP_ID_MSIX starting from PCI_CAP_ID_PM_OFFSET */
216 cap = dm_pci_find_next_capability(swap, PCI_CAP_ID_PM_OFFSET,
217 PCI_CAP_ID_MSIX);
218 ut_asserteq(PCI_CAP_ID_MSIX_OFFSET, cap);
219
220 /* look up PCI_CAP_ID_VNDR starting from PCI_CAP_ID_EXP_OFFSET */
221 cap = dm_pci_find_next_capability(swap, PCI_CAP_ID_EXP_OFFSET,
222 PCI_CAP_ID_VNDR);
223 ut_asserteq(0, cap);
224
Bin Meng95e11062018-08-03 01:14:53 -0700225 ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 1, &bus));
226 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &swap));
227
228 /* look up PCI_EXT_CAP_ID_DSN */
229 cap = dm_pci_find_ext_capability(swap, PCI_EXT_CAP_ID_DSN);
230 ut_asserteq(PCI_EXT_CAP_ID_DSN_OFFSET, cap);
231
232 /* look up PCI_EXT_CAP_ID_SRIOV */
233 cap = dm_pci_find_ext_capability(swap, PCI_EXT_CAP_ID_SRIOV);
234 ut_asserteq(0, cap);
235
Bin Meng7a206142018-10-15 02:21:22 -0700236 /* look up PCI_EXT_CAP_ID_DSN starting from PCI_EXT_CAP_ID_ERR_OFFSET */
237 cap = dm_pci_find_next_ext_capability(swap, PCI_EXT_CAP_ID_ERR_OFFSET,
238 PCI_EXT_CAP_ID_DSN);
239 ut_asserteq(PCI_EXT_CAP_ID_DSN_OFFSET, cap);
240
241 /* look up PCI_EXT_CAP_ID_RCRB starting from PCI_EXT_CAP_ID_VC_OFFSET */
242 cap = dm_pci_find_next_ext_capability(swap, PCI_EXT_CAP_ID_VC_OFFSET,
243 PCI_EXT_CAP_ID_RCRB);
244 ut_asserteq(0, cap);
245
Bin Meng95e11062018-08-03 01:14:53 -0700246 return 0;
247}
Simon Glasse180c2b2020-07-28 19:41:12 -0600248DM_TEST(dm_test_pci_cap, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300249
250/* Test looking up BARs in EA capability structure */
251static int dm_test_pci_ea(struct unit_test_state *uts)
252{
253 struct udevice *bus, *swap;
254 void *bar;
255 int cap;
256
257 /*
258 * use emulated device mapping function, we're not using real physical
259 * addresses in this test
260 */
261 sandbox_set_enable_pci_map(true);
262
263 ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 0, &bus));
264 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x01, 0), &swap));
265
266 /* look up PCI_CAP_ID_EA */
267 cap = dm_pci_find_capability(swap, PCI_CAP_ID_EA);
268 ut_asserteq(PCI_CAP_ID_EA_OFFSET, cap);
269
270 /* test swap case in BAR 1 */
Andrew Scull2635e3b2022-04-21 16:11:13 +0000271 bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, 0);
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300272 ut_assertnonnull(bar);
273 *(int *)bar = 2; /* swap upper/lower */
274
Andrew Scull2635e3b2022-04-21 16:11:13 +0000275 bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_1, 0, 0, PCI_REGION_TYPE, 0);
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300276 ut_assertnonnull(bar);
277 strcpy(bar, "ea TEST");
278 unmap_sysmem(bar);
Andrew Scull2635e3b2022-04-21 16:11:13 +0000279 bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_1, 0, 0, PCI_REGION_TYPE, 0);
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300280 ut_assertnonnull(bar);
281 ut_asserteq_str("EA test", bar);
282
283 /* test magic values in BARs2, 4; BAR 3 is n/a */
Andrew Scull2635e3b2022-04-21 16:11:13 +0000284 bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_2, 0, 0, PCI_REGION_TYPE, 0);
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300285 ut_assertnonnull(bar);
286 ut_asserteq(PCI_EA_BAR2_MAGIC, *(u32 *)bar);
287
Andrew Scull2635e3b2022-04-21 16:11:13 +0000288 bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_3, 0, 0, PCI_REGION_TYPE, 0);
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300289 ut_assertnull(bar);
290
Andrew Scull2635e3b2022-04-21 16:11:13 +0000291 bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_4, 0, 0, PCI_REGION_TYPE, 0);
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300292 ut_assertnonnull(bar);
293 ut_asserteq(PCI_EA_BAR4_MAGIC, *(u32 *)bar);
294
295 return 0;
296}
Simon Glasse180c2b2020-07-28 19:41:12 -0600297DM_TEST(dm_test_pci_ea, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
Simon Glass33c215a2019-09-15 12:08:58 -0600298
299/* Test the dev_read_addr_pci() function */
300static int dm_test_pci_addr_flat(struct unit_test_state *uts)
301{
302 struct udevice *swap1f, *swap1;
303 ulong io_addr, mem_addr;
304
305 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap1f));
306 io_addr = dm_pci_read_bar32(swap1f, 0);
307 ut_asserteq(io_addr, dev_read_addr_pci(swap1f));
308
309 /*
310 * This device has both I/O and MEM spaces but the MEM space appears
311 * first
312 */
313 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1, 0), &swap1));
314 mem_addr = dm_pci_read_bar32(swap1, 1);
315 ut_asserteq(mem_addr, dev_read_addr_pci(swap1));
316
317 return 0;
318}
Simon Glasse180c2b2020-07-28 19:41:12 -0600319DM_TEST(dm_test_pci_addr_flat, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT |
320 UT_TESTF_FLAT_TREE);
Simon Glass33c215a2019-09-15 12:08:58 -0600321
322/*
323 * Test the dev_read_addr_pci() function with livetree. That function is
324 * not currently fully implemented, in that it fails to return the BAR address.
325 * Once that is implemented this test can be removed and dm_test_pci_addr_flat()
Simon Glasse180c2b2020-07-28 19:41:12 -0600326 * can be used for both flattree and livetree by removing the UT_TESTF_FLAT_TREE
Simon Glass33c215a2019-09-15 12:08:58 -0600327 * flag above.
328 */
329static int dm_test_pci_addr_live(struct unit_test_state *uts)
330{
331 struct udevice *swap1f, *swap1;
332
333 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap1f));
Patrice Chotard9876ae72022-01-04 08:42:48 +0100334 ut_asserteq_64(FDT_ADDR_T_NONE, dev_read_addr_pci(swap1f));
Simon Glass33c215a2019-09-15 12:08:58 -0600335
336 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1, 0), &swap1));
Patrice Chotard9876ae72022-01-04 08:42:48 +0100337 ut_asserteq_64(FDT_ADDR_T_NONE, dev_read_addr_pci(swap1));
Simon Glass33c215a2019-09-15 12:08:58 -0600338
339 return 0;
340}
Simon Glasse180c2b2020-07-28 19:41:12 -0600341DM_TEST(dm_test_pci_addr_live, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT |
342 UT_TESTF_LIVE_TREE);
Simon Glass20349782020-07-07 13:12:10 -0600343
344/* Test device_is_on_pci_bus() */
345static int dm_test_pci_on_bus(struct unit_test_state *uts)
346{
347 struct udevice *dev;
348
349 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &dev));
350 ut_asserteq(true, device_is_on_pci_bus(dev));
351 ut_asserteq(false, device_is_on_pci_bus(dev_get_parent(dev)));
352 ut_asserteq(true, device_is_on_pci_bus(dev));
353
354 return 0;
355}
Simon Glasse180c2b2020-07-28 19:41:12 -0600356DM_TEST(dm_test_pci_on_bus, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
Suneel Garapati4cf56ec2019-10-19 17:10:20 -0700357
358/*
359 * Test support for multiple memory regions enabled via
360 * CONFIG_PCI_REGION_MULTI_ENTRY. When this feature is not enabled,
361 * only the last region of one type is stored. In this test-case,
362 * we have 2 memory regions, the first at 0x3000.0000 and the 2nd
363 * at 0x3100.0000. A correct test results now in BAR1 located at
364 * 0x3000.0000.
365 */
366static int dm_test_pci_region_multi(struct unit_test_state *uts)
367{
368 struct udevice *dev;
369 ulong mem_addr;
370
371 /* Test memory BAR1 on bus#1 */
372 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &dev));
373 mem_addr = dm_pci_read_bar32(dev, 1);
374 ut_asserteq(mem_addr, 0x30000000);
375
376 return 0;
377}
378DM_TEST(dm_test_pci_region_multi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000379
380/*
381 * Test the translation of PCI bus addresses to physical addresses using the
382 * ranges from bus#1.
383 */
384static int dm_test_pci_bus_to_phys(struct unit_test_state *uts)
385{
Andrew Scull7739d932022-04-21 16:11:11 +0000386 unsigned long mask = PCI_REGION_TYPE;
387 unsigned long flags = PCI_REGION_MEM;
Andrew Scull55e6adb2022-04-21 16:11:09 +0000388 struct udevice *dev;
389 phys_addr_t phys_addr;
390
391 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &dev));
392
393 /* Before any of the ranges. */
Andrew Scull7739d932022-04-21 16:11:11 +0000394 phys_addr = dm_pci_bus_to_phys(dev, 0x20000000, 0x400, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000395 ut_asserteq(0, phys_addr);
396
397 /* Identity range: whole, start, mid, end */
Andrew Scull7739d932022-04-21 16:11:11 +0000398 phys_addr = dm_pci_bus_to_phys(dev, 0x2ffff000, 0x2000, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000399 ut_asserteq(0, phys_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000400 phys_addr = dm_pci_bus_to_phys(dev, 0x30000000, 0x2000, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000401 ut_asserteq(0x30000000, phys_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000402 phys_addr = dm_pci_bus_to_phys(dev, 0x30000000, 0x1000, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000403 ut_asserteq(0x30000000, phys_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000404 phys_addr = dm_pci_bus_to_phys(dev, 0x30000abc, 0x12, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000405 ut_asserteq(0x30000abc, phys_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000406 phys_addr = dm_pci_bus_to_phys(dev, 0x30000800, 0x1800, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000407 ut_asserteq(0x30000800, phys_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000408 phys_addr = dm_pci_bus_to_phys(dev, 0x30008000, 0x1801, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000409 ut_asserteq(0, phys_addr);
410
411 /* Translated range: whole, start, mid, end */
Andrew Scull7739d932022-04-21 16:11:11 +0000412 phys_addr = dm_pci_bus_to_phys(dev, 0x30fff000, 0x2000, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000413 ut_asserteq(0, phys_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000414 phys_addr = dm_pci_bus_to_phys(dev, 0x31000000, 0x2000, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000415 ut_asserteq(0x3e000000, phys_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000416 phys_addr = dm_pci_bus_to_phys(dev, 0x31000000, 0x1000, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000417 ut_asserteq(0x3e000000, phys_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000418 phys_addr = dm_pci_bus_to_phys(dev, 0x31000abc, 0x12, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000419 ut_asserteq(0x3e000abc, phys_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000420 phys_addr = dm_pci_bus_to_phys(dev, 0x31000800, 0x1800, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000421 ut_asserteq(0x3e000800, phys_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000422 phys_addr = dm_pci_bus_to_phys(dev, 0x31008000, 0x1801, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000423 ut_asserteq(0, phys_addr);
424
425 /* Beyond all of the ranges. */
Andrew Scull7739d932022-04-21 16:11:11 +0000426 phys_addr = dm_pci_bus_to_phys(dev, 0x32000000, 0x400, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000427 ut_asserteq(0, phys_addr);
428
429 return 0;
430}
431DM_TEST(dm_test_pci_bus_to_phys, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
432
433/*
434 * Test the translation of physical addresses to PCI bus addresses using the
435 * ranges from bus#1.
436 */
437static int dm_test_pci_phys_to_bus(struct unit_test_state *uts)
438{
Andrew Scull7739d932022-04-21 16:11:11 +0000439 unsigned long mask = PCI_REGION_TYPE;
440 unsigned long flags = PCI_REGION_MEM;
Andrew Scull55e6adb2022-04-21 16:11:09 +0000441 struct udevice *dev;
442 pci_addr_t pci_addr;
443
444 ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &dev));
445
446 /* Before any of the ranges. */
Andrew Scull7739d932022-04-21 16:11:11 +0000447 pci_addr = dm_pci_phys_to_bus(dev, 0x20000000, 0x400, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000448 ut_asserteq(0, pci_addr);
449
450 /* Identity range: partial overlap, whole, start, mid, end */
Andrew Scull7739d932022-04-21 16:11:11 +0000451 pci_addr = dm_pci_phys_to_bus(dev, 0x2ffff000, 0x2000, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000452 ut_asserteq(0, pci_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000453 pci_addr = dm_pci_phys_to_bus(dev, 0x30000000, 0x2000, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000454 ut_asserteq(0x30000000, pci_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000455 pci_addr = dm_pci_phys_to_bus(dev, 0x30000000, 0x1000, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000456 ut_asserteq(0x30000000, pci_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000457 pci_addr = dm_pci_phys_to_bus(dev, 0x30000abc, 0x12, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000458 ut_asserteq(0x30000abc, pci_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000459 pci_addr = dm_pci_phys_to_bus(dev, 0x30000800, 0x1800, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000460 ut_asserteq(0x30000800, pci_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000461 pci_addr = dm_pci_phys_to_bus(dev, 0x30008000, 0x1801, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000462 ut_asserteq(0, pci_addr);
463
464 /* Translated range: partial overlap, whole, start, mid, end */
Andrew Scull7739d932022-04-21 16:11:11 +0000465 pci_addr = dm_pci_phys_to_bus(dev, 0x3dfff000, 0x2000, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000466 ut_asserteq(0, pci_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000467 pci_addr = dm_pci_phys_to_bus(dev, 0x3e000000, 0x2000, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000468 ut_asserteq(0x31000000, pci_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000469 pci_addr = dm_pci_phys_to_bus(dev, 0x3e000000, 0x1000, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000470 ut_asserteq(0x31000000, pci_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000471 pci_addr = dm_pci_phys_to_bus(dev, 0x3e000abc, 0x12, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000472 ut_asserteq(0x31000abc, pci_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000473 pci_addr = dm_pci_phys_to_bus(dev, 0x3e000800, 0x1800, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000474 ut_asserteq(0x31000800, pci_addr);
Andrew Scull7739d932022-04-21 16:11:11 +0000475 pci_addr = dm_pci_phys_to_bus(dev, 0x3e008000, 0x1801, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000476 ut_asserteq(0, pci_addr);
477
478 /* Beyond all of the ranges. */
Andrew Scull7739d932022-04-21 16:11:11 +0000479 pci_addr = dm_pci_phys_to_bus(dev, 0x3f000000, 0x400, mask, flags);
Andrew Scull55e6adb2022-04-21 16:11:09 +0000480 ut_asserteq(0, pci_addr);
481
482 return 0;
483}
484DM_TEST(dm_test_pci_phys_to_bus, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);