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Tom Rini4549e782018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunay3d2d1152018-03-12 10:46:17 +01002/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
Patrick Delaunay414315b2020-04-22 14:29:18 +02004 */
5
6/*
7 * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
8 * DDR type: DDR3 / DDR3L
9 * DDR width: 32bits
10 * DDR density: 8Gb
11 * System frequency: 533000Khz
12 * Relaxed Timing Mode: false
13 * Address mapping type: RBC
Patrick Delaunay067a4c02019-04-10 14:09:24 +020014 *
Patrick Delaunay414315b2020-04-22 14:29:18 +020015 * Save Date: 2020.02.20, save Time: 18:49:33
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010016 */
Marek Vasuta8c97f42020-04-22 13:18:13 +020017#define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-2x4gb-533mhz
Fabrice GIRARDOT2220c2e2021-01-15 13:55:01 +010018#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000kHz"
Patrick Delaunay414315b2020-04-22 14:29:18 +020019#define DDR_MEM_SPEED 533000
20#define DDR_MEM_SIZE 0x40000000
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010021
22#define DDR_MSTR 0x00040401
23#define DDR_MRCTRL0 0x00000010
24#define DDR_MRCTRL1 0x00000000
25#define DDR_DERATEEN 0x00000000
26#define DDR_DERATEINT 0x00800000
27#define DDR_PWRCTL 0x00000000
28#define DDR_PWRTMG 0x00400010
29#define DDR_HWLPCTL 0x00000000
30#define DDR_RFSHCTL0 0x00210000
31#define DDR_RFSHCTL3 0x00000000
32#define DDR_RFSHTMG 0x0081008B
33#define DDR_CRCPARCTL0 0x00000000
34#define DDR_DRAMTMG0 0x121B2414
35#define DDR_DRAMTMG1 0x000A041C
36#define DDR_DRAMTMG2 0x0608090F
37#define DDR_DRAMTMG3 0x0050400C
38#define DDR_DRAMTMG4 0x08040608
39#define DDR_DRAMTMG5 0x06060403
40#define DDR_DRAMTMG6 0x02020002
41#define DDR_DRAMTMG7 0x00000202
42#define DDR_DRAMTMG8 0x00001005
43#define DDR_DRAMTMG14 0x000000A0
44#define DDR_ZQCTL0 0xC2000040
45#define DDR_DFITMG0 0x02060105
46#define DDR_DFITMG1 0x00000202
47#define DDR_DFILPCFG0 0x07000000
48#define DDR_DFIUPD0 0xC0400003
49#define DDR_DFIUPD1 0x00000000
50#define DDR_DFIUPD2 0x00000000
51#define DDR_DFIPHYMSTR 0x00000000
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010052#define DDR_ODTCFG 0x06000600
53#define DDR_ODTMAP 0x00000001
Patrick Delaunay067a4c02019-04-10 14:09:24 +020054#define DDR_SCHED 0x00000C01
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010055#define DDR_SCHED1 0x00000000
56#define DDR_PERFHPR1 0x01000001
57#define DDR_PERFLPR1 0x08000200
58#define DDR_PERFWR1 0x08000400
59#define DDR_DBG0 0x00000000
60#define DDR_DBG1 0x00000000
61#define DDR_DBGCMD 0x00000000
62#define DDR_POISONCFG 0x00000000
63#define DDR_PCCFG 0x00000010
64#define DDR_PCFGR_0 0x00010000
65#define DDR_PCFGW_0 0x00000000
Patrick Delaunay067a4c02019-04-10 14:09:24 +020066#define DDR_PCFGQOS0_0 0x02100C03
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010067#define DDR_PCFGQOS1_0 0x00800100
Patrick Delaunay067a4c02019-04-10 14:09:24 +020068#define DDR_PCFGWQOS0_0 0x01100C03
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010069#define DDR_PCFGWQOS1_0 0x01000200
70#define DDR_PCFGR_1 0x00010000
71#define DDR_PCFGW_1 0x00000000
Patrick Delaunay067a4c02019-04-10 14:09:24 +020072#define DDR_PCFGQOS0_1 0x02100C03
73#define DDR_PCFGQOS1_1 0x00800040
74#define DDR_PCFGWQOS0_1 0x01100C03
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010075#define DDR_PCFGWQOS1_1 0x01000200
Patrick Delaunay414315b2020-04-22 14:29:18 +020076#define DDR_ADDRMAP1 0x00080808
77#define DDR_ADDRMAP2 0x00000000
78#define DDR_ADDRMAP3 0x00000000
79#define DDR_ADDRMAP4 0x00001F1F
80#define DDR_ADDRMAP5 0x07070707
81#define DDR_ADDRMAP6 0x0F070707
82#define DDR_ADDRMAP9 0x00000000
83#define DDR_ADDRMAP10 0x00000000
84#define DDR_ADDRMAP11 0x00000000
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010085#define DDR_PGCR 0x01442E02
86#define DDR_PTR0 0x0022AA5B
87#define DDR_PTR1 0x04841104
88#define DDR_PTR2 0x042DA068
89#define DDR_ACIOCR 0x10400812
90#define DDR_DXCCR 0x00000C40
Patrick Delaunaybe16c412019-07-30 19:16:13 +020091#define DDR_DSGCR 0xF200011F
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010092#define DDR_DCR 0x0000000B
93#define DDR_DTPR0 0x38D488D0
94#define DDR_DTPR1 0x098B00D8
95#define DDR_DTPR2 0x10023600
96#define DDR_MR0 0x00000840
97#define DDR_MR1 0x00000000
98#define DDR_MR2 0x00000208
99#define DDR_MR3 0x00000000
100#define DDR_ODTCR 0x00010000
Patrick Delaunay067a4c02019-04-10 14:09:24 +0200101#define DDR_ZQ0CR1 0x00000038
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100102#define DDR_DX0GCR 0x0000CE81
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100103#define DDR_DX1GCR 0x0000CE81
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100104#define DDR_DX2GCR 0x0000CE81
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100105#define DDR_DX3GCR 0x0000CE81
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100106
107#include "stm32mp15-ddr.dtsi"