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York Sunee52b182012-10-11 07:13:37 +00001/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
York Sunee52b182012-10-11 07:13:37 +00005 */
6
7/*
8 * Corenet DS style board configuration file
9 */
York Sun1cb19fb2013-06-27 10:48:29 -070010#ifndef __T4QDS_H
11#define __T4QDS_H
Liu Gang69fdf902013-05-07 16:30:50 +080012
York Sun15672c62014-04-30 14:43:49 -070013#define CONFIG_DISPLAY_BOARDINFO
York Sunee52b182012-10-11 07:13:37 +000014#define CONFIG_CMD_REGINFO
15
16/* High Level Configuration Options */
17#define CONFIG_BOOKE
York Sunee52b182012-10-11 07:13:37 +000018#define CONFIG_E500 /* BOOKE e500 family */
19#define CONFIG_E500MC /* BOOKE e500mc family */
20#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
York Sunee52b182012-10-11 07:13:37 +000021#define CONFIG_MP /* support multiple processors */
22
23#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053024#define CONFIG_SYS_TEXT_BASE 0xeff40000
York Sunee52b182012-10-11 07:13:37 +000025#endif
26
27#ifndef CONFIG_RESET_VECTOR_ADDRESS
28#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
29#endif
30
31#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
32#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
33#define CONFIG_FSL_IFC /* Enable IFC Support */
34#define CONFIG_PCI /* Enable PCI/PCIE */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040035#define CONFIG_PCIE1 /* PCIE controller 1 */
36#define CONFIG_PCIE2 /* PCIE controller 2 */
37#define CONFIG_PCIE3 /* PCIE controller 3 */
York Sunee52b182012-10-11 07:13:37 +000038#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
39#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
40
41#define CONFIG_SYS_SRIO
42#define CONFIG_SRIO1 /* SRIO port 1 */
43#define CONFIG_SRIO2 /* SRIO port 2 */
44
45#define CONFIG_FSL_LAW /* Use common FSL init code */
46
47#define CONFIG_ENV_OVERWRITE
48
York Sunee52b182012-10-11 07:13:37 +000049/*
50 * These can be toggled for performance analysis, otherwise use default.
51 */
52#define CONFIG_SYS_CACHE_STASHING
53#define CONFIG_BTB /* toggle branch predition */
York Sunee52b182012-10-11 07:13:37 +000054#ifdef CONFIG_DDR_ECC
55#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
56#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
57#endif
58
59#define CONFIG_ENABLE_36BIT_PHYS
60
York Sunee52b182012-10-11 07:13:37 +000061#define CONFIG_ADDR_MAP
62#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
York Sunee52b182012-10-11 07:13:37 +000063
York Sunee52b182012-10-11 07:13:37 +000064#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
65#define CONFIG_SYS_MEMTEST_END 0x00400000
66#define CONFIG_SYS_ALT_MEMTEST
67#define CONFIG_PANIC_HANG /* do not reset board on panic */
68
69/*
70 * Config the L3 Cache as L3 SRAM
71 */
Shaohui Xieb6036992014-04-22 15:10:44 +080072#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
73#define CONFIG_SYS_L3_SIZE (512 << 10)
74#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
75#ifdef CONFIG_RAMBOOT_PBL
76#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
77#endif
78#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
79#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
80#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
81#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
York Sunee52b182012-10-11 07:13:37 +000082
York Sunee52b182012-10-11 07:13:37 +000083#define CONFIG_SYS_DCSRBAR 0xf0000000
84#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
York Sunee52b182012-10-11 07:13:37 +000085
York Sunee52b182012-10-11 07:13:37 +000086/*
87 * DDR Setup
88 */
89#define CONFIG_VERY_BIG_RAM
90#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
91#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
92
93/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
94#define CONFIG_DIMM_SLOTS_PER_CTLR 2
95#define CONFIG_CHIP_SELECTS_PER_CTRL 4
96#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
97
98#define CONFIG_DDR_SPD
York Sun5614e712013-09-30 09:22:09 -070099#define CONFIG_SYS_FSL_DDR3
York Sunee52b182012-10-11 07:13:37 +0000100
York Sunee52b182012-10-11 07:13:37 +0000101/*
102 * IFC Definitions
103 */
104#define CONFIG_SYS_FLASH_BASE 0xe0000000
York Sunee52b182012-10-11 07:13:37 +0000105#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
York Sunee52b182012-10-11 07:13:37 +0000106
Shaohui Xieb6036992014-04-22 15:10:44 +0800107#ifdef CONFIG_SPL_BUILD
108#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
109#else
110#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
111#endif
York Sunee52b182012-10-11 07:13:37 +0000112
York Sunee52b182012-10-11 07:13:37 +0000113#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
114#define CONFIG_MISC_INIT_R
115
116#define CONFIG_HWCONFIG
117
118/* define to use L1 as initial stack */
119#define CONFIG_L1_INIT_RAM
120#define CONFIG_SYS_INIT_RAM_LOCK
121#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
York Sunee52b182012-10-11 07:13:37 +0000122#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700123#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
York Sunee52b182012-10-11 07:13:37 +0000124/* The assembler doesn't like typecast */
125#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
126 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
127 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
York Sunee52b182012-10-11 07:13:37 +0000128#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
129
130#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
131 GENERATED_GBL_DATA_SIZE)
132#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
133
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530134#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
York Sunee52b182012-10-11 07:13:37 +0000135#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
136
137/* Serial Port - controlled on board with jumper J8
138 * open - index 2
139 * shorted - index 1
140 */
141#define CONFIG_CONS_INDEX 1
York Sunee52b182012-10-11 07:13:37 +0000142#define CONFIG_SYS_NS16550_SERIAL
143#define CONFIG_SYS_NS16550_REG_SIZE 1
144#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
145
146#define CONFIG_SYS_BAUDRATE_TABLE \
147 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
148
149#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
150#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
151#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
152#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
153
York Sunee52b182012-10-11 07:13:37 +0000154/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200155#define CONFIG_SYS_I2C
156#define CONFIG_SYS_I2C_FSL
Heiko Schocher00f792e2012-10-24 13:48:22 +0200157#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
158#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
Heiko Schocher00f792e2012-10-24 13:48:22 +0200159#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
160#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
161
York Sunee52b182012-10-11 07:13:37 +0000162/*
163 * RapidIO
164 */
165#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
York Sunee52b182012-10-11 07:13:37 +0000166#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
York Sunee52b182012-10-11 07:13:37 +0000167#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
168
169#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
York Sunee52b182012-10-11 07:13:37 +0000170#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
York Sunee52b182012-10-11 07:13:37 +0000171#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
172
173/*
York Sunee52b182012-10-11 07:13:37 +0000174 * General PCI
175 * Memory space is mapped 1-1, but I/O space must start from 0.
176 */
177
178/* controller 1, direct to uli, tgtid 3, Base address 20000 */
179#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
York Sunee52b182012-10-11 07:13:37 +0000180#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
181#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
York Sunee52b182012-10-11 07:13:37 +0000182#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
183#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
184#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
York Sunee52b182012-10-11 07:13:37 +0000185#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
York Sunee52b182012-10-11 07:13:37 +0000186#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
187
188/* controller 2, Slot 2, tgtid 2, Base address 201000 */
189#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
York Sunee52b182012-10-11 07:13:37 +0000190#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
191#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
York Sunee52b182012-10-11 07:13:37 +0000192#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
193#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
194#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
York Sunee52b182012-10-11 07:13:37 +0000195#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
York Sunee52b182012-10-11 07:13:37 +0000196#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
197
198/* controller 3, Slot 1, tgtid 1, Base address 202000 */
199#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
York Sunee52b182012-10-11 07:13:37 +0000200#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
201#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
York Sunee52b182012-10-11 07:13:37 +0000202#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
203#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
204#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
York Sunee52b182012-10-11 07:13:37 +0000205#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
York Sunee52b182012-10-11 07:13:37 +0000206#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
207
208/* controller 4, Base address 203000 */
209#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
210#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
211#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
212#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
213#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
214#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
215
York Sunee52b182012-10-11 07:13:37 +0000216#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000217#define CONFIG_PCI_INDIRECT_BRIDGE
York Sunee52b182012-10-11 07:13:37 +0000218#define CONFIG_PCI_PNP /* do pci plug-and-play */
York Sunee52b182012-10-11 07:13:37 +0000219
220#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
221#define CONFIG_DOS_PARTITION
222#endif /* CONFIG_PCI */
223
224/* SATA */
225#ifdef CONFIG_FSL_SATA_V2
226#define CONFIG_LIBATA
227#define CONFIG_FSL_SATA
228
229#define CONFIG_SYS_SATA_MAX_DEVICE 2
230#define CONFIG_SATA1
231#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
232#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
233#define CONFIG_SATA2
234#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
235#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
236
237#define CONFIG_LBA48
238#define CONFIG_CMD_SATA
239#define CONFIG_DOS_PARTITION
York Sunee52b182012-10-11 07:13:37 +0000240#endif
241
242#ifdef CONFIG_FMAN_ENET
243#define CONFIG_MII /* MII PHY management */
244#define CONFIG_ETHPRIME "FM1@DTSEC1"
245#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
246#endif
247
248/*
249 * Environment
250 */
251#define CONFIG_LOADS_ECHO /* echo on for serial download */
252#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
253
254/*
255 * Command line configuration.
256 */
York Sunee52b182012-10-11 07:13:37 +0000257#define CONFIG_CMD_ERRATA
York Sunee52b182012-10-11 07:13:37 +0000258#define CONFIG_CMD_IRQ
York Sunee52b182012-10-11 07:13:37 +0000259
260#ifdef CONFIG_PCI
261#define CONFIG_CMD_PCI
York Sunee52b182012-10-11 07:13:37 +0000262#endif
263
264/*
York Sunee52b182012-10-11 07:13:37 +0000265 * Miscellaneous configurable options
266 */
267#define CONFIG_SYS_LONGHELP /* undef to save memory */
268#define CONFIG_CMDLINE_EDITING /* Command-line editing */
269#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
270#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
York Sunee52b182012-10-11 07:13:37 +0000271#ifdef CONFIG_CMD_KGDB
272#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
273#else
274#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
275#endif
276#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
277#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
278#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
York Sunee52b182012-10-11 07:13:37 +0000279
280/*
281 * For booting Linux, the board info and command line data
282 * have to be in the first 64 MB of memory, since this is
283 * the maximum mapped by the Linux kernel during initialization.
284 */
285#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
286#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
287
288#ifdef CONFIG_CMD_KGDB
289#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
York Sunee52b182012-10-11 07:13:37 +0000290#endif
291
292/*
293 * Environment Configuration
294 */
295#define CONFIG_ROOTPATH "/opt/nfsroot"
296#define CONFIG_BOOTFILE "uImage"
297#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
298
299/* default location for tftp and bootm */
300#define CONFIG_LOADADDR 1000000
301
York Sunee52b182012-10-11 07:13:37 +0000302#define CONFIG_BAUDRATE 115200
303
York Sunee52b182012-10-11 07:13:37 +0000304#define CONFIG_HVBOOT \
305 "setenv bootargs config-addr=0x60000000; " \
306 "bootm 0x01000000 - 0x00f00000"
307
York Sunee52b182012-10-11 07:13:37 +0000308#endif /* __CONFIG_H */