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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ramneek Mehreshdc9cdf82015-05-29 14:47:15 +05302/*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 *
5 * DWC3 controller driver
6 *
7 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
Ramneek Mehreshdc9cdf82015-05-29 14:47:15 +05308 */
9
Samuel Holland91ce84a2021-07-05 13:29:03 +010010#include <clk.h>
Ramneek Mehreshdc9cdf82015-05-29 14:47:15 +053011#include <common.h>
Patrice Chotardb7c1c7d2017-07-18 11:38:40 +020012#include <dm.h>
Patrice Chotardf56db162017-07-18 11:38:44 +020013#include <generic-phy.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060014#include <log.h>
Samuel Holland91ce84a2021-07-05 13:29:03 +010015#include <reset.h>
Patrice Chotardb7c1c7d2017-07-18 11:38:40 +020016#include <usb.h>
Jean-Jacques Hiblotd648a502018-11-29 10:52:45 +010017#include <dwc3-uboot.h>
Simon Glassc05ed002020-05-10 11:40:11 -060018#include <linux/delay.h>
Patrice Chotardb7c1c7d2017-07-18 11:38:40 +020019
Jean-Jacques Hiblot1708a122019-09-11 11:33:46 +020020#include <usb/xhci.h>
Ramneek Mehreshdc9cdf82015-05-29 14:47:15 +053021#include <asm/io.h>
22#include <linux/usb/dwc3.h>
Patrice Chotard576e3cc2017-07-18 11:38:41 +020023#include <linux/usb/otg.h>
Ramneek Mehreshdc9cdf82015-05-29 14:47:15 +053024
Simon Glass8a8d24b2020-12-03 16:55:23 -070025struct xhci_dwc3_plat {
Samuel Holland91ce84a2021-07-05 13:29:03 +010026 struct clk_bulk clks;
Chunfeng Yun58221d72020-05-14 13:55:11 +080027 struct phy_bulk phys;
Samuel Holland91ce84a2021-07-05 13:29:03 +010028 struct reset_ctl_bulk resets;
Patrice Chotardf56db162017-07-18 11:38:44 +020029};
30
Ramneek Mehreshdc9cdf82015-05-29 14:47:15 +053031void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
32{
33 clrsetbits_le32(&dwc3_reg->g_ctl,
34 DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
35 DWC3_GCTL_PRTCAPDIR(mode));
36}
37
Masahiro Yamada121a4d12017-06-22 16:35:14 +090038static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
Ramneek Mehreshdc9cdf82015-05-29 14:47:15 +053039{
40 /* Assert USB3 PHY reset */
41 setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
42
43 /* Assert USB2 PHY reset */
44 setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
45
46 mdelay(100);
47
48 /* Clear USB3 PHY reset */
49 clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
50
51 /* Clear USB2 PHY reset */
52 clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
53}
54
55void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
56{
57 /* Before Resetting PHY, put Core in Reset */
58 setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
59
60 /* reset USB3 phy - if required */
61 dwc3_phy_reset(dwc3_reg);
62
Rajesh Bhagat5955bb92015-12-02 11:44:27 +053063 mdelay(100);
64
Ramneek Mehreshdc9cdf82015-05-29 14:47:15 +053065 /* After PHYs are stable we can take Core out of reset state */
66 clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
67}
68
69int dwc3_core_init(struct dwc3 *dwc3_reg)
70{
71 u32 reg;
72 u32 revision;
73 unsigned int dwc3_hwparams1;
74
75 revision = readl(&dwc3_reg->g_snpsid);
76 /* This should read as U3 followed by revision number */
Mark Kettenis53eed9a2021-09-16 16:00:09 +020077 if ((revision & DWC3_GSNPSID_MASK) != 0x55330000 &&
78 (revision & DWC3_GSNPSID_MASK) != 0x33310000) {
Ramneek Mehreshdc9cdf82015-05-29 14:47:15 +053079 puts("this is not a DesignWare USB3 DRD Core\n");
80 return -1;
81 }
82
83 dwc3_core_soft_reset(dwc3_reg);
84
85 dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
86
87 reg = readl(&dwc3_reg->g_ctl);
88 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
89 reg &= ~DWC3_GCTL_DISSCRAMBLE;
90 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
91 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
92 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
93 break;
94 default:
95 debug("No power optimization available\n");
96 }
97
98 /*
99 * WORKAROUND: DWC3 revisions <1.90a have a bug
100 * where the device can fail to connect at SuperSpeed
101 * and falls back to high-speed mode which causes
102 * the device to enter a Connect/Disconnect loop
103 */
104 if ((revision & DWC3_REVISION_MASK) < 0x190a)
105 reg |= DWC3_GCTL_U2RSTECN;
106
107 writel(reg, &dwc3_reg->g_ctl);
108
109 return 0;
110}
Nikhil Badola667f4dd2015-06-23 09:17:49 +0530111
112void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
113{
114 setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
115 GFLADJ_30MHZ(val));
116}
Patrice Chotardb7c1c7d2017-07-18 11:38:40 +0200117
Sven Schwermerfd09c202018-11-21 08:43:56 +0100118#if CONFIG_IS_ENABLED(DM_USB)
Samuel Holland91ce84a2021-07-05 13:29:03 +0100119static int xhci_dwc3_reset_init(struct udevice *dev,
120 struct xhci_dwc3_plat *plat)
121{
122 int ret;
123
124 ret = reset_get_bulk(dev, &plat->resets);
125 if (ret == -ENOTSUPP || ret == -ENOENT)
126 return 0;
127 else if (ret)
128 return ret;
129
130 ret = reset_deassert_bulk(&plat->resets);
131 if (ret) {
132 reset_release_bulk(&plat->resets);
133 return ret;
134 }
135
136 return 0;
137}
138
139static int xhci_dwc3_clk_init(struct udevice *dev,
140 struct xhci_dwc3_plat *plat)
141{
142 int ret;
143
144 ret = clk_get_bulk(dev, &plat->clks);
145 if (ret == -ENOSYS || ret == -ENOENT)
146 return 0;
147 if (ret)
148 return ret;
149
150 ret = clk_enable_bulk(&plat->clks);
151 if (ret) {
152 clk_release_bulk(&plat->clks);
153 return ret;
154 }
155
156 return 0;
157}
158
Patrice Chotardb7c1c7d2017-07-18 11:38:40 +0200159static int xhci_dwc3_probe(struct udevice *dev)
160{
Patrice Chotardb7c1c7d2017-07-18 11:38:40 +0200161 struct xhci_hcor *hcor;
162 struct xhci_hccr *hccr;
163 struct dwc3 *dwc3_reg;
Patrice Chotard576e3cc2017-07-18 11:38:41 +0200164 enum usb_dr_mode dr_mode;
Simon Glass8a8d24b2020-12-03 16:55:23 -0700165 struct xhci_dwc3_plat *plat = dev_get_plat(dev);
Mark Kettenis062790f2019-06-30 18:01:55 +0200166 const char *phy;
167 u32 reg;
Patrice Chotardf56db162017-07-18 11:38:44 +0200168 int ret;
Patrice Chotardb7c1c7d2017-07-18 11:38:40 +0200169
Samuel Holland91ce84a2021-07-05 13:29:03 +0100170 ret = xhci_dwc3_reset_init(dev, plat);
171 if (ret)
172 return ret;
173
174 ret = xhci_dwc3_clk_init(dev, plat);
175 if (ret)
176 return ret;
177
Stefan Roese72a53ac2020-08-24 13:04:36 +0200178 hccr = (struct xhci_hccr *)((uintptr_t)dev_remap_addr(dev));
Patrice Chotardd38a8ea2017-07-25 13:24:44 +0200179 hcor = (struct xhci_hcor *)((uintptr_t)hccr +
Patrice Chotardb7c1c7d2017-07-18 11:38:40 +0200180 HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
181
Chunfeng Yun58221d72020-05-14 13:55:11 +0800182 ret = dwc3_setup_phy(dev, &plat->phys);
Jean-Jacques Hiblotd648a502018-11-29 10:52:45 +0100183 if (ret && (ret != -ENOTSUPP))
Vignesh R3fc26352018-03-07 14:50:09 +0530184 return ret;
Vignesh R2fd42422018-03-07 14:50:10 +0530185
Patrice Chotardb7c1c7d2017-07-18 11:38:40 +0200186 dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
187
188 dwc3_core_init(dwc3_reg);
189
Mark Kettenis062790f2019-06-30 18:01:55 +0200190 /* Set dwc3 usb2 phy config */
191 reg = readl(&dwc3_reg->g_usb2phycfg[0]);
192
193 phy = dev_read_string(dev, "phy_type");
194 if (phy && strcmp(phy, "utmi_wide") == 0) {
195 reg |= DWC3_GUSB2PHYCFG_PHYIF;
196 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
197 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
198 }
199
200 if (dev_read_bool(dev, "snps,dis_enblslpm-quirk"))
201 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
202
203 if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
204 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
205
Neil Armstrongb35b8072019-09-09 18:52:39 +0000206 if (dev_read_bool(dev, "snps,dis_u2_susphy_quirk"))
207 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
208
Mark Kettenis062790f2019-06-30 18:01:55 +0200209 writel(reg, &dwc3_reg->g_usb2phycfg[0]);
210
Simon Glassf10643c2020-12-19 10:40:14 -0700211 dr_mode = usb_get_dr_mode(dev_ofnode(dev));
Mark Kettenis6a6468f2022-04-19 21:06:33 +0200212 if (dr_mode == USB_DR_MODE_OTG &&
213 dev_read_bool(dev, "usb-role-switch")) {
214 dr_mode = usb_get_role_switch_default_mode(dev_ofnode(dev));
215 if (dr_mode == USB_DR_MODE_UNKNOWN)
216 dr_mode = USB_DR_MODE_OTG;
217 }
Patrice Chotard576e3cc2017-07-18 11:38:41 +0200218 if (dr_mode == USB_DR_MODE_UNKNOWN)
219 /* by default set dual role mode to HOST */
220 dr_mode = USB_DR_MODE_HOST;
221
222 dwc3_set_mode(dwc3_reg, dr_mode);
223
Patrice Chotardb7c1c7d2017-07-18 11:38:40 +0200224 return xhci_register(dev, hccr, hcor);
225}
226
227static int xhci_dwc3_remove(struct udevice *dev)
228{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700229 struct xhci_dwc3_plat *plat = dev_get_plat(dev);
Jean-Jacques Hiblotd648a502018-11-29 10:52:45 +0100230
Chunfeng Yun58221d72020-05-14 13:55:11 +0800231 dwc3_shutdown_phy(dev, &plat->phys);
Patrice Chotardf56db162017-07-18 11:38:44 +0200232
Samuel Holland91ce84a2021-07-05 13:29:03 +0100233 clk_release_bulk(&plat->clks);
234
235 reset_release_bulk(&plat->resets);
236
Patrice Chotardb7c1c7d2017-07-18 11:38:40 +0200237 return xhci_deregister(dev);
238}
239
240static const struct udevice_id xhci_dwc3_ids[] = {
241 { .compatible = "snps,dwc3" },
242 { }
243};
244
245U_BOOT_DRIVER(xhci_dwc3) = {
246 .name = "xhci-dwc3",
247 .id = UCLASS_USB,
248 .of_match = xhci_dwc3_ids,
249 .probe = xhci_dwc3_probe,
250 .remove = xhci_dwc3_remove,
251 .ops = &xhci_usb_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700252 .priv_auto = sizeof(struct xhci_ctrl),
Simon Glass8a8d24b2020-12-03 16:55:23 -0700253 .plat_auto = sizeof(struct xhci_dwc3_plat),
Patrice Chotardb7c1c7d2017-07-18 11:38:40 +0200254 .flags = DM_FLAG_ALLOC_PRIV_DMA,
255};
Patrice Chotard623b7ac2017-07-24 17:07:03 +0200256#endif