blob: bb0e0ceb32ecb2bc863347c09226276322c4afbd [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Michal Simek38716182014-02-05 08:06:29 +01002/*
3 * Copyright (c) 2004-2008 Texas Instruments
4 *
5 * (C) Copyright 2002
6 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
Michal Simek38716182014-02-05 08:06:29 +01007 */
8
9OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
10OUTPUT_ARCH(arm)
11ENTRY(_start)
12SECTIONS
13{
14 . = 0x00000000;
15
16 . = ALIGN(4);
17 .text :
18 {
19 *(.__image_copy_start)
Masahiro Yamadaa811db52014-06-05 19:47:45 +090020 *(.vectors)
Michal Simek38716182014-02-05 08:06:29 +010021 CPUDIR/start.o (.text*)
Alexander Graf7e21fbc2018-06-12 07:48:37 +020022 }
23
24 /* This needs to come before *(.text*) */
25 .__efi_runtime_start : {
26 *(.__efi_runtime_start)
27 }
28
29 .efi_runtime : {
30 *(.text.efi_runtime*)
31 *(.rodata.efi_runtime*)
32 *(.data.efi_runtime*)
33 }
34
35 .__efi_runtime_stop : {
36 *(.__efi_runtime_stop)
37 }
38
39 .text_rest :
40 {
Michal Simek38716182014-02-05 08:06:29 +010041 *(.text*)
42 }
43
44 . = ALIGN(4);
45 .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
46
47 . = ALIGN(4);
48 .data : {
49 *(.data*)
50 }
51
52 . = ALIGN(4);
53
54 . = .;
55
56 . = ALIGN(4);
Andrew Scull99e2fbc2022-05-30 10:00:04 +000057 __u_boot_list : {
58 KEEP(*(SORT(__u_boot_list*)));
Michal Simek38716182014-02-05 08:06:29 +010059 }
60
Ilias Apalodimas6b7f91c2024-03-15 08:43:47 +020061 .efi_runtime_rel ALIGN(4) : {
62 __efi_runtime_rel_start = .;
Alexander Graf7e21fbc2018-06-12 07:48:37 +020063 *(.rel*.efi_runtime)
64 *(.rel*.efi_runtime.*)
Ilias Apalodimas6b7f91c2024-03-15 08:43:47 +020065 __efi_runtime_rel_stop = .;
Alexander Graff5e46b42017-07-03 13:41:34 +020066 }
67
Michal Simekbe3a73c2022-08-31 11:28:59 +020068 . = ALIGN(8);
Michal Simek38716182014-02-05 08:06:29 +010069 .image_copy_end :
70 {
71 *(.__image_copy_end)
72 }
73
74 .rel_dyn_start :
75 {
76 *(.__rel_dyn_start)
77 }
78
79 .rel.dyn : {
80 *(.rel*)
81 }
82
83 .rel_dyn_end :
84 {
85 *(.__rel_dyn_end)
86 }
87
Albert ARIBAUDd0b5d9d2014-02-22 17:53:42 +010088 .end :
89 {
90 *(.__end)
91 }
92
93 _image_binary_end = .;
Michal Simek38716182014-02-05 08:06:29 +010094
95/*
Ilias Apalodimasfaf396a2024-03-15 08:43:46 +020096 * These sections occupy the same memory, but their lifetimes do
97 * not overlap: U-Boot initializes .bss only after applying dynamic
98 * relocations and therefore after it doesn't need .rel.dyn any more.
Michal Simek38716182014-02-05 08:06:29 +010099 */
Ilias Apalodimasfaf396a2024-03-15 08:43:46 +0200100 .bss ADDR(.rel.dyn) (OVERLAY): {
101 __bss_start = .;
Michal Simek38716182014-02-05 08:06:29 +0100102 *(.bss*)
Ilias Apalodimasfaf396a2024-03-15 08:43:46 +0200103 . = ALIGN(8);
104 __bss_end = .;
Michal Simek38716182014-02-05 08:06:29 +0100105 }
106
107 /*
Albert ARIBAUD41623c92014-04-15 16:13:51 +0200108 * Zynq needs to discard these sections because the user
Michal Simek38716182014-02-05 08:06:29 +0100109 * is expected to pass this image on to tools for boot.bin
110 * generation that require them to be dropped.
111 */
112 /DISCARD/ : { *(.dynsym) }
113 /DISCARD/ : { *(.dynbss*) }
114 /DISCARD/ : { *(.dynstr*) }
115 /DISCARD/ : { *(.dynamic*) }
116 /DISCARD/ : { *(.plt*) }
117 /DISCARD/ : { *(.interp*) }
118 /DISCARD/ : { *(.gnu*) }
119 /DISCARD/ : { *(.ARM.exidx*) }
120 /DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
121}