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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 6ba2da90de9acbdfbc0ad1519fd2905e9548cb34 / . / arch / arm / cpu / arm720t / start.S
blob: 365d8f08cb093075d7a68583ed50d37fc5c5f292 [file] [log] [blame]
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]1/*
2 * armboot - Startup Code for ARM720 CPU-core
3 *
Albert ARIBAUDfa82f872011-08-04 18:45:45 +0200[diff] [blame]4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]8 */
9
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200[diff] [blame]10#include <asm-offsets.h>
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]11#include <config.h>
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]12
13/*
14 *************************************************************************
15 *
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]16 * Startup Code (reset vector)
17 *
wdenkf6e20fc2004-02-08 19:38:38 +0000[diff] [blame]18 * do important init only if we don't start from RAM!
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]19 * relocate armboot to ram
20 * setup stack
21 * jump to second stage
22 *
23 *************************************************************************
24 */
25
Albert ARIBAUD41623c92014-04-15 16:13:51 +0200[diff] [blame]26 .globl reset
Heiko Schocherabef7b82010-09-17 13:10:52 +0200[diff] [blame]27
28reset:
29 /*
30 * set the cpu to SVC32 mode
31 */
32 mrs r0,cpsr
33 bic r0,r0,#0x1f
34 orr r0,r0,#0xd3
35 msr cpsr,r0
36
37 /*
38 * we do sys-critical inits only at reboot,
39 * not when booting from ram!
40 */
Simon Glass1c2d2722017-05-31 17:57:11 -0600[diff] [blame]41#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
42 !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
Heiko Schocherabef7b82010-09-17 13:10:52 +0200[diff] [blame]43 bl cpu_init_crit
44#endif
45
Albert ARIBAUDe05e5de2013-01-08 10:18:02 +0000[diff] [blame]46 bl _main
Heiko Schocherabef7b82010-09-17 13:10:52 +0200[diff] [blame]47
48/*------------------------------------------------------------------------------*/
49
Albert ARIBAUDe05e5de2013-01-08 10:18:02 +0000[diff] [blame]50 .globl c_runtime_cpu_setup
51c_runtime_cpu_setup:
52
53 mov pc, lr
54
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]55/*
56 *************************************************************************
57 *
58 * CPU_init_critical registers
59 *
60 * setup important registers
61 * setup memory timing
62 *
63 *************************************************************************
64 */
65
Simon Glass1c2d2722017-05-31 17:57:11 -0600[diff] [blame]66#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
67 !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]68cpu_init_crit:
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]69
Wolfgang Denk87cb6862005-10-06 17:08:18 +0200[diff] [blame]70 mov ip, lr
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]71 /*
72 * before relocating, we have to setup RAM timing
wdenkf6e20fc2004-02-08 19:38:38 +0000[diff] [blame]73 * because memory timing is board-dependent, you will
wdenk400558b2005-04-02 23:52:25 +0000[diff] [blame]74 * find a lowlevel_init.S in your board directory.
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]75 */
wdenk400558b2005-04-02 23:52:25 +0000[diff] [blame]76 bl lowlevel_init
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]77 mov lr, ip
78
79 mov pc, lr
Axel Lin578e6372013-05-21 13:44:10 +0000[diff] [blame]80#endif /* CONFIG_SKIP_LOWLEVEL_INIT */