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Tom Warren1b245fe2012-12-11 13:34:13 +00001/*
Tom Warren7aaa5a62015-03-04 16:36:00 -07002 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
Tom Warren1b245fe2012-12-11 13:34:13 +00003 *
Tom Rini5b8031c2016-01-14 22:05:13 -05004 * SPDX-License-Identifier: GPL-2.0
Tom Warren1b245fe2012-12-11 13:34:13 +00005 */
6
7#include <common.h>
8#include <asm/io.h>
9#include <asm/arch/clock.h>
10#include <asm/arch/gp_padctrl.h>
11#include <asm/arch/pinmux.h>
12#include <asm/arch/tegra.h>
13#include <asm/arch-tegra/clk_rst.h>
14#include <asm/arch-tegra/pmc.h>
15#include <asm/arch-tegra/scu.h>
16#include "cpu.h"
17
Tom Warren1b245fe2012-12-11 13:34:13 +000018int get_num_cpus(void)
19{
Tom Warren4040ec12013-01-28 13:32:08 +000020 struct apb_misc_gp_ctlr *gp;
21 uint rev;
Tom Warren7aaa5a62015-03-04 16:36:00 -070022 debug("%s entry\n", __func__);
Tom Warren4040ec12013-01-28 13:32:08 +000023
24 gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
25 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
26
27 switch (rev) {
28 case CHIPID_TEGRA20:
29 return 2;
30 break;
31 case CHIPID_TEGRA30:
32 case CHIPID_TEGRA114:
Tom Warren7aaa5a62015-03-04 16:36:00 -070033 case CHIPID_TEGRA124:
34 case CHIPID_TEGRA210:
Tom Warren4040ec12013-01-28 13:32:08 +000035 default:
36 return 4;
37 break;
38 }
Tom Warren1b245fe2012-12-11 13:34:13 +000039}
40
41/*
42 * Timing tables for each SOC for all four oscillator options.
43 */
44struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
Jimmy Zhang44de8e22013-09-23 22:07:49 +020045 /*
46 * T20: 1 GHz
47 *
48 * Register Field Bits Width
49 * ------------------------------
50 * PLLX_BASE p 22:20 3
51 * PLLX_BASE n 17: 8 10
52 * PLLX_BASE m 4: 0 5
53 * PLLX_MISC cpcon 11: 8 4
54 */
55 {
56 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
57 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
58 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
59 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
Tom Warren3e8650c2015-06-22 13:03:44 -070060 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
61 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
Tom Warren1b245fe2012-12-11 13:34:13 +000062 },
Jimmy Zhang44de8e22013-09-23 22:07:49 +020063 /*
64 * T25: 1.2 GHz
65 *
66 * Register Field Bits Width
67 * ------------------------------
68 * PLLX_BASE p 22:20 3
69 * PLLX_BASE n 17: 8 10
70 * PLLX_BASE m 4: 0 5
71 * PLLX_MISC cpcon 11: 8 4
72 */
73 {
74 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
75 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
76 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
77 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
Tom Warren3e8650c2015-06-22 13:03:44 -070078 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
79 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
Tom Warren1b245fe2012-12-11 13:34:13 +000080 },
Jimmy Zhang44de8e22013-09-23 22:07:49 +020081 /*
Stephen Warren2364e152014-05-08 09:33:45 -060082 * T30: 600 MHz
Jimmy Zhang44de8e22013-09-23 22:07:49 +020083 *
84 * Register Field Bits Width
85 * ------------------------------
86 * PLLX_BASE p 22:20 3
87 * PLLX_BASE n 17: 8 10
88 * PLLX_BASE m 4: 0 5
89 * PLLX_MISC cpcon 11: 8 4
90 */
91 {
Stephen Warren2364e152014-05-08 09:33:45 -060092 { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
93 { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
94 { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
95 { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
Tom Warren3e8650c2015-06-22 13:03:44 -070096 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
97 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
Tom Warren1b245fe2012-12-11 13:34:13 +000098 },
Jimmy Zhang44de8e22013-09-23 22:07:49 +020099 /*
100 * T114: 700 MHz
101 *
102 * Register Field Bits Width
103 * ------------------------------
104 * PLLX_BASE p 23:20 4
105 * PLLX_BASE n 15: 8 8
106 * PLLX_BASE m 7: 0 8
107 */
108 {
109 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
110 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
111 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
112 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
Tom Warren3e8650c2015-06-22 13:03:44 -0700113 { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
114 { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
Tom Warren4040ec12013-01-28 13:32:08 +0000115 },
Tom Warren32edd2e2014-01-24 12:46:14 -0700116
117 /*
118 * T124: 700 MHz
119 *
120 * Register Field Bits Width
121 * ------------------------------
122 * PLLX_BASE p 23:20 4
123 * PLLX_BASE n 15: 8 8
124 * PLLX_BASE m 7: 0 8
125 */
126 {
127 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
128 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
129 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
130 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
Tom Warren3e8650c2015-06-22 13:03:44 -0700131 { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
132 { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
Tom Warren32edd2e2014-01-24 12:46:14 -0700133 },
Tom Warren7aaa5a62015-03-04 16:36:00 -0700134
135 /*
136 * T210: 700 MHz
137 *
138 * Register Field Bits Width
139 * ------------------------------
140 * PLLX_BASE p 24:20 5
141 * PLLX_BASE n 15: 8 8
142 * PLLX_BASE m 7: 0 8
143 */
144 {
145 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/
146 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
147 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/
148 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/
Tom Warren3e8650c2015-06-22 13:03:44 -0700149 { .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */
150 { .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */
Tom Warren7aaa5a62015-03-04 16:36:00 -0700151 },
Tom Warren1b245fe2012-12-11 13:34:13 +0000152};
153
Tom Warren32edd2e2014-01-24 12:46:14 -0700154static inline void pllx_set_iddq(void)
155{
Tom Warren7aaa5a62015-03-04 16:36:00 -0700156#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
Tom Warren32edd2e2014-01-24 12:46:14 -0700157 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
158 u32 reg;
Tom Warren7aaa5a62015-03-04 16:36:00 -0700159 debug("%s entry\n", __func__);
Tom Warren32edd2e2014-01-24 12:46:14 -0700160
161 /* Disable IDDQ */
162 reg = readl(&clkrst->crc_pllx_misc3);
163 reg &= ~PLLX_IDDQ_MASK;
164 writel(reg, &clkrst->crc_pllx_misc3);
165 udelay(2);
166 debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
167 readl(&clkrst->crc_pllx_misc3));
168#endif
169}
170
Tom Warren1b245fe2012-12-11 13:34:13 +0000171int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
172 u32 divp, u32 cpcon)
173{
Tom Warren722e0002015-06-25 09:50:44 -0700174 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
Thierry Reding4475c772013-10-01 17:04:45 +0200175 int chip = tegra_get_chip();
Tom Warren1b245fe2012-12-11 13:34:13 +0000176 u32 reg;
Tom Warren7aaa5a62015-03-04 16:36:00 -0700177 debug("%s entry\n", __func__);
Tom Warren1b245fe2012-12-11 13:34:13 +0000178
179 /* If PLLX is already enabled, just return */
180 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
Tom Warren7aaa5a62015-03-04 16:36:00 -0700181 debug("%s: PLLX already enabled, returning\n", __func__);
Tom Warren1b245fe2012-12-11 13:34:13 +0000182 return 0;
183 }
184
Tom Warren32edd2e2014-01-24 12:46:14 -0700185 pllx_set_iddq();
186
Tom Warren1b245fe2012-12-11 13:34:13 +0000187 /* Set BYPASS, m, n and p to PLLX_BASE */
Tom Warren722e0002015-06-25 09:50:44 -0700188 reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift);
189 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift);
Tom Warren1b245fe2012-12-11 13:34:13 +0000190 writel(reg, &pll->pll_base);
191
192 /* Set cpcon to PLLX_MISC */
Thierry Reding4475c772013-10-01 17:04:45 +0200193 if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
Tom Warren722e0002015-06-25 09:50:44 -0700194 reg = (cpcon << pllinfo->kcp_shift);
Thierry Reding4475c772013-10-01 17:04:45 +0200195 else
196 reg = 0;
Tom Warren1b245fe2012-12-11 13:34:13 +0000197
Tom Warren722e0002015-06-25 09:50:44 -0700198 /*
199 * TODO(twarren@nvidia.com) Check which SoCs use DCCON
200 * and add to pllinfo table if needed!
201 */
202 /* Set dccon to PLLX_MISC if freq > 600MHz */
Tom Warren1b245fe2012-12-11 13:34:13 +0000203 if (divn > 600)
204 reg |= (1 << PLL_DCCON_SHIFT);
205 writel(reg, &pll->pll_misc);
206
Tom Warren1b245fe2012-12-11 13:34:13 +0000207 /* Disable BYPASS */
Stephen Warren41447fb2014-01-24 12:46:09 -0700208 reg = readl(&pll->pll_base);
Tom Warren1b245fe2012-12-11 13:34:13 +0000209 reg &= ~PLL_BYPASS_MASK;
210 writel(reg, &pll->pll_base);
Tom Warren7aaa5a62015-03-04 16:36:00 -0700211 debug("%s: base = 0x%08X\n", __func__, reg);
Tom Warren1b245fe2012-12-11 13:34:13 +0000212
Tom Warren722e0002015-06-25 09:50:44 -0700213 /* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */
Tom Warren1b245fe2012-12-11 13:34:13 +0000214 reg = readl(&pll->pll_misc);
Tom Warren722e0002015-06-25 09:50:44 -0700215 if (pllinfo->lock_ena < 32)
216 reg |= (1 << pllinfo->lock_ena);
Tom Warren1b245fe2012-12-11 13:34:13 +0000217 writel(reg, &pll->pll_misc);
Tom Warren7aaa5a62015-03-04 16:36:00 -0700218 debug("%s: misc = 0x%08X\n", __func__, reg);
Stephen Warren41447fb2014-01-24 12:46:09 -0700219
220 /* Enable PLLX last, once it's all configured */
221 reg = readl(&pll->pll_base);
222 reg |= PLL_ENABLE_MASK;
223 writel(reg, &pll->pll_base);
Tom Warren7aaa5a62015-03-04 16:36:00 -0700224 debug("%s: base final = 0x%08X\n", __func__, reg);
Tom Warren1b245fe2012-12-11 13:34:13 +0000225
226 return 0;
227}
228
229void init_pllx(void)
230{
231 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
232 struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
Tom Warren49493cb2013-04-10 10:32:32 -0700233 int soc_type, sku_info, chip_sku;
Tom Warren1b245fe2012-12-11 13:34:13 +0000234 enum clock_osc_freq osc;
235 struct clk_pll_table *sel;
Tom Warren7aaa5a62015-03-04 16:36:00 -0700236 debug("%s entry\n", __func__);
Tom Warren1b245fe2012-12-11 13:34:13 +0000237
Tom Warren49493cb2013-04-10 10:32:32 -0700238 /* get SOC (chip) type */
239 soc_type = tegra_get_chip();
Tom Warren7aaa5a62015-03-04 16:36:00 -0700240 debug("%s: SoC = 0x%02X\n", __func__, soc_type);
Tom Warren49493cb2013-04-10 10:32:32 -0700241
242 /* get SKU info */
243 sku_info = tegra_get_sku_info();
Tom Warren7aaa5a62015-03-04 16:36:00 -0700244 debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info);
Tom Warren49493cb2013-04-10 10:32:32 -0700245
246 /* get chip SKU, combo of the above info */
247 chip_sku = tegra_get_chip_sku();
Tom Warren7aaa5a62015-03-04 16:36:00 -0700248 debug("%s: Chip SKU = %d\n", __func__, chip_sku);
Tom Warren1b245fe2012-12-11 13:34:13 +0000249
250 /* get osc freq */
251 osc = clock_get_osc_freq();
Tom Warren7aaa5a62015-03-04 16:36:00 -0700252 debug("%s: osc = %d\n", __func__, osc);
Tom Warren1b245fe2012-12-11 13:34:13 +0000253
254 /* set pllx */
Tom Warren49493cb2013-04-10 10:32:32 -0700255 sel = &tegra_pll_x_table[chip_sku][osc];
Tom Warren1b245fe2012-12-11 13:34:13 +0000256 pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
Tom Warren1b245fe2012-12-11 13:34:13 +0000257}
258
259void enable_cpu_clock(int enable)
260{
261 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
262 u32 clk;
Tom Warren7aaa5a62015-03-04 16:36:00 -0700263 debug("%s entry\n", __func__);
Tom Warren1b245fe2012-12-11 13:34:13 +0000264
265 /*
266 * NOTE:
267 * Regardless of whether the request is to enable or disable the CPU
268 * clock, every processor in the CPU complex except the master (CPU 0)
269 * will have it's clock stopped because the AVP only talks to the
270 * master.
271 */
272
273 if (enable) {
274 /* Initialize PLLX */
275 init_pllx();
276
277 /* Wait until all clocks are stable */
278 udelay(PLL_STABILIZATION_DELAY);
279
280 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
281 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
282 }
283
284 /*
285 * Read the register containing the individual CPU clock enables and
286 * always stop the clocks to CPUs > 0.
287 */
288 clk = readl(&clkrst->crc_clk_cpu_cmplx);
289 clk |= 1 << CPU1_CLK_STP_SHIFT;
Tom Warren4040ec12013-01-28 13:32:08 +0000290 if (get_num_cpus() == 4)
291 clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
292
Tom Warren1b245fe2012-12-11 13:34:13 +0000293 /* Stop/Unstop the CPU clock */
294 clk &= ~CPU0_CLK_STP_MASK;
295 clk |= !enable << CPU0_CLK_STP_SHIFT;
296 writel(clk, &clkrst->crc_clk_cpu_cmplx);
297
298 clock_enable(PERIPH_ID_CPU);
299}
300
301static int is_cpu_powered(void)
302{
303 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
304
305 return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
306}
307
308static void remove_cpu_io_clamps(void)
309{
310 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
311 u32 reg;
Tom Warren7aaa5a62015-03-04 16:36:00 -0700312 debug("%s entry\n", __func__);
Tom Warren1b245fe2012-12-11 13:34:13 +0000313
314 /* Remove the clamps on the CPU I/O signals */
315 reg = readl(&pmc->pmc_remove_clamping);
316 reg |= CPU_CLMP;
317 writel(reg, &pmc->pmc_remove_clamping);
318
319 /* Give I/O signals time to stabilize */
320 udelay(IO_STABILIZATION_DELAY);
321}
322
323void powerup_cpu(void)
324{
325 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
326 u32 reg;
327 int timeout = IO_STABILIZATION_DELAY;
Tom Warren7aaa5a62015-03-04 16:36:00 -0700328 debug("%s entry\n", __func__);
Tom Warren1b245fe2012-12-11 13:34:13 +0000329
330 if (!is_cpu_powered()) {
331 /* Toggle the CPU power state (OFF -> ON) */
332 reg = readl(&pmc->pmc_pwrgate_toggle);
333 reg &= PARTID_CP;
334 reg |= START_CP;
335 writel(reg, &pmc->pmc_pwrgate_toggle);
336
337 /* Wait for the power to come up */
338 while (!is_cpu_powered()) {
339 if (timeout-- == 0)
340 printf("CPU failed to power up!\n");
341 else
342 udelay(10);
343 }
344
345 /*
346 * Remove the I/O clamps from CPU power partition.
347 * Recommended only on a Warm boot, if the CPU partition gets
348 * power gated. Shouldn't cause any harm when called after a
349 * cold boot according to HW, probably just redundant.
350 */
351 remove_cpu_io_clamps();
352 }
353}
354
355void reset_A9_cpu(int reset)
356{
357 /*
358 * NOTE: Regardless of whether the request is to hold the CPU in reset
359 * or take it out of reset, every processor in the CPU complex
360 * except the master (CPU 0) will be held in reset because the
361 * AVP only talks to the master. The AVP does not know that there
362 * are multiple processors in the CPU complex.
363 */
364 int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
365 int num_cpus = get_num_cpus();
366 int cpu;
367
Tom Warren7aaa5a62015-03-04 16:36:00 -0700368 debug("%s entry\n", __func__);
Tom Warren1b245fe2012-12-11 13:34:13 +0000369 /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
370 for (cpu = 1; cpu < num_cpus; cpu++)
371 reset_cmplx_set_enable(cpu, mask, 1);
372 reset_cmplx_set_enable(0, mask, reset);
373
374 /* Enable/Disable master CPU reset */
375 reset_set_enable(PERIPH_ID_CPU, reset);
376}
377
378void clock_enable_coresight(int enable)
379{
Tom Warren4040ec12013-01-28 13:32:08 +0000380 u32 rst, src = 2;
Tom Warren1b245fe2012-12-11 13:34:13 +0000381
Tom Warren7aaa5a62015-03-04 16:36:00 -0700382 debug("%s entry\n", __func__);
Tom Warren1b245fe2012-12-11 13:34:13 +0000383 clock_set_enable(PERIPH_ID_CORESIGHT, enable);
384 reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
385
386 if (enable) {
387 /*
Tom Warren49493cb2013-04-10 10:32:32 -0700388 * Put CoreSight on PLLP_OUT0 and divide it down as per
Tom Warren32edd2e2014-01-24 12:46:14 -0700389 * PLLP base frequency based on SoC type (T20/T30+).
Tom Warren49493cb2013-04-10 10:32:32 -0700390 * Clock divider request would setup CSITE clock as 144MHz
391 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
Tom Warren1b245fe2012-12-11 13:34:13 +0000392 */
Stephen Warrena4bcd672014-01-24 12:46:10 -0700393 src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
Tom Warren1b245fe2012-12-11 13:34:13 +0000394 clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
395
396 /* Unlock the CPU CoreSight interfaces */
397 rst = CORESIGHT_UNLOCK;
398 writel(rst, CSITE_CPU_DBG0_LAR);
399 writel(rst, CSITE_CPU_DBG1_LAR);
Tom Warren4040ec12013-01-28 13:32:08 +0000400 if (get_num_cpus() == 4) {
401 writel(rst, CSITE_CPU_DBG2_LAR);
402 writel(rst, CSITE_CPU_DBG3_LAR);
403 }
Tom Warren1b245fe2012-12-11 13:34:13 +0000404 }
405}
406
407void halt_avp(void)
408{
Tom Warren7aaa5a62015-03-04 16:36:00 -0700409 debug("%s entry\n", __func__);
410
Tom Warren1b245fe2012-12-11 13:34:13 +0000411 for (;;) {
Stephen Warren716ff5c2014-02-03 14:03:27 -0700412 writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
413 FLOW_CTLR_HALT_COP_EVENTS);
Tom Warren1b245fe2012-12-11 13:34:13 +0000414 }
415}