Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Simon Glass | 6ec1b75 | 2014-12-10 08:55:51 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Test-related constants for sandbox |
| 4 | * |
| 5 | * Copyright (c) 2014 Google, Inc |
Simon Glass | 6ec1b75 | 2014-12-10 08:55:51 -0700 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __ASM_TEST_H |
| 9 | #define __ASM_TEST_H |
| 10 | |
| 11 | /* The sandbox driver always permits an I2C device with this address */ |
Simon Glass | 9569c40 | 2015-03-05 12:25:26 -0700 | [diff] [blame] | 12 | #define SANDBOX_I2C_TEST_ADDR 0x59 |
| 13 | |
| 14 | #define SANDBOX_PCI_VENDOR_ID 0x1234 |
Simon Glass | 3414581 | 2019-09-25 08:56:01 -0600 | [diff] [blame] | 15 | #define SANDBOX_PCI_SWAP_CASE_EMUL_ID 0x5678 |
Simon Glass | 3b65ee3 | 2019-12-06 21:41:54 -0700 | [diff] [blame] | 16 | #define SANDBOX_PCI_PMC_EMUL_ID 0x5677 |
Simon Glass | 3e17ffb | 2019-12-06 21:41:57 -0700 | [diff] [blame] | 17 | #define SANDBOX_PCI_P2SB_EMUL_ID 0x5676 |
Simon Glass | 9569c40 | 2015-03-05 12:25:26 -0700 | [diff] [blame] | 18 | #define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM |
| 19 | #define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL |
Simon Glass | 6ec1b75 | 2014-12-10 08:55:51 -0700 | [diff] [blame] | 20 | |
Bin Meng | 95e1106 | 2018-08-03 01:14:53 -0700 | [diff] [blame] | 21 | #define PCI_CAP_ID_PM_OFFSET 0x50 |
| 22 | #define PCI_CAP_ID_EXP_OFFSET 0x60 |
| 23 | #define PCI_CAP_ID_MSIX_OFFSET 0x70 |
Alex Marginean | 21ebbaf | 2019-06-07 11:24:24 +0300 | [diff] [blame] | 24 | #define PCI_CAP_ID_EA_OFFSET 0x80 |
Bin Meng | 95e1106 | 2018-08-03 01:14:53 -0700 | [diff] [blame] | 25 | |
| 26 | #define PCI_EXT_CAP_ID_ERR_OFFSET 0x100 |
| 27 | #define PCI_EXT_CAP_ID_VC_OFFSET 0x200 |
| 28 | #define PCI_EXT_CAP_ID_DSN_OFFSET 0x300 |
| 29 | |
Bin Meng | 59a160e | 2018-08-03 01:14:46 -0700 | [diff] [blame] | 30 | /* Useful for PCI_VDEVICE() macro */ |
| 31 | #define PCI_VENDOR_ID_SANDBOX SANDBOX_PCI_VENDOR_ID |
| 32 | #define SWAP_CASE_DRV_DATA 0x55aa |
| 33 | |
Simon Glass | 6a1c7ce | 2015-07-06 12:54:24 -0600 | [diff] [blame] | 34 | #define SANDBOX_CLK_RATE 32768 |
| 35 | |
Alex Marginean | 21ebbaf | 2019-06-07 11:24:24 +0300 | [diff] [blame] | 36 | /* Macros used to test PCI EA capability structure */ |
| 37 | #define PCI_CAP_EA_BASE_LO0 0x00100000 |
| 38 | #define PCI_CAP_EA_BASE_LO1 0x00110000 |
| 39 | #define PCI_CAP_EA_BASE_LO2 0x00120000 |
| 40 | #define PCI_CAP_EA_BASE_LO4 0x00140000 |
| 41 | #define PCI_CAP_EA_BASE_HI2 0x00020000ULL |
| 42 | #define PCI_CAP_EA_BASE_HI4 0x00040000ULL |
| 43 | #define PCI_CAP_EA_SIZE_LO 0x0000ffff |
| 44 | #define PCI_CAP_EA_SIZE_HI 0x00000010ULL |
| 45 | #define PCI_EA_BAR2_MAGIC 0x72727272 |
| 46 | #define PCI_EA_BAR4_MAGIC 0x74747474 |
| 47 | |
Simon Glass | 04035fd | 2015-07-06 12:54:35 -0600 | [diff] [blame] | 48 | /* System controller driver data */ |
| 49 | enum { |
| 50 | SYSCON0 = 32, |
| 51 | SYSCON1, |
| 52 | |
| 53 | SYSCON_COUNT |
| 54 | }; |
| 55 | |
Simon Glass | 182bf92 | 2015-04-20 12:37:15 -0600 | [diff] [blame] | 56 | /** |
| 57 | * sandbox_i2c_set_test_mode() - set test mode for running unit tests |
| 58 | * |
| 59 | * See sandbox_i2c_xfer() for the behaviour changes. |
| 60 | * |
| 61 | * @bus: sandbox I2C bus to adjust |
| 62 | * @test_mode: true to select test mode, false to run normally |
| 63 | */ |
| 64 | void sandbox_i2c_set_test_mode(struct udevice *bus, bool test_mode); |
| 65 | |
Simon Glass | 6ec1b75 | 2014-12-10 08:55:51 -0700 | [diff] [blame] | 66 | enum sandbox_i2c_eeprom_test_mode { |
| 67 | SIE_TEST_MODE_NONE, |
| 68 | /* Permits read/write of only one byte per I2C transaction */ |
| 69 | SIE_TEST_MODE_SINGLE_BYTE, |
| 70 | }; |
| 71 | |
| 72 | void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev, |
| 73 | enum sandbox_i2c_eeprom_test_mode mode); |
| 74 | |
| 75 | void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len); |
| 76 | |
Robert Beckett | 951674a | 2019-10-28 17:44:59 +0000 | [diff] [blame] | 77 | void sandbox_i2c_eeprom_set_chip_addr_offset_mask(struct udevice *dev, |
| 78 | uint mask); |
| 79 | |
Robert Beckett | 22e9351 | 2019-10-28 17:44:58 +0000 | [diff] [blame] | 80 | uint sanbox_i2c_eeprom_get_prev_addr(struct udevice *dev); |
| 81 | |
| 82 | uint sanbox_i2c_eeprom_get_prev_offset(struct udevice *dev); |
| 83 | |
Simon Glass | dd18e5d | 2015-04-20 12:37:24 -0600 | [diff] [blame] | 84 | /** |
| 85 | * sandbox_i2c_rtc_set_offset() - set the time offset from system/base time |
| 86 | * |
| 87 | * @dev: RTC device to adjust |
| 88 | * @use_system_time: true to use system time, false to use @base_time |
| 89 | * @offset: RTC offset from current system/base time (-1 for no |
| 90 | * change) |
| 91 | * @return old value of RTC offset |
| 92 | */ |
| 93 | long sandbox_i2c_rtc_set_offset(struct udevice *dev, bool use_system_time, |
| 94 | int offset); |
| 95 | |
| 96 | /** |
| 97 | * sandbox_i2c_rtc_get_set_base_time() - get and set the base time |
| 98 | * |
| 99 | * @dev: RTC device to adjust |
| 100 | * @base_time: New base system time (set to -1 for no change) |
| 101 | * @return old base time |
| 102 | */ |
| 103 | long sandbox_i2c_rtc_get_set_base_time(struct udevice *dev, long base_time); |
| 104 | |
Simon Glass | d8a26f0 | 2015-11-08 23:48:06 -0700 | [diff] [blame] | 105 | int sandbox_usb_keyb_add_string(struct udevice *dev, const char *str); |
| 106 | |
Mario Six | 4eea531 | 2018-09-27 09:19:31 +0200 | [diff] [blame] | 107 | /** |
| 108 | * sandbox_osd_get_mem() - get the internal memory of a sandbox OSD |
| 109 | * |
| 110 | * @dev: OSD device for which to access the internal memory for |
| 111 | * @buf: pointer to buffer to receive the OSD memory data |
| 112 | * @buflen: length of buffer in bytes |
| 113 | */ |
| 114 | int sandbox_osd_get_mem(struct udevice *dev, u8 *buf, size_t buflen); |
Simon Glass | 5d9a88f | 2018-10-01 12:22:40 -0600 | [diff] [blame] | 115 | |
| 116 | /** |
| 117 | * sandbox_pwm_get_config() - get the PWM config for a channel |
| 118 | * |
| 119 | * @dev: Device to check |
| 120 | * @channel: Channel number to check |
| 121 | * @period_ns: Period of the PWM in nanoseconds |
| 122 | * @duty_ns: Current duty cycle of the PWM in nanoseconds |
| 123 | * @enable: true if the PWM is enabled |
| 124 | * @polarity: true if the PWM polarity is active high |
| 125 | * @return 0 if OK, -ENOSPC if the PWM number is invalid |
| 126 | */ |
| 127 | int sandbox_pwm_get_config(struct udevice *dev, uint channel, uint *period_nsp, |
| 128 | uint *duty_nsp, bool *enablep, bool *polarityp); |
| 129 | |
Simon Glass | a58986c | 2018-11-06 15:21:41 -0700 | [diff] [blame] | 130 | /** |
| 131 | * sandbox_sf_set_block_protect() - Set the BP bits of the status register |
| 132 | * |
| 133 | * @dev: Device to update |
| 134 | * @bp_mask: BP bits to set (bits 2:0, so a value of 0 to 7) |
| 135 | */ |
| 136 | void sandbox_sf_set_block_protect(struct udevice *dev, int bp_mask); |
| 137 | |
Simon Glass | ce6d99a | 2018-12-10 10:37:33 -0700 | [diff] [blame] | 138 | /** |
| 139 | * sandbox_get_codec_params() - Read back codec parameters |
| 140 | * |
| 141 | * This reads back the parameters set by audio_codec_set_params() for the |
| 142 | * sandbox audio driver. Arguments are as for that function. |
| 143 | */ |
| 144 | void sandbox_get_codec_params(struct udevice *dev, int *interfacep, int *ratep, |
| 145 | int *mclk_freqp, int *bits_per_samplep, |
| 146 | uint *channelsp); |
| 147 | |
Simon Glass | e96fa6c | 2018-12-10 10:37:34 -0700 | [diff] [blame] | 148 | /** |
| 149 | * sandbox_get_i2s_sum() - Read back the sum of the audio data so far |
| 150 | * |
| 151 | * This data is provided to the sandbox driver by the I2S tx_data() method. |
| 152 | * |
| 153 | * @dev: Device to check |
| 154 | * @return sum of audio data |
| 155 | */ |
| 156 | int sandbox_get_i2s_sum(struct udevice *dev); |
| 157 | |
Simon Glass | d490189 | 2018-12-10 10:37:36 -0700 | [diff] [blame] | 158 | /** |
| 159 | * sandbox_get_setup_called() - Returns the number of times setup(*) was called |
| 160 | * |
| 161 | * This is used in the sound test |
| 162 | * |
| 163 | * @dev: Device to check |
| 164 | * @return call count for the setup() method |
| 165 | */ |
| 166 | int sandbox_get_setup_called(struct udevice *dev); |
| 167 | |
| 168 | /** |
Simon Glass | 3062cd1 | 2020-02-03 07:36:06 -0700 | [diff] [blame] | 169 | * sandbox_get_sound_active() - Returns whether sound play is in progress |
| 170 | * |
| 171 | * @return true if active, false if not |
| 172 | */ |
| 173 | int sandbox_get_sound_active(struct udevice *dev); |
| 174 | |
| 175 | /** |
Simon Glass | d490189 | 2018-12-10 10:37:36 -0700 | [diff] [blame] | 176 | * sandbox_get_sound_sum() - Read back the sum of the sound data so far |
| 177 | * |
| 178 | * This data is provided to the sandbox driver by the sound play() method. |
| 179 | * |
| 180 | * @dev: Device to check |
| 181 | * @return sum of audio data |
| 182 | */ |
| 183 | int sandbox_get_sound_sum(struct udevice *dev); |
| 184 | |
Simon Glass | b45c833 | 2019-02-16 20:24:50 -0700 | [diff] [blame] | 185 | /** |
Simon Glass | 2850266 | 2019-02-16 20:24:54 -0700 | [diff] [blame] | 186 | * sandbox_set_allow_beep() - Set whether the 'beep' interface is supported |
| 187 | * |
| 188 | * @dev: Device to update |
| 189 | * @allow: true to allow the start_beep() method, false to disallow it |
| 190 | */ |
| 191 | void sandbox_set_allow_beep(struct udevice *dev, bool allow); |
| 192 | |
| 193 | /** |
| 194 | * sandbox_get_beep_frequency() - Get the frequency of the current beep |
| 195 | * |
| 196 | * @dev: Device to check |
| 197 | * @return frequency of beep, if there is an active beep, else 0 |
| 198 | */ |
| 199 | int sandbox_get_beep_frequency(struct udevice *dev); |
| 200 | |
| 201 | /** |
Simon Glass | b45c833 | 2019-02-16 20:24:50 -0700 | [diff] [blame] | 202 | * sandbox_get_pch_spi_protect() - Get the PCI SPI protection status |
| 203 | * |
| 204 | * @dev: Device to check |
| 205 | * @return 0 if not protected, 1 if protected |
| 206 | */ |
| 207 | int sandbox_get_pch_spi_protect(struct udevice *dev); |
| 208 | |
Ramon Fried | f2a55ac | 2019-04-27 11:15:24 +0300 | [diff] [blame] | 209 | /** |
| 210 | * sandbox_get_pci_ep_irq_count() - Get the PCI EP IRQ count |
| 211 | * |
| 212 | * @dev: Device to check |
| 213 | * @return irq count |
| 214 | */ |
| 215 | int sandbox_get_pci_ep_irq_count(struct udevice *dev); |
| 216 | |
Simon Glass | 75d8f49 | 2019-09-25 08:56:42 -0600 | [diff] [blame] | 217 | /** |
| 218 | * sandbox_pci_read_bar() - Read the BAR value for a read_config operation |
| 219 | * |
| 220 | * This is used in PCI emulators to read a base address reset. This has special |
| 221 | * rules because when the register is set to 0xffffffff it can be used to |
| 222 | * discover the type and size of the BAR. |
| 223 | * |
| 224 | * @barval: Current value of the BAR |
| 225 | * @type: Type of BAR (PCI_BASE_ADDRESS_SPACE_IO or |
| 226 | * PCI_BASE_ADDRESS_MEM_TYPE_32) |
| 227 | * @size: Size of BAR in bytes |
| 228 | * @return BAR value to return from emulator |
| 229 | */ |
| 230 | uint sandbox_pci_read_bar(u32 barval, int type, uint size); |
| 231 | |
Simon Glass | 619025b | 2019-10-11 16:16:48 -0600 | [diff] [blame] | 232 | /** |
| 233 | * sandbox_set_enable_memio() - Enable readl/writel() for sandbox |
| 234 | * |
| 235 | * Normally these I/O functions do nothing with sandbox. Certain tests need them |
| 236 | * to work as for other architectures, so this function can be used to enable |
| 237 | * them. |
| 238 | * |
| 239 | * @enable: true to enable, false to disable |
| 240 | */ |
| 241 | void sandbox_set_enable_memio(bool enable); |
| 242 | |
Simon Glass | 6ec1b75 | 2014-12-10 08:55:51 -0700 | [diff] [blame] | 243 | #endif |