blob: 006fe8281c5bd1a691b39a2ad0adde1e89a9757a [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasutec33de32011-11-08 23:18:14 +00002/*
3 * Freescale i.MX28 SPI driver
4 *
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
7 *
Marek Vasutec33de32011-11-08 23:18:14 +00008 * NOTE: This driver only supports the SPI-controller chipselects,
9 * GPIO driven chipselects are not supported.
10 */
11
12#include <common.h>
13#include <malloc.h>
Simon Glasscf92e052015-09-02 17:24:58 -060014#include <memalign.h>
Marek Vasutec33de32011-11-08 23:18:14 +000015#include <spi.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090016#include <linux/errno.h>
Marek Vasutec33de32011-11-08 23:18:14 +000017#include <asm/io.h>
18#include <asm/arch/clock.h>
19#include <asm/arch/imx-regs.h>
20#include <asm/arch/sys_proto.h>
Stefano Babic552a8482017-06-29 10:16:06 +020021#include <asm/mach-imx/dma.h>
Marek Vasutec33de32011-11-08 23:18:14 +000022
23#define MXS_SPI_MAX_TIMEOUT 1000000
24#define MXS_SPI_PORT_OFFSET 0x2000
Fabio Estevam148ca642012-04-23 08:30:50 +000025#define MXS_SSP_CHIPSELECT_MASK 0x00300000
26#define MXS_SSP_CHIPSELECT_SHIFT 20
Marek Vasutec33de32011-11-08 23:18:14 +000027
Marek Vasut7c5e6f72012-07-09 00:48:33 +000028#define MXSSSP_SMALL_TRANSFER 512
29
Marek Vasutec33de32011-11-08 23:18:14 +000030struct mxs_spi_slave {
31 struct spi_slave slave;
32 uint32_t max_khz;
33 uint32_t mode;
Otavio Salvador9c471142012-08-05 09:05:31 +000034 struct mxs_ssp_regs *regs;
Marek Vasutec33de32011-11-08 23:18:14 +000035};
36
37static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
38{
39 return container_of(slave, struct mxs_spi_slave, slave);
40}
41
42void spi_init(void)
43{
44}
45
Fabio Estevam79cb14a2012-04-23 08:30:49 +000046int spi_cs_is_valid(unsigned int bus, unsigned int cs)
47{
48 /* MXS SPI: 4 ports and 3 chip selects maximum */
Marek Vasut3430e0b2013-02-23 02:42:58 +000049 if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
Fabio Estevam79cb14a2012-04-23 08:30:49 +000050 return 0;
51 else
52 return 1;
53}
54
Marek Vasutec33de32011-11-08 23:18:14 +000055struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
56 unsigned int max_hz, unsigned int mode)
57{
58 struct mxs_spi_slave *mxs_slave;
Marek Vasutec33de32011-11-08 23:18:14 +000059
Fabio Estevam79cb14a2012-04-23 08:30:49 +000060 if (!spi_cs_is_valid(bus, cs)) {
61 printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
Marek Vasutec33de32011-11-08 23:18:14 +000062 return NULL;
63 }
64
Simon Glassd3504fe2013-03-18 19:23:40 +000065 mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
Marek Vasutec33de32011-11-08 23:18:14 +000066 if (!mxs_slave)
67 return NULL;
68
Marek Vasut3430e0b2013-02-23 02:42:58 +000069 if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
Marek Vasut7c5e6f72012-07-09 00:48:33 +000070 goto err_init;
71
Marek Vasutec33de32011-11-08 23:18:14 +000072 mxs_slave->max_khz = max_hz / 1000;
73 mxs_slave->mode = mode;
Marek Vasut14e26bc2013-01-11 03:19:02 +000074 mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
Marek Vasutec33de32011-11-08 23:18:14 +000075
76 return &mxs_slave->slave;
Marek Vasut7c5e6f72012-07-09 00:48:33 +000077
78err_init:
Marek Vasut7c5e6f72012-07-09 00:48:33 +000079 free(mxs_slave);
80 return NULL;
Marek Vasutec33de32011-11-08 23:18:14 +000081}
82
83void spi_free_slave(struct spi_slave *slave)
84{
85 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
86 free(mxs_slave);
87}
88
89int spi_claim_bus(struct spi_slave *slave)
90{
91 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
Otavio Salvador9c471142012-08-05 09:05:31 +000092 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
Marek Vasutec33de32011-11-08 23:18:14 +000093 uint32_t reg = 0;
94
Otavio Salvadorfa7a51c2012-08-13 09:53:12 +000095 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
Marek Vasutec33de32011-11-08 23:18:14 +000096
Marek Vasuta928a362013-08-26 17:45:23 +020097 writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
98 SSP_CTRL0_BUS_WIDTH_ONE_BIT,
99 &ssp_regs->hw_ssp_ctrl0);
Marek Vasutec33de32011-11-08 23:18:14 +0000100
101 reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
102 reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
103 reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
104 writel(reg, &ssp_regs->hw_ssp_ctrl1);
105
106 writel(0, &ssp_regs->hw_ssp_cmd0);
107
Otavio Salvadorbf48fcb2013-01-11 03:19:03 +0000108 mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
Marek Vasutec33de32011-11-08 23:18:14 +0000109
110 return 0;
111}
112
113void spi_release_bus(struct spi_slave *slave)
114{
115}
116
Otavio Salvador9c471142012-08-05 09:05:31 +0000117static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
Marek Vasutec33de32011-11-08 23:18:14 +0000118{
119 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
120 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
121}
122
Otavio Salvador9c471142012-08-05 09:05:31 +0000123static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
Marek Vasutec33de32011-11-08 23:18:14 +0000124{
125 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
126 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
127}
128
Marek Vasutccd4d5a2012-07-09 00:48:32 +0000129static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
130 char *data, int length, int write, unsigned long flags)
Marek Vasutec33de32011-11-08 23:18:14 +0000131{
Otavio Salvador9c471142012-08-05 09:05:31 +0000132 struct mxs_ssp_regs *ssp_regs = slave->regs;
Marek Vasutc7065fa2012-07-09 00:48:31 +0000133
Marek Vasutec33de32011-11-08 23:18:14 +0000134 if (flags & SPI_XFER_BEGIN)
135 mxs_spi_start_xfer(ssp_regs);
136
Marek Vasutccd4d5a2012-07-09 00:48:32 +0000137 while (length--) {
Marek Vasutec33de32011-11-08 23:18:14 +0000138 /* We transfer 1 byte */
Marek Vasutc96e78c2013-02-23 02:42:59 +0000139#if defined(CONFIG_MX23)
140 writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
141 writel(1, &ssp_regs->hw_ssp_ctrl0_set);
142#elif defined(CONFIG_MX28)
Marek Vasutec33de32011-11-08 23:18:14 +0000143 writel(1, &ssp_regs->hw_ssp_xfer_size);
Marek Vasutc96e78c2013-02-23 02:42:59 +0000144#endif
Marek Vasutec33de32011-11-08 23:18:14 +0000145
Marek Vasutccd4d5a2012-07-09 00:48:32 +0000146 if ((flags & SPI_XFER_END) && !length)
Marek Vasutec33de32011-11-08 23:18:14 +0000147 mxs_spi_end_xfer(ssp_regs);
148
Marek Vasutc7065fa2012-07-09 00:48:31 +0000149 if (write)
Marek Vasutec33de32011-11-08 23:18:14 +0000150 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
151 else
152 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
153
154 writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
155
Otavio Salvadorfa7a51c2012-08-13 09:53:12 +0000156 if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
Marek Vasutec33de32011-11-08 23:18:14 +0000157 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
158 printf("MXS SPI: Timeout waiting for start\n");
Fabio Estevamd9fb6a42012-03-18 17:23:35 +0000159 return -ETIMEDOUT;
Marek Vasutec33de32011-11-08 23:18:14 +0000160 }
161
Marek Vasutc7065fa2012-07-09 00:48:31 +0000162 if (write)
163 writel(*data++, &ssp_regs->hw_ssp_data);
Marek Vasutec33de32011-11-08 23:18:14 +0000164
165 writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
166
Marek Vasutc7065fa2012-07-09 00:48:31 +0000167 if (!write) {
Otavio Salvadorfa7a51c2012-08-13 09:53:12 +0000168 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
Marek Vasutec33de32011-11-08 23:18:14 +0000169 SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
170 printf("MXS SPI: Timeout waiting for data\n");
Fabio Estevamd9fb6a42012-03-18 17:23:35 +0000171 return -ETIMEDOUT;
Marek Vasutec33de32011-11-08 23:18:14 +0000172 }
173
Marek Vasutc7065fa2012-07-09 00:48:31 +0000174 *data = readl(&ssp_regs->hw_ssp_data);
175 data++;
Marek Vasutec33de32011-11-08 23:18:14 +0000176 }
177
Otavio Salvadorfa7a51c2012-08-13 09:53:12 +0000178 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
Marek Vasutec33de32011-11-08 23:18:14 +0000179 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
180 printf("MXS SPI: Timeout waiting for finish\n");
Fabio Estevamd9fb6a42012-03-18 17:23:35 +0000181 return -ETIMEDOUT;
Marek Vasutec33de32011-11-08 23:18:14 +0000182 }
183 }
184
185 return 0;
Marek Vasutccd4d5a2012-07-09 00:48:32 +0000186}
187
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000188static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
189 char *data, int length, int write, unsigned long flags)
190{
Marek Vasut2c432142012-08-21 16:17:27 +0000191 const int xfer_max_sz = 0xff00;
192 const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
Otavio Salvador9c471142012-08-05 09:05:31 +0000193 struct mxs_ssp_regs *ssp_regs = slave->regs;
Marek Vasut2c432142012-08-21 16:17:27 +0000194 struct mxs_dma_desc *dp;
195 uint32_t ctrl0;
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000196 uint32_t cache_data_count;
Marek Vasut88d15552012-08-31 16:07:59 +0000197 const uint32_t dstart = (uint32_t)data;
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000198 int dmach;
Marek Vasut2c432142012-08-21 16:17:27 +0000199 int tl;
Marek Vasute9f7eaf2012-08-31 16:08:00 +0000200 int ret = 0;
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000201
Marek Vasutc96e78c2013-02-23 02:42:59 +0000202#if defined(CONFIG_MX23)
203 const int mxs_spi_pio_words = 1;
204#elif defined(CONFIG_MX28)
205 const int mxs_spi_pio_words = 4;
206#endif
207
Marek Vasut2c432142012-08-21 16:17:27 +0000208 ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
209
210 memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
211
212 ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
213 ctrl0 |= SSP_CTRL0_DATA_XFER;
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000214
215 if (flags & SPI_XFER_BEGIN)
216 ctrl0 |= SSP_CTRL0_LOCK_CS;
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000217 if (!write)
218 ctrl0 |= SSP_CTRL0_READ;
219
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000220 if (length % ARCH_DMA_MINALIGN)
221 cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
222 else
223 cache_data_count = length;
224
Marek Vasut88d15552012-08-31 16:07:59 +0000225 /* Flush data to DRAM so DMA can pick them up */
Marek Vasut2c432142012-08-21 16:17:27 +0000226 if (write)
Marek Vasut88d15552012-08-31 16:07:59 +0000227 flush_dcache_range(dstart, dstart + cache_data_count);
228
229 /* Invalidate the area, so no writeback into the RAM races with DMA */
230 invalidate_dcache_range(dstart, dstart + cache_data_count);
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000231
232 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
Marek Vasut2c432142012-08-21 16:17:27 +0000233
234 dp = desc;
235 while (length) {
236 dp->address = (dma_addr_t)dp;
237 dp->cmd.address = (dma_addr_t)data;
238
239 /*
240 * This is correct, even though it does indeed look insane.
241 * I hereby have to, wholeheartedly, thank Freescale Inc.,
242 * for always inventing insane hardware and keeping me busy
243 * and employed ;-)
244 */
245 if (write)
246 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
247 else
248 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
249
250 /*
251 * The DMA controller can transfer large chunks (64kB) at
252 * time by setting the transfer length to 0. Setting tl to
253 * 0x10000 will overflow below and make .data contain 0.
254 * Otherwise, 0xff00 is the transfer maximum.
255 */
256 if (length >= 0x10000)
257 tl = 0x10000;
258 else
259 tl = min(length, xfer_max_sz);
260
261 dp->cmd.data |=
Marek Vasute9f7eaf2012-08-31 16:08:00 +0000262 ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
Marek Vasutc96e78c2013-02-23 02:42:59 +0000263 (mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
Marek Vasut2c432142012-08-21 16:17:27 +0000264 MXS_DMA_DESC_HALT_ON_TERMINATE |
265 MXS_DMA_DESC_TERMINATE_FLUSH;
Marek Vasut2c432142012-08-21 16:17:27 +0000266
267 data += tl;
268 length -= tl;
269
Marek Vasute9f7eaf2012-08-31 16:08:00 +0000270 if (!length) {
271 dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
272
273 if (flags & SPI_XFER_END) {
274 ctrl0 &= ~SSP_CTRL0_LOCK_CS;
275 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
276 }
277 }
278
279 /*
Marek Vasutc96e78c2013-02-23 02:42:59 +0000280 * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
281 * case of MX28, write only CTRL0 in case of MX23 due
282 * to the difference in register layout. It is utterly
Marek Vasute9f7eaf2012-08-31 16:08:00 +0000283 * essential that the XFER_SIZE register is written on
284 * a per-descriptor basis with the same size as is the
285 * descriptor!
286 */
287 dp->cmd.pio_words[0] = ctrl0;
Marek Vasutc96e78c2013-02-23 02:42:59 +0000288#ifdef CONFIG_MX28
Marek Vasute9f7eaf2012-08-31 16:08:00 +0000289 dp->cmd.pio_words[1] = 0;
290 dp->cmd.pio_words[2] = 0;
291 dp->cmd.pio_words[3] = tl;
Marek Vasutc96e78c2013-02-23 02:42:59 +0000292#endif
Marek Vasute9f7eaf2012-08-31 16:08:00 +0000293
Marek Vasut2c432142012-08-21 16:17:27 +0000294 mxs_dma_desc_append(dmach, dp);
295
296 dp++;
297 }
298
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000299 if (mxs_dma_go(dmach))
Marek Vasute9f7eaf2012-08-31 16:08:00 +0000300 ret = -EINVAL;
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000301
302 /* The data arrived into DRAM, invalidate cache over them */
Marek Vasut88d15552012-08-31 16:07:59 +0000303 if (!write)
304 invalidate_dcache_range(dstart, dstart + cache_data_count);
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000305
Marek Vasute9f7eaf2012-08-31 16:08:00 +0000306 return ret;
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000307}
308
Marek Vasutccd4d5a2012-07-09 00:48:32 +0000309int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
310 const void *dout, void *din, unsigned long flags)
311{
312 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
Otavio Salvador9c471142012-08-05 09:05:31 +0000313 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
Marek Vasutccd4d5a2012-07-09 00:48:32 +0000314 int len = bitlen / 8;
315 char dummy;
316 int write = 0;
317 char *data = NULL;
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000318 int dma = 1;
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000319
Marek Vasutccd4d5a2012-07-09 00:48:32 +0000320 if (bitlen == 0) {
321 if (flags & SPI_XFER_END) {
322 din = (void *)&dummy;
323 len = 1;
324 } else
325 return 0;
326 }
327
328 /* Half-duplex only */
329 if (din && dout)
330 return -EINVAL;
331 /* No data */
332 if (!din && !dout)
333 return 0;
334
335 if (dout) {
336 data = (char *)dout;
337 write = 1;
338 } else if (din) {
339 data = (char *)din;
340 write = 0;
341 }
342
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000343 /*
344 * Check for alignment, if the buffer is aligned, do DMA transfer,
345 * PIO otherwise. This is a temporary workaround until proper bounce
346 * buffer is in place.
347 */
348 if (dma) {
349 if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
350 dma = 0;
351 if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
352 dma = 0;
353 }
354
355 if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
356 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
357 return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
358 } else {
359 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
360 return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
361 }
Marek Vasutec33de32011-11-08 23:18:14 +0000362}