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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 6ca8646c1860bba74326bf916a5a3389a5c0d3b5 / . / board / amcc / yucca / init.S
blob: 67e8f8f3a2c53bc1c5432555b479c3fcb16f6c44 [file] [log] [blame]
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]1/*
Stefan Roese2f5df472007-03-08 10:10:18 +0100[diff] [blame]2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]5 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]25
26#include <ppc_asm.tmpl>
27#include <config.h>
Stefan Roese2f5df472007-03-08 10:10:18 +0100[diff] [blame]28#include <asm-ppc/mmu.h>
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]29
30/**************************************************************************
31 * TLB TABLE
32 *
33 * This table is used by the cpu boot code to setup the initial tlb
34 * entries. Rather than make broad assumptions in the cpu source tree,
35 * this table lets each board set things up however they like.
36 *
37 * Pointer to the table is returned in r1
38 *
39 *************************************************************************/
40
41 .section .bootpg,"ax"
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]42
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200[diff] [blame]43/**************************************************************************
44 * TLB table for revA
45 *************************************************************************/
46 .globl tlbtabA
47tlbtabA:
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]48 tlbtab_start
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]49
Stefan Roese2f5df472007-03-08 10:10:18 +0100[diff] [blame]50 /*
51 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
52 * speed up boot process. It is patched after relocation to enable SA_I
53 */
54 tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
55
56 /*
57 * TLB entries for SDRAM are not needed on this platform.
58 * They are dynamically generated in the SPD DDR(2) detection
59 * routine.
60 */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]61
62 tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200[diff] [blame]63 tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]64
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200[diff] [blame]65 tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]66 tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
67
68 tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
69 tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200[diff] [blame]70 tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
Rafal Jaworowski36b904a2006-08-11 12:35:52 +0200[diff] [blame]71 tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200[diff] [blame]72
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200[diff] [blame]73 tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
74 tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
75 tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
Rafal Jaworowski36b904a2006-08-11 12:35:52 +0200[diff] [blame]76 tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
77 tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
78 tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]79 tlbtab_end
80
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200[diff] [blame]81/**************************************************************************
82 * TLB table for revB
83 *
Wolfgang Denkd10afb32006-08-10 15:40:49 +0200[diff] [blame]84 * Notice: revB of the 440SPe chip is very strict about PLB real addresses
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200[diff] [blame]85 * and ranges to be mapped for config space: it seems to only work with
86 * d_nnnn_nnnn range (hangs the core upon config transaction attempts when
87 * set otherwise) while revA uses c_nnnn_nnnn.
88 *************************************************************************/
89 .globl tlbtabB
90tlbtabB:
91 tlbtab_start
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200[diff] [blame]92
Stefan Roese2f5df472007-03-08 10:10:18 +0100[diff] [blame]93 /*
94 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
95 * speed up boot process. It is patched after relocation to enable SA_I
96 */
97 tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
98
99 /*
100 * TLB entries for SDRAM are not needed on this platform.
101 * They are dynamically generated in the SPD DDR(2) detection
102 * routine.
103 */
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200[diff] [blame]104
105 tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
106 tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
107
108 tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
109 tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
110
111 tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
112 tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
113 tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
114
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200[diff] [blame]115 tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
116 tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
117 tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200[diff] [blame]118 tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
119 tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
120 tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]121 tlbtab_end