blob: 1b05b8058a51e9f3031961c0a669f6c4daad1944 [file] [log] [blame]
wdenk43d96162003-03-06 00:02:04 +00001/*
2 * (C) Copyright 2000, 2001, 2002
3 * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
4 *
5 * Configuration for the Auerswald Innokom CPU board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * include/configs/innokom.h - configuration options, board specific
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
wdenk43d96162003-03-06 00:02:04 +000033/*
wdenk43d96162003-03-06 00:02:04 +000034 * High Level Configuration Options
35 * (easy to change)
36 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020037#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
wdenk43d96162003-03-06 00:02:04 +000038#define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */
39
40#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
41 /* for timer/console/ethernet */
42/*
43 * Hardware drivers
44 */
45
46/*
47 * select serial console configuration
48 */
49#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
50
51/* allow to overwrite serial and ethaddr */
52#define CONFIG_ENV_OVERWRITE
53
54#define CONFIG_BAUDRATE 19200
wdenk06d01db2003-03-14 20:47:52 +000055#define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */
wdenk43d96162003-03-06 00:02:04 +000056
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -050057
58/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050059 * BOOTP options
60 */
61#define CONFIG_BOOTP_BOOTFILESIZE
62#define CONFIG_BOOTP_BOOTPATH
63#define CONFIG_BOOTP_GATEWAY
64#define CONFIG_BOOTP_HOSTNAME
65
66
67/*
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -050068 * Command line configuration.
69 */
70
71#define CONFIG_CMD_ASKENV
72#define CONFIG_CMD_BDI
73#define CONFIG_CMD_CACHE
74#define CONFIG_CMD_DHCP
75#define CONFIG_CMD_ECHO
76#define CONFIG_CMD_ENV
77#define CONFIG_CMD_FLASH
78#define CONFIG_CMD_I2C
79#define CONFIG_CMD_IMI
80#define CONFIG_CMD_LOADB
81#define CONFIG_CMD_MEMORY
82#define CONFIG_CMD_NET
83#define CONFIG_CMD_RUN
84
wdenk43d96162003-03-06 00:02:04 +000085
86#define CONFIG_BOOTDELAY 3
87/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
88#define CONFIG_BOOTARGS "console=ttyS0,19200"
89#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
90#define CONFIG_NETMASK 255.255.255.0
91#define CONFIG_IPADDR 192.168.1.56
92#define CONFIG_SERVERIP 192.168.1.2
93#define CONFIG_BOOTCOMMAND "bootm 0x40000"
94#define CONFIG_SHOW_BOOT_PROGRESS
95
96#define CONFIG_CMDLINE_TAG 1
97
wdenk43d96162003-03-06 00:02:04 +000098/*
99 * Miscellaneous configurable options
100 */
101
102/*
wdenkf6e20fc2004-02-08 19:38:38 +0000103 * Size of malloc() pool
wdenk43d96162003-03-06 00:02:04 +0000104 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_MALLOC_LEN (256*1024)
106#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenk43d96162003-03-06 00:02:04 +0000107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_LONGHELP /* undef to save memory */
109#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
110#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
111#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
112#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
113#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk43d96162003-03-06 00:02:04 +0000114
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
116#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
wdenk43d96162003-03-06 00:02:04 +0000117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
wdenk43d96162003-03-06 00:02:04 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* load kernel to this address */
wdenk43d96162003-03-06 00:02:04 +0000121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
wdenk43d96162003-03-06 00:02:04 +0000123 /* RS: the oscillator is actually 3680130?? */
124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
wdenk43d96162003-03-06 00:02:04 +0000126 /* 0101000001 */
127 /* ^^^^^ Memory Speed 99.53 MHz */
128 /* ^^ Run Mode Speed = 2x Mem Speed */
129 /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */
wdenk43d96162003-03-06 00:02:04 +0000132
wdenk8bde7f72003-06-27 21:31:46 +0000133 /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk43d96162003-03-06 00:02:04 +0000135
136/*
137 * I2C bus
138 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200139#define CONFIG_HARD_I2C 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_I2C_SPEED 50000
141#define CONFIG_SYS_I2C_SLAVE 0xfe
wdenk43d96162003-03-06 00:02:04 +0000142
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200143#define CONFIG_ENV_IS_IN_EEPROM 1
wdenk43d96162003-03-06 00:02:04 +0000144
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200145#define CONFIG_ENV_OFFSET 0x00 /* environment starts here */
146#define CONFIG_ENV_SIZE 1024 /* 1 KiB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */
148#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
149#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */
150#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* length of address */
151#define CONFIG_SYS_EEPROM_SIZE 4096 /* size in bytes */
152#define CONFIG_SYS_I2C_INIT_BOARD 1 /* board has it's own init */
wdenk06d01db2003-03-14 20:47:52 +0000153
154/*
155 * SMSC91C111 Network Card
156 */
157#define CONFIG_DRIVER_SMC91111 1
158#define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */
159#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
160#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
wdenkf39748a2004-06-09 13:37:52 +0000161#define CONFIG_SMC_AUTONEG_TIMEOUT 10 /* timeout 10 seconds */
wdenk06d01db2003-03-14 20:47:52 +0000162#undef CONFIG_SHOW_ACTIVITY
163#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
wdenk43d96162003-03-06 00:02:04 +0000164
165/*
166 * Stack sizes
167 *
168 * The stack sizes are set up in start.S using the settings below
169 */
170#define CONFIG_STACKSIZE (128*1024) /* regular stack */
171#ifdef CONFIG_USE_IRQ
172#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
173#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
174#endif
175
176/*
177 * Physical Memory Map
178 */
179#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
180#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
181#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
182
183#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
184#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* RAM starts here */
187#define CONFIG_SYS_DRAM_SIZE 0x04000000
wdenk43d96162003-03-06 00:02:04 +0000188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenk43d96162003-03-06 00:02:04 +0000190
wdenk06d01db2003-03-14 20:47:52 +0000191/*
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200192 * JFFS2 partitions
193 *
wdenk06d01db2003-03-14 20:47:52 +0000194 */
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200195/* development flash */
196#define CONFIG_MTD_INNOKOM_16MB 1
197#undef CONFIG_MTD_INNOKOM_64MB
wdenk06d01db2003-03-14 20:47:52 +0000198
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200199/* production flash */
200/*
201#define CONFIG_MTD_INNOKOM_64MB 1
202#undef CONFIG_MTD_INNOKOM_16MB
203*/
204
205/* No command line, one static partition, whole device */
206#undef CONFIG_JFFS2_CMDLINE
207#define CONFIG_JFFS2_DEV "nor0"
208#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
209#define CONFIG_JFFS2_PART_OFFSET 0x00000000
210
211/* mtdparts command line support */
212/* Note: fake mtd_id used, no linux mtd map file */
213/*
214#define CONFIG_JFFS2_CMDLINE
215#define MTDIDS_DEFAULT "nor0=innokom-0"
216*/
217
218/* development flash */
219/*
220#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)"
221*/
222
223/* production flash */
224/*
225#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)"
226*/
wdenk06d01db2003-03-14 20:47:52 +0000227
228/*
wdenk3e386912003-04-05 00:53:31 +0000229 * GPIO settings
wdenk06d01db2003-03-14 20:47:52 +0000230 *
231 * GP15 == nCS1 is 1
wdenk43d96162003-03-06 00:02:04 +0000232 * GP24 == SFRM is 1
233 * GP25 == TXD is 1
234 * GP33 == nCS5 is 1
235 * GP39 == FFTXD is 1
236 * GP41 == RTS is 1
237 * GP47 == TXD is 1
238 * GP49 == nPWE is 1
239 * GP62 == LED_B is 1
240 * GP63 == TDM_OE is 1
241 * GP78 == nCS2 is 1
242 * GP79 == nCS3 is 1
243 * GP80 == nCS4 is 1
244 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_GPSR0_VAL 0x03008000
246#define CONFIG_SYS_GPSR1_VAL 0xC0028282
247#define CONFIG_SYS_GPSR2_VAL 0x0001C000
wdenk43d96162003-03-06 00:02:04 +0000248
249/* GP02 == DON_RST is 0
250 * GP23 == SCLK is 0
251 * GP45 == USB_ACT is 0
252 * GP60 == PLLEN is 0
253 * GP61 == LED_A is 0
254 * GP73 == SWUPD_LED is 0
255 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_GPCR0_VAL 0x00800004
257#define CONFIG_SYS_GPCR1_VAL 0x30002000
258#define CONFIG_SYS_GPCR2_VAL 0x00000100
wdenk43d96162003-03-06 00:02:04 +0000259
260/* GP00 == DON_READY is input
261 * GP01 == DON_OK is input
262 * GP02 == DON_RST is output
263 * GP03 == RESET_IND is input
264 * GP07 == RES11 is input
265 * GP09 == RES12 is input
266 * GP11 == SWUPDATE is input
267 * GP14 == nPOWEROK is input
268 * GP15 == nCS1 is output
269 * GP17 == RES22 is input
270 * GP18 == RDY is input
271 * GP23 == SCLK is output
272 * GP24 == SFRM is output
273 * GP25 == TXD is output
274 * GP26 == RXD is input
275 * GP32 == RES21 is input
276 * GP33 == nCS5 is output
277 * GP34 == FFRXD is input
278 * GP35 == CTS is input
279 * GP39 == FFTXD is output
280 * GP41 == RTS is output
281 * GP42 == USB_OK is input
282 * GP45 == USB_ACT is output
283 * GP46 == RXD is input
284 * GP47 == TXD is output
285 * GP49 == nPWE is output
286 * GP58 == nCPUBUSINT is input
287 * GP59 == LANINT is input
288 * GP60 == PLLEN is output
289 * GP61 == LED_A is output
290 * GP62 == LED_B is output
291 * GP63 == TDM_OE is output
292 * GP64 == nDSPINT is input
293 * GP65 == STRAP0 is input
294 * GP67 == STRAP1 is input
295 * GP69 == STRAP2 is input
296 * GP70 == STRAP3 is input
297 * GP71 == STRAP4 is input
298 * GP73 == SWUPD_LED is output
299 * GP78 == nCS2 is output
300 * GP79 == nCS3 is output
301 * GP80 == nCS4 is output
302 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_GPDR0_VAL 0x03808004
304#define CONFIG_SYS_GPDR1_VAL 0xF002A282
305#define CONFIG_SYS_GPDR2_VAL 0x0001C200
wdenk43d96162003-03-06 00:02:04 +0000306
307/* GP15 == nCS1 is AF10
308 * GP18 == RDY is AF01
309 * GP23 == SCLK is AF10
310 * GP24 == SFRM is AF10
311 * GP25 == TXD is AF10
312 * GP26 == RXD is AF01
313 * GP33 == nCS5 is AF10
314 * GP34 == FFRXD is AF01
315 * GP35 == CTS is AF01
316 * GP39 == FFTXD is AF10
317 * GP41 == RTS is AF10
318 * GP46 == RXD is AF10
319 * GP47 == TXD is AF01
320 * GP49 == nPWE is AF10
321 * GP78 == nCS2 is AF10
322 * GP79 == nCS3 is AF10
323 * GP80 == nCS4 is AF10
324 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
326#define CONFIG_SYS_GAFR0_U_VAL 0x001A8010
327#define CONFIG_SYS_GAFR1_L_VAL 0x60088058
328#define CONFIG_SYS_GAFR1_U_VAL 0x00000008
329#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
330#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
wdenk43d96162003-03-06 00:02:04 +0000331
wdenk06d01db2003-03-14 20:47:52 +0000332
wdenk43d96162003-03-06 00:02:04 +0000333/* FIXME: set GPIO_RER/FER */
334
335/* RDH = 1
336 * PH = 1
337 * VFS = 1
338 * BFS = 1
339 * SSS = 1
340 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_PSSR_VAL 0x37
wdenk43d96162003-03-06 00:02:04 +0000342
343/*
344 * Memory settings
wdenk06d01db2003-03-14 20:47:52 +0000345 *
346 * This is the configuration for nCS0/1 -> flash banks
wdenk43d96162003-03-06 00:02:04 +0000347 * configuration for nCS1:
348 * [31] 0 - Slower Device
349 * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
350 * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
351 * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
352 * [19] 1 - 16 Bit bus width
353 * [18:16] 000 - nonburst RAM or FLASH
354 * configuration for nCS0:
355 * [15] 0 - Slower Device
356 * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
357 * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
358 * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
359 * [03] 1 - 16 Bit bus width
360 * [02:00] 000 - nonburst RAM or FLASH
361 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_MSC0_VAL 0x25b825b8 /* flash banks */
wdenk43d96162003-03-06 00:02:04 +0000363
364/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
365 * configuration for nCS3: DSP
366 * [31] 0 - Slower Device
367 * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
368 * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
369 * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
370 * [19] 1 - 16 Bit bus width
371 * [18:16] 100 - variable latency I/O
372 * configuration for nCS2: TDM-Switch
373 * [15] 0 - Slower Device
374 * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
375 * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
376 * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
377 * [03] 1 - 16 Bit bus width
378 * [02:00] 100 - variable latency I/O
379 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_MSC1_VAL 0x123C593C /* TDM switch, DSP */
wdenk43d96162003-03-06 00:02:04 +0000381
382/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
383 *
384 * configuration for nCS5: LAN Controller
385 * [31] 0 - Slower Device
386 * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
387 * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
388 * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
389 * [19] 1 - 16 Bit bus width
390 * [18:16] 100 - variable latency I/O
391 * configuration for nCS4: ExtBus
392 * [15] 0 - Slower Device
393 * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
394 * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
395 * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
396 * [03] 1 - 16 Bit bus width
397 * [02:00] 100 - variable latency I/O
398 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */
wdenk43d96162003-03-06 00:02:04 +0000400
401/* MDCNFG: SDRAM Configuration Register
402 *
403 * [31:29] 000 - reserved
404 * [28] 0 - no SA1111 compatiblity mode
405 * [27] 0 - latch return data with return clock
406 * [26] 0 - alternate addressing for pair 2/3
407 * [25:24] 00 - timings
408 * [23] 0 - internal banks in lower partition 2/3 (not used)
409 * [22:21] 00 - row address bits for partition 2/3 (not used)
410 * [20:19] 00 - column address bits for partition 2/3 (not used)
411 * [18] 0 - SDRAM partition 2/3 width is 32 bit
412 * [17] 0 - SDRAM partition 3 disabled
413 * [16] 0 - SDRAM partition 2 disabled
414 * [15:13] 000 - reserved
415 * [12] 1 - SA1111 compatiblity mode
416 * [11] 1 - latch return data with return clock
417 * [10] 0 - no alternate addressing for pair 0/1
wdenk06d01db2003-03-14 20:47:52 +0000418 * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
wdenk43d96162003-03-06 00:02:04 +0000419 * [7] 1 - 4 internal banks in lower partition pair
420 * [06:05] 10 - 13 row address bits for partition 0/1
421 * [04:03] 01 - 9 column address bits for partition 0/1
422 * [02] 0 - SDRAM partition 0/1 width is 32 bit
423 * [01] 0 - disable SDRAM partition 1
424 * [00] 1 - enable SDRAM partition 0
wdenk43d96162003-03-06 00:02:04 +0000425 */
wdenk06d01db2003-03-14 20:47:52 +0000426/* use the configuration above but disable partition 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_MDCNFG_VAL 0x000019c8
wdenk43d96162003-03-06 00:02:04 +0000428
429/* MDREFR: SDRAM Refresh Control Register
430 *
431 * [32:26] 0 - reserved
432 * [25] 0 - K2FREE: not free running
433 * [24] 0 - K1FREE: not free running
wdenk3e386912003-04-05 00:53:31 +0000434 * [23] 1 - K0FREE: not free running
wdenk43d96162003-03-06 00:02:04 +0000435 * [22] 0 - SLFRSH: self refresh disabled
436 * [21] 0 - reserved
437 * [20] 0 - APD: no auto power down
438 * [19] 0 - K2DB2: SDCLK2 is MemClk
439 * [18] 0 - K2RUN: disable SDCLK2
440 * [17] 0 - K1DB2: SDCLK1 is MemClk
441 * [16] 1 - K1RUN: enable SDCLK1
442 * [15] 1 - E1PIN: SDRAM clock enable
443 * [14] 1 - K0DB2: SDCLK0 is MemClk
wdenk3e386912003-04-05 00:53:31 +0000444 * [13] 0 - K0RUN: disable SDCLK0
wdenk43d96162003-03-06 00:02:04 +0000445 * [12] 1 - E0PIN: disable SDCKE0
446 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
447 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_MDREFR_VAL 0x0081D018
wdenk43d96162003-03-06 00:02:04 +0000449
450/* MDMRS: Mode Register Set Configuration Register
451 *
452 * [31] 0 - reserved
453 * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
454 * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
455 * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
456 * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
457 * [15] 0 - reserved
458 * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
459 * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
460 * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
461 * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
462 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#define CONFIG_SYS_MDMRS_VAL 0x00020022
wdenk43d96162003-03-06 00:02:04 +0000464
465/*
466 * PCMCIA and CF Interfaces
467 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_MECR_VAL 0x00000000
469#define CONFIG_SYS_MCMEM0_VAL 0x00000000
470#define CONFIG_SYS_MCMEM1_VAL 0x00000000
471#define CONFIG_SYS_MCATT0_VAL 0x00000000
472#define CONFIG_SYS_MCATT1_VAL 0x00000000
473#define CONFIG_SYS_MCIO0_VAL 0x00000000
474#define CONFIG_SYS_MCIO1_VAL 0x00000000
wdenk43d96162003-03-06 00:02:04 +0000475
476/*
477#define CSB226_USER_LED0 0x00000008
478#define CSB226_USER_LED1 0x00000010
479#define CSB226_USER_LED2 0x00000020
480*/
481
482/*
483 * FLASH and environment organization
484 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
486#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
wdenk43d96162003-03-06 00:02:04 +0000487
488/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
490#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk43d96162003-03-06 00:02:04 +0000491
wdenk43d96162003-03-06 00:02:04 +0000492#endif /* __CONFIG_H */