blob: 696ac88c3fdc8896c9553cc202603d7f12aca1f8 [file] [log] [blame]
Peter Tyser1f03cbf2008-12-23 16:32:00 -06001/*
2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2004-2008 Freescale Semiconductor, Inc.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Peter Tyser1f03cbf2008-12-23 16:32:00 -06006 */
7
8/*
Peter Tyserc00ac252010-10-22 00:20:26 -05009 * xpedite520x board configuration file
Peter Tyser1f03cbf2008-12-23 16:32:00 -060010 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * High Level Configuration Options
16 */
Peter Tyser1f03cbf2008-12-23 16:32:00 -060017#define CONFIG_XPEDITE5200 1
18#define CONFIG_SYS_BOARD_NAME "XPedite5200"
John Schmoller92af65492010-10-22 00:20:24 -050019#define CONFIG_SYS_FORM_PMC_XMC 1
Peter Tyser1f03cbf2008-12-23 16:32:00 -060020#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
Peter Tyser1f03cbf2008-12-23 16:32:00 -060021
Wolfgang Denk2ae18242010-10-06 09:05:45 +020022#ifndef CONFIG_SYS_TEXT_BASE
23#define CONFIG_SYS_TEXT_BASE 0xfff80000
24#endif
25
Peter Tyser1f03cbf2008-12-23 16:32:00 -060026#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
27#define CONFIG_PCI1 1 /* PCI controller 1 */
28#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000029#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Peter Tyser1f03cbf2008-12-23 16:32:00 -060030#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Peter Tyser1f03cbf2008-12-23 16:32:00 -060031
32/*
33 * DDR config
34 */
Peter Tyser1f03cbf2008-12-23 16:32:00 -060035#undef CONFIG_FSL_DDR_INTERACTIVE
36#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
37#define CONFIG_DDR_SPD
38#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
39#define SPD_EEPROM_ADDRESS 0x54
Peter Tyser1f03cbf2008-12-23 16:32:00 -060040#define CONFIG_DIMM_SLOTS_PER_CTLR 1
41#define CONFIG_CHIP_SELECTS_PER_CTRL 2
42#define CONFIG_DDR_ECC
43#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
44#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
45#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
46#define CONFIG_VERY_BIG_RAM
47
48#define CONFIG_SYS_CLK_FREQ 66666666
49
50/*
51 * These can be toggled for performance analysis, otherwise use default.
52 */
53#define CONFIG_L2_CACHE /* toggle L2 cache */
54#define CONFIG_BTB /* toggle branch predition */
55#define CONFIG_ENABLE_36BIT_PHYS 1
56
Timur Tabie46fedf2011-08-04 18:03:41 -050057#define CONFIG_SYS_CCSRBAR 0xef000000
58#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Peter Tyser1f03cbf2008-12-23 16:32:00 -060059
60/*
61 * Diagnostics
62 */
63#define CONFIG_SYS_ALT_MEMTEST
64#define CONFIG_SYS_MEMTEST_START 0x10000000
65#define CONFIG_SYS_MEMTEST_END 0x20000000
Peter Tyser66a8b442010-10-22 00:20:33 -050066#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
67 CONFIG_SYS_POST_I2C)
68#define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
69 CONFIG_SYS_I2C_EEPROM_ADDR, \
70 CONFIG_SYS_I2C_PCA953X_ADDR0, \
71 CONFIG_SYS_I2C_PCA953X_ADDR1, \
72 CONFIG_SYS_I2C_RTC_ADDR}
Peter Tyser1f03cbf2008-12-23 16:32:00 -060073
74/*
75 * Memory map
76 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
77 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
78 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
79 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
80 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
81 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
82 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
83 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
84 */
85
Kumar Gala202d9482009-09-15 22:21:58 -050086#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
Peter Tyser1f03cbf2008-12-23 16:32:00 -060087
88/*
89 * NAND flash configuration
90 */
91#define CONFIG_SYS_NAND_BASE 0xef800000
92#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
93#define CONFIG_SYS_MAX_NAND_DEVICE 1
94#define CONFIG_NAND_ACTL
95#define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
96#define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
97#define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
98#define CONFIG_SYS_NAND_ACTL_DELAY 25
99
100/*
101 * NOR flash configuration
102 */
103#define CONFIG_SYS_FLASH_BASE 0xfc000000
104#define CONFIG_SYS_FLASH_BASE2 0xf8000000
105#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
106#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
107#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
108#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
109#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
110#define CONFIG_FLASH_CFI_DRIVER
111#define CONFIG_SYS_FLASH_CFI
Peter Tyser5ff82102009-07-19 19:17:40 -0500112#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600113#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
114 {0xfbf40000, 0xc0000} }
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200115#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600116
117/*
118 * Chip select configuration
119 */
120/* NOR Flash 0 on CS0 */
121#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
122 BR_PS_16 | \
123 BR_V)
124#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
125 OR_GPCM_ACS_DIV4 | \
126 OR_GPCM_SCY_8)
127
128/* NOR Flash 1 on CS1 */
129#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
130 BR_PS_16 | \
131 BR_V)
132#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
133
134/* NAND flash on CS2 */
135#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
136 BR_PS_8 | \
137 BR_V)
138
139/* NAND flash on CS2 */
140#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
141 OR_GPCM_BCTLD | \
142 OR_GPCM_CSNT | \
143 OR_GPCM_ACS_DIV4 | \
144 OR_GPCM_SCY_4 | \
145 OR_GPCM_TRLX | \
146 OR_GPCM_EHTR)
147
148/* NAND flash on CS3 */
149#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
150 BR_PS_8 | \
151 BR_V)
152#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
153
154/*
155 * Use L1 as initial stack
156 */
157#define CONFIG_SYS_INIT_RAM_LOCK 1
158#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200159#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600160
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200161#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600162#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
163
164#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
165#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
166
167/*
168 * Serial Port
169 */
170#define CONFIG_CONS_INDEX 1
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600171#define CONFIG_SYS_NS16550_SERIAL
172#define CONFIG_SYS_NS16550_REG_SIZE 1
173#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
174#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
175#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
176#define CONFIG_SYS_BAUDRATE_TABLE \
177 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600178#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
179#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
180
181/*
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600182 * I2C
183 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200184#define CONFIG_SYS_I2C
185#define CONFIG_SYS_I2C_FSL
186#define CONFIG_SYS_FSL_I2C_SPEED 400000
187#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
188#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
189#define CONFIG_SYS_FSL_I2C2_SPEED 400000
190#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
191#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600192
193/* I2C EEPROM */
194#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
195#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
196#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
197#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
198
199/* I2C RTC */
200#define CONFIG_RTC_M41T11 1
201#define CONFIG_SYS_I2C_RTC_ADDR 0x68
202#define CONFIG_SYS_M41T11_BASE_YEAR 2000
203
204/* GPIO */
205#define CONFIG_PCA953X
206#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
207#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
208#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
209
210/* PCA957 @ 0x18 */
211#define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
212#define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
213#define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
214#define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
215#define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
John Schmoller72fb68d2010-10-22 00:20:25 -0500216#define CONFIG_SYS_PCA953X_NVM_WP 0x20
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600217#define CONFIG_SYS_PCA953X_MONARCH 0x40
218#define CONFIG_SYS_PCA953X_EREADY 0x80
219
220/* PCA957 @ 0x19 */
221#define CONFIG_SYS_PCA953X_P14_IO0 0x01
222#define CONFIG_SYS_PCA953X_P14_IO1 0x02
223#define CONFIG_SYS_PCA953X_P14_IO2 0x04
224#define CONFIG_SYS_PCA953X_P14_IO3 0x08
225#define CONFIG_SYS_PCA953X_P14_IO4 0x10
226#define CONFIG_SYS_PCA953X_P14_IO5 0x20
227#define CONFIG_SYS_PCA953X_P14_IO6 0x40
228#define CONFIG_SYS_PCA953X_P14_IO7 0x80
229
Peter Tyser66a8b442010-10-22 00:20:33 -0500230/* 12-bit ADC used to measure CPU diode */
231#define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
232
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600233/*
234 * General PCI
235 * Memory space is mapped 1-1, but I/O space must start from 0.
236 */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500237#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
238#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600239#define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500240#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600241#define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
242#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
243
244/*
245 * Networking options
246 */
247#define CONFIG_TSEC_ENET /* tsec ethernet support */
248#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600249#define CONFIG_MII 1 /* MII PHY management */
250#define CONFIG_ETHPRIME "eTSEC1"
251
252#define CONFIG_TSEC1 1
253#define CONFIG_TSEC1_NAME "eTSEC1"
254#define TSEC1_FLAGS TSEC_GIGABIT
255#define TSEC1_PHY_ADDR 1
256#define TSEC1_PHYIDX 0
257#define CONFIG_HAS_ETH0
258
259#define CONFIG_TSEC2 1
260#define CONFIG_TSEC2_NAME "eTSEC2"
261#define TSEC2_FLAGS TSEC_GIGABIT
262#define TSEC2_PHY_ADDR 2
263#define TSEC2_PHYIDX 0
264#define CONFIG_HAS_ETH1
265
266#define CONFIG_TSEC3 1
267#define CONFIG_TSEC3_NAME "eTSEC3"
268#define TSEC3_FLAGS TSEC_GIGABIT
269#define TSEC3_PHY_ADDR 3
270#define TSEC3_PHYIDX 0
271#define CONFIG_HAS_ETH2
272
273#define CONFIG_TSEC4 1
274#define CONFIG_TSEC4_NAME "eTSEC4"
275#define TSEC4_FLAGS TSEC_GIGABIT
276#define TSEC4_PHY_ADDR 4
277#define TSEC4_PHYIDX 0
278#define CONFIG_HAS_ETH3
279
280/*
281 * BOOTP options
282 */
283#define CONFIG_BOOTP_BOOTFILESIZE
284#define CONFIG_BOOTP_BOOTPATH
285#define CONFIG_BOOTP_GATEWAY
286
287/*
288 * Command configuration.
289 */
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600290#define CONFIG_CMD_DATE
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600291#define CONFIG_CMD_EEPROM
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600292#define CONFIG_CMD_JFFS2
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600293#define CONFIG_CMD_NAND
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600294#define CONFIG_CMD_PCA953X
295#define CONFIG_CMD_PCA953X_INFO
296#define CONFIG_CMD_PCI
John Schmoller96d61602010-10-22 00:20:23 -0500297#define CONFIG_CMD_PCI_ENUM
Becky Bruce199e2622010-06-17 11:37:25 -0500298#define CONFIG_CMD_REGINFO
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600299
300/*
301 * Miscellaneous configurable options
302 */
303#define CONFIG_SYS_LONGHELP /* undef to save memory */
304#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600305#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
306#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
307#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
308#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600309#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillips5be58f52010-07-14 19:47:18 -0500310#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600311#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600312#define CONFIG_PANIC_HANG /* do not reset board on panic */
313#define CONFIG_PREBOOT /* enable preboot variable */
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600314#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
315#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
316
317/*
318 * For booting Linux, the board info and command line data
319 * have to be in the first 16 MB of memory, since this is
320 * the maximum mapped by the Linux kernel during initialization.
321 */
322#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
Peter Tyser39121c02009-07-21 13:51:07 -0500323#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600324
325/*
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600326 * Environment Configuration
327 */
328#define CONFIG_ENV_IS_IN_FLASH 1
329#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
330#define CONFIG_ENV_SIZE 0x8000
331#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
332
333/*
334 * Flash memory map:
335 * fff80000 - ffffffff Pri U-Boot (512 KB)
336 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
337 * fff00000 - fff3ffff Pri FDT (256KB)
338 * fef00000 - ffefffff Pri OS image (16MB)
339 * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
340 *
341 * fbf80000 - fbffffff Sec U-Boot (512 KB)
342 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
343 * fbf00000 - fbf3ffff Sec FDT (256KB)
344 * faf00000 - fbefffff Sec OS image (16MB)
345 * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
346 */
Marek Vasut5368c552012-09-23 17:41:24 +0200347#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
348#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000)
349#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
350#define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000)
351#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
352#define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000)
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600353
354#define CONFIG_PROG_UBOOT1 \
355 "$download_cmd $loadaddr $ubootfile; " \
356 "if test $? -eq 0; then " \
357 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
358 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
359 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
360 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
361 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
362 "if test $? -ne 0; then " \
363 "echo PROGRAM FAILED; " \
364 "else; " \
365 "echo PROGRAM SUCCEEDED; " \
366 "fi; " \
367 "else; " \
368 "echo DOWNLOAD FAILED; " \
369 "fi;"
370
371#define CONFIG_PROG_UBOOT2 \
372 "$download_cmd $loadaddr $ubootfile; " \
373 "if test $? -eq 0; then " \
374 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
375 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
376 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
377 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
378 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
379 "if test $? -ne 0; then " \
380 "echo PROGRAM FAILED; " \
381 "else; " \
382 "echo PROGRAM SUCCEEDED; " \
383 "fi; " \
384 "else; " \
385 "echo DOWNLOAD FAILED; " \
386 "fi;"
387
388#define CONFIG_BOOT_OS_NET \
389 "$download_cmd $osaddr $osfile; " \
390 "if test $? -eq 0; then " \
391 "if test -n $fdtaddr; then " \
392 "$download_cmd $fdtaddr $fdtfile; " \
393 "if test $? -eq 0; then " \
394 "bootm $osaddr - $fdtaddr; " \
395 "else; " \
396 "echo FDT DOWNLOAD FAILED; " \
397 "fi; " \
398 "else; " \
399 "bootm $osaddr; " \
400 "fi; " \
401 "else; " \
402 "echo OS DOWNLOAD FAILED; " \
403 "fi;"
404
405#define CONFIG_PROG_OS1 \
406 "$download_cmd $osaddr $osfile; " \
407 "if test $? -eq 0; then " \
408 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
409 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
410 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
411 "if test $? -ne 0; then " \
412 "echo OS PROGRAM FAILED; " \
413 "else; " \
414 "echo OS PROGRAM SUCCEEDED; " \
415 "fi; " \
416 "else; " \
417 "echo OS DOWNLOAD FAILED; " \
418 "fi;"
419
420#define CONFIG_PROG_OS2 \
421 "$download_cmd $osaddr $osfile; " \
422 "if test $? -eq 0; then " \
423 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
424 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
425 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
426 "if test $? -ne 0; then " \
427 "echo OS PROGRAM FAILED; " \
428 "else; " \
429 "echo OS PROGRAM SUCCEEDED; " \
430 "fi; " \
431 "else; " \
432 "echo OS DOWNLOAD FAILED; " \
433 "fi;"
434
435#define CONFIG_PROG_FDT1 \
436 "$download_cmd $fdtaddr $fdtfile; " \
437 "if test $? -eq 0; then " \
438 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
439 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
440 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
441 "if test $? -ne 0; then " \
442 "echo FDT PROGRAM FAILED; " \
443 "else; " \
444 "echo FDT PROGRAM SUCCEEDED; " \
445 "fi; " \
446 "else; " \
447 "echo FDT DOWNLOAD FAILED; " \
448 "fi;"
449
450#define CONFIG_PROG_FDT2 \
451 "$download_cmd $fdtaddr $fdtfile; " \
452 "if test $? -eq 0; then " \
453 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
454 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
455 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
456 "if test $? -ne 0; then " \
457 "echo FDT PROGRAM FAILED; " \
458 "else; " \
459 "echo FDT PROGRAM SUCCEEDED; " \
460 "fi; " \
461 "else; " \
462 "echo FDT DOWNLOAD FAILED; " \
463 "fi;"
464
465#define CONFIG_EXTRA_ENV_SETTINGS \
466 "autoload=yes\0" \
467 "download_cmd=tftp\0" \
468 "console_args=console=ttyS0,115200\0" \
469 "root_args=root=/dev/nfs rw\0" \
470 "misc_args=ip=on\0" \
471 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
472 "bootfile=/home/user/file\0" \
Peter Tyserc00ac252010-10-22 00:20:26 -0500473 "osfile=/home/user/board.uImage\0" \
474 "fdtfile=/home/user/board.dtb\0" \
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600475 "ubootfile=/home/user/u-boot.bin\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500476 "fdtaddr=0x1e00000\0" \
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600477 "osaddr=0x1000000\0" \
478 "loadaddr=0x1000000\0" \
479 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
480 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
481 "prog_os1="CONFIG_PROG_OS1"\0" \
482 "prog_os2="CONFIG_PROG_OS2"\0" \
483 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
484 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
485 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
486 "bootcmd_flash1=run set_bootargs; " \
487 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
488 "bootcmd_flash2=run set_bootargs; " \
489 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
490 "bootcmd=run bootcmd_flash1\0"
491#endif /* __CONFIG_H */