blob: 3f0132a6e339fd23e88857c0a83dae1ad8825d79 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass1938f4a2013-03-11 06:49:53 +00002/*
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2002-2006
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * (C) Copyright 2002
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Marius Groeger <mgroeger@sysgo.de>
Simon Glass1938f4a2013-03-11 06:49:53 +000010 */
11
12#include <common.h>
Simon Glassf0293d32018-11-15 18:43:52 -070013#include <bloblist.h>
Simon Glassd96c2602019-12-28 10:44:58 -070014#include <clock_legacy.h>
Simon Glass24b852a2015-11-08 23:47:45 -070015#include <console.h>
Mario Six5d6c61a2018-08-06 10:23:41 +020016#include <cpu.h>
Simon Glass30c7c432019-11-14 12:57:34 -070017#include <cpu_func.h>
Simon Glassab7cd622014-07-23 06:55:04 -060018#include <dm.h>
Simon Glass4bfd1f52019-08-01 09:46:43 -060019#include <env.h>
Simon Glassf3998fd2019-08-02 09:44:25 -060020#include <env_internal.h>
Simon Glass1938f4a2013-03-11 06:49:53 +000021#include <fdtdec.h>
Simon Glassf828bf22013-04-20 08:42:41 +000022#include <fs.h>
Simon Glassdb41d652019-12-28 10:45:07 -070023#include <hang.h>
Simon Glasse4fef6c2013-03-11 14:30:42 +000024#include <i2c.h>
Simon Glass67c4e9f2019-11-14 12:57:45 -070025#include <init.h>
Simon Glass1938f4a2013-03-11 06:49:53 +000026#include <initcall.h>
Simon Glass3c1ecde2019-08-01 09:46:38 -060027#include <lcd.h>
Simon Glassfb5cf7f2015-02-27 22:06:36 -070028#include <malloc.h>
Joe Hershberger0eb25b62015-03-22 17:08:59 -050029#include <mapmem.h>
Simon Glassa733b062013-04-26 02:53:43 +000030#include <os.h>
Simon Glass1938f4a2013-03-11 06:49:53 +000031#include <post.h>
Simon Glasse47b2d62017-03-31 08:40:38 -060032#include <relocate.h>
Simon Glassb03e0512019-11-14 12:57:24 -070033#include <serial.h>
Simon Glassb0edea32018-11-15 18:44:09 -070034#ifdef CONFIG_SPL
35#include <spl.h>
36#endif
Jeroen Hofsteec5d40012014-06-23 23:20:19 +020037#include <status_led.h>
Mario Six23471ae2018-08-06 10:23:34 +020038#include <sysreset.h>
Simon Glass1057e6c2016-02-24 09:14:50 -070039#include <timer.h>
Simon Glass71c52db2013-06-11 11:14:42 -070040#include <trace.h>
Simon Glass5a541942016-01-18 19:52:21 -070041#include <video.h>
Simon Glasse4fef6c2013-03-11 14:30:42 +000042#include <watchdog.h>
Simon Glassb885d022017-05-17 08:23:01 -060043#ifdef CONFIG_MACH_TYPE
44#include <asm/mach-types.h>
45#endif
Simon Glass1fbf97d2017-03-31 08:40:39 -060046#if defined(CONFIG_MP) && defined(CONFIG_PPC)
47#include <asm/mp.h>
48#endif
Simon Glass1938f4a2013-03-11 06:49:53 +000049#include <asm/io.h>
50#include <asm/sections.h>
Simon Glassab7cd622014-07-23 06:55:04 -060051#include <dm/root.h>
Simon Glass056285f2017-03-31 08:40:35 -060052#include <linux/errno.h>
Simon Glass1938f4a2013-03-11 06:49:53 +000053
54/*
55 * Pointer to initial global data area
56 *
57 * Here we initialize it if needed.
58 */
59#ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
60#undef XTRN_DECLARE_GLOBAL_DATA_PTR
61#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
Mario Six16ef1472018-01-15 11:10:02 +010062DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
Simon Glass1938f4a2013-03-11 06:49:53 +000063#else
64DECLARE_GLOBAL_DATA_PTR;
65#endif
66
67/*
Simon Glass4c509342015-04-28 20:25:03 -060068 * TODO(sjg@chromium.org): IMO this code should be
Simon Glass1938f4a2013-03-11 06:49:53 +000069 * refactored to a single function, something like:
70 *
71 * void led_set_state(enum led_colour_t colour, int on);
72 */
73/************************************************************************
74 * Coloured LED functionality
75 ************************************************************************
76 * May be supplied by boards if desired
77 */
Jeroen Hofsteec5d40012014-06-23 23:20:19 +020078__weak void coloured_LED_init(void) {}
79__weak void red_led_on(void) {}
80__weak void red_led_off(void) {}
81__weak void green_led_on(void) {}
82__weak void green_led_off(void) {}
83__weak void yellow_led_on(void) {}
84__weak void yellow_led_off(void) {}
85__weak void blue_led_on(void) {}
86__weak void blue_led_off(void) {}
Simon Glass1938f4a2013-03-11 06:49:53 +000087
88/*
89 * Why is gd allocated a register? Prior to reloc it might be better to
90 * just pass it around to each function in this file?
91 *
92 * After reloc one could argue that it is hardly used and doesn't need
93 * to be in a register. Or if it is it should perhaps hold pointers to all
94 * global data for all modules, so that post-reloc we can avoid the massive
95 * literal pool we get on ARM. Or perhaps just encourage each module to use
96 * a structure...
97 */
98
Sonic Zhangd54d7eb2014-07-17 19:01:34 +080099#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000100static int init_func_watchdog_init(void)
101{
Tom Riniea3310e2017-03-14 11:08:10 -0400102# if defined(CONFIG_HW_WATCHDOG) && \
103 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -0700104 defined(CONFIG_SH) || \
Anatolij Gustschin46d7a3b2016-06-13 14:24:23 +0200105 defined(CONFIG_DESIGNWARE_WATCHDOG) || \
Stefan Roese14a380a2015-03-10 08:04:36 +0100106 defined(CONFIG_IMX_WATCHDOG))
Sonic Zhangd54d7eb2014-07-17 19:01:34 +0800107 hw_watchdog_init();
Simon Glasse4fef6c2013-03-11 14:30:42 +0000108 puts(" Watchdog enabled\n");
Anatolij Gustschinba169d92016-06-13 14:24:24 +0200109# endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000110 WATCHDOG_RESET();
111
112 return 0;
113}
114
115int init_func_watchdog_reset(void)
116{
117 WATCHDOG_RESET();
118
119 return 0;
120}
121#endif /* CONFIG_WATCHDOG */
122
Jeroen Hofsteedd2a6cd2014-10-08 22:57:22 +0200123__weak void board_add_ram_info(int use_default)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000124{
125 /* please define platform specific board_add_ram_info() */
126}
127
Simon Glass1938f4a2013-03-11 06:49:53 +0000128static int init_baud_rate(void)
129{
Simon Glassbfebc8c2017-08-03 12:22:13 -0600130 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
Simon Glass1938f4a2013-03-11 06:49:53 +0000131 return 0;
132}
133
134static int display_text_info(void)
135{
Ben Stoltz9b217492015-07-31 09:31:37 -0600136#if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
Daniel Schwierzeck9fdee7d2014-11-15 23:46:53 +0100137 ulong bss_start, bss_end, text_base;
Simon Glass1938f4a2013-03-11 06:49:53 +0000138
Simon Glass632efa72013-03-11 07:06:48 +0000139 bss_start = (ulong)&__bss_start;
140 bss_end = (ulong)&__bss_end;
Albert ARIBAUDb60eff32014-02-22 17:53:43 +0100141
Sonic Zhangd54d7eb2014-07-17 19:01:34 +0800142#ifdef CONFIG_SYS_TEXT_BASE
Daniel Schwierzeck9fdee7d2014-11-15 23:46:53 +0100143 text_base = CONFIG_SYS_TEXT_BASE;
Sonic Zhangd54d7eb2014-07-17 19:01:34 +0800144#else
Daniel Schwierzeck9fdee7d2014-11-15 23:46:53 +0100145 text_base = CONFIG_SYS_MONITOR_BASE;
Sonic Zhangd54d7eb2014-07-17 19:01:34 +0800146#endif
Daniel Schwierzeck9fdee7d2014-11-15 23:46:53 +0100147
148 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
Mario Six16ef1472018-01-15 11:10:02 +0100149 text_base, bss_start, bss_end);
Simon Glassa733b062013-04-26 02:53:43 +0000150#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000151
Simon Glass1938f4a2013-03-11 06:49:53 +0000152 return 0;
153}
154
Mario Six23471ae2018-08-06 10:23:34 +0200155#ifdef CONFIG_SYSRESET
156static int print_resetinfo(void)
157{
158 struct udevice *dev;
159 char status[256];
160 int ret;
161
162 ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
163 if (ret) {
164 debug("%s: No sysreset device found (error: %d)\n",
165 __func__, ret);
166 /* Not all boards have sysreset drivers available during early
167 * boot, so don't fail if one can't be found.
168 */
169 return 0;
170 }
171
172 if (!sysreset_get_status(dev, status, sizeof(status)))
173 printf("%s", status);
174
175 return 0;
176}
177#endif
178
Mario Six5d6c61a2018-08-06 10:23:41 +0200179#if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
180static int print_cpuinfo(void)
181{
182 struct udevice *dev;
183 char desc[512];
184 int ret;
185
186 ret = uclass_first_device_err(UCLASS_CPU, &dev);
187 if (ret) {
188 debug("%s: Could not get CPU device (err = %d)\n",
189 __func__, ret);
190 return ret;
191 }
192
193 ret = cpu_get_desc(dev, desc, sizeof(desc));
194 if (ret) {
195 debug("%s: Could not get CPU description (err = %d)\n",
196 dev->name, ret);
197 return ret;
198 }
199
Bin Mengecfe6632018-10-10 22:06:55 -0700200 printf("CPU: %s\n", desc);
Mario Six5d6c61a2018-08-06 10:23:41 +0200201
202 return 0;
203}
204#endif
205
Simon Glass1938f4a2013-03-11 06:49:53 +0000206static int announce_dram_init(void)
207{
208 puts("DRAM: ");
209 return 0;
210}
211
212static int show_dram_config(void)
213{
York Sunfa39ffe2014-05-02 17:28:05 -0700214 unsigned long long size;
Simon Glass1938f4a2013-03-11 06:49:53 +0000215
216#ifdef CONFIG_NR_DRAM_BANKS
217 int i;
218
219 debug("\nRAM Configuration:\n");
220 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
221 size += gd->bd->bi_dram[i].size;
Bin Meng715f5992015-08-06 01:31:20 -0700222 debug("Bank #%d: %llx ", i,
223 (unsigned long long)(gd->bd->bi_dram[i].start));
Simon Glass1938f4a2013-03-11 06:49:53 +0000224#ifdef DEBUG
225 print_size(gd->bd->bi_dram[i].size, "\n");
226#endif
227 }
228 debug("\nDRAM: ");
229#else
230 size = gd->ram_size;
231#endif
232
Simon Glasse4fef6c2013-03-11 14:30:42 +0000233 print_size(size, "");
234 board_add_ram_info(0);
235 putc('\n');
Simon Glass1938f4a2013-03-11 06:49:53 +0000236
237 return 0;
238}
239
Simon Glass76b00ac2017-03-31 08:40:32 -0600240__weak int dram_init_banksize(void)
Simon Glass1938f4a2013-03-11 06:49:53 +0000241{
242#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
243 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
244 gd->bd->bi_dram[0].size = get_effective_memsize();
245#endif
Simon Glass76b00ac2017-03-31 08:40:32 -0600246
247 return 0;
Simon Glass1938f4a2013-03-11 06:49:53 +0000248}
249
Simon Glass69153982017-05-12 21:09:56 -0600250#if defined(CONFIG_SYS_I2C)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000251static int init_func_i2c(void)
252{
253 puts("I2C: ");
trem815a76f2013-09-21 18:13:34 +0200254#ifdef CONFIG_SYS_I2C
255 i2c_init_all();
256#else
Simon Glasse4fef6c2013-03-11 14:30:42 +0000257 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
trem815a76f2013-09-21 18:13:34 +0200258#endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000259 puts("ready\n");
260 return 0;
261}
262#endif
263
Rajesh Bhagat1fab98f2018-01-17 16:13:08 +0530264#if defined(CONFIG_VID)
265__weak int init_func_vid(void)
266{
267 return 0;
268}
269#endif
270
Simon Glass1938f4a2013-03-11 06:49:53 +0000271static int setup_mon_len(void)
272{
Michal Simeke945f6d2014-05-08 16:08:44 +0200273#if defined(__ARM__) || defined(__MICROBLAZE__)
Albert ARIBAUDb60eff32014-02-22 17:53:43 +0100274 gd->mon_len = (ulong)&__bss_end - (ulong)_start;
Ben Stoltz9b217492015-07-31 09:31:37 -0600275#elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
Simon Glassa733b062013-04-26 02:53:43 +0000276 gd->mon_len = (ulong)&_end - (ulong)_init;
Tom Riniea3310e2017-03-14 11:08:10 -0400277#elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
Sonic Zhangd54d7eb2014-07-17 19:01:34 +0800278 gd->mon_len = CONFIG_SYS_MONITOR_LEN;
Rick Chen068feb92017-12-26 13:55:58 +0800279#elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800280 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
Simon Glassb0b35952016-05-14 18:49:28 -0600281#elif defined(CONFIG_SYS_MONITOR_BASE)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000282 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
283 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
Simon Glass632efa72013-03-11 07:06:48 +0000284#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000285 return 0;
286}
287
Simon Glassb0edea32018-11-15 18:44:09 -0700288static int setup_spl_handoff(void)
289{
290#if CONFIG_IS_ENABLED(HANDOFF)
291 gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF,
292 sizeof(struct spl_handoff));
293 debug("Found SPL hand-off info %p\n", gd->spl_handoff);
294#endif
295
296 return 0;
297}
298
Simon Glass1938f4a2013-03-11 06:49:53 +0000299__weak int arch_cpu_init(void)
300{
301 return 0;
302}
303
Paul Burton8ebf5062016-09-21 11:18:46 +0100304__weak int mach_cpu_init(void)
305{
306 return 0;
307}
308
Simon Glass1938f4a2013-03-11 06:49:53 +0000309/* Get the top of usable RAM */
310__weak ulong board_get_usable_ram_top(ulong total_size)
311{
Stephen Warren1e4d11a2014-12-23 10:34:49 -0700312#ifdef CONFIG_SYS_SDRAM_BASE
313 /*
Simon Glass4c509342015-04-28 20:25:03 -0600314 * Detect whether we have so much RAM that it goes past the end of our
Stephen Warren1e4d11a2014-12-23 10:34:49 -0700315 * 32-bit address space. If so, clip the usable RAM so it doesn't.
316 */
317 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
318 /*
319 * Will wrap back to top of 32-bit space when reservations
320 * are made.
321 */
322 return 0;
323#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000324 return gd->ram_top;
325}
326
327static int setup_dest_addr(void)
328{
329 debug("Monitor len: %08lX\n", gd->mon_len);
330 /*
331 * Ram is setup, size stored in gd !!
332 */
333 debug("Ram size: %08lX\n", (ulong)gd->ram_size);
York Sun36cc0de2017-03-06 09:02:28 -0800334#if defined(CONFIG_SYS_MEM_TOP_HIDE)
Simon Glass1938f4a2013-03-11 06:49:53 +0000335 /*
336 * Subtract specified amount of memory to hide so that it won't
337 * get "touched" at all by U-Boot. By fixing up gd->ram_size
338 * the Linux kernel should now get passed the now "corrected"
York Sun36cc0de2017-03-06 09:02:28 -0800339 * memory size and won't touch it either. This should work
340 * for arch/ppc and arch/powerpc. Only Linux board ports in
341 * arch/powerpc with bootwrapper support, that recalculate the
342 * memory size from the SDRAM controller setup will have to
343 * get fixed.
Simon Glass1938f4a2013-03-11 06:49:53 +0000344 */
York Sun36cc0de2017-03-06 09:02:28 -0800345 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
346#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000347#ifdef CONFIG_SYS_SDRAM_BASE
Siva Durga Prasad Paladugu1473b122018-07-16 15:56:10 +0530348 gd->ram_base = CONFIG_SYS_SDRAM_BASE;
Simon Glass1938f4a2013-03-11 06:49:53 +0000349#endif
Siva Durga Prasad Paladugu1473b122018-07-16 15:56:10 +0530350 gd->ram_top = gd->ram_base + get_effective_memsize();
Simon Glass1938f4a2013-03-11 06:49:53 +0000351 gd->ram_top = board_get_usable_ram_top(gd->mon_len);
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000352 gd->relocaddr = gd->ram_top;
Simon Glass1938f4a2013-03-11 06:49:53 +0000353 debug("Ram top: %08lX\n", (ulong)gd->ram_top);
Gabriel Huauec3b4822014-09-03 13:57:54 -0700354#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
Simon Glasse4fef6c2013-03-11 14:30:42 +0000355 /*
356 * We need to make sure the location we intend to put secondary core
357 * boot code is reserved and not used by any part of u-boot
358 */
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000359 if (gd->relocaddr > determine_mp_bootpg(NULL)) {
360 gd->relocaddr = determine_mp_bootpg(NULL);
361 debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
Simon Glasse4fef6c2013-03-11 14:30:42 +0000362 }
363#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000364 return 0;
365}
366
Simon Glass1938f4a2013-03-11 06:49:53 +0000367#ifdef CONFIG_PRAM
368/* reserve protected RAM */
369static int reserve_pram(void)
370{
371 ulong reg;
372
Simon Glassbfebc8c2017-08-03 12:22:13 -0600373 reg = env_get_ulong("pram", 10, CONFIG_PRAM);
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000374 gd->relocaddr -= (reg << 10); /* size is in kB */
Simon Glass1938f4a2013-03-11 06:49:53 +0000375 debug("Reserving %ldk for protected RAM at %08lx\n", reg,
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000376 gd->relocaddr);
Simon Glass1938f4a2013-03-11 06:49:53 +0000377 return 0;
378}
379#endif /* CONFIG_PRAM */
380
381/* Round memory pointer down to next 4 kB limit */
382static int reserve_round_4k(void)
383{
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000384 gd->relocaddr &= ~(4096 - 1);
Simon Glass1938f4a2013-03-11 06:49:53 +0000385 return 0;
386}
387
Simon Glass80d4bcd2017-03-31 08:40:29 -0600388#ifdef CONFIG_ARM
Siva Durga Prasad Paladugu60873f72017-07-13 19:01:08 +0530389__weak int reserve_mmu(void)
Simon Glass1938f4a2013-03-11 06:49:53 +0000390{
Trevor Woerner10015022019-05-03 09:41:00 -0400391#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
Simon Glass1938f4a2013-03-11 06:49:53 +0000392 /* reserve TLB table */
David Fengcce6be72013-12-14 11:47:36 +0800393 gd->arch.tlb_size = PGTABLE_SIZE;
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000394 gd->relocaddr -= gd->arch.tlb_size;
Simon Glass1938f4a2013-03-11 06:49:53 +0000395
396 /* round down to next 64 kB limit */
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000397 gd->relocaddr &= ~(0x10000 - 1);
Simon Glass1938f4a2013-03-11 06:49:53 +0000398
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000399 gd->arch.tlb_addr = gd->relocaddr;
Simon Glass1938f4a2013-03-11 06:49:53 +0000400 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
401 gd->arch.tlb_addr + gd->arch.tlb_size);
York Sun50e93b92016-06-24 16:46:19 -0700402
403#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
404 /*
405 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
406 * with location within secure ram.
407 */
408 gd->arch.tlb_allocated = gd->arch.tlb_addr;
409#endif
Simon Glass80d4bcd2017-03-31 08:40:29 -0600410#endif
York Sun50e93b92016-06-24 16:46:19 -0700411
Simon Glass1938f4a2013-03-11 06:49:53 +0000412 return 0;
413}
414#endif
415
Simon Glass5a541942016-01-18 19:52:21 -0700416static int reserve_video(void)
417{
Simon Glass0f079eb2017-03-31 08:40:30 -0600418#ifdef CONFIG_DM_VIDEO
Simon Glass5a541942016-01-18 19:52:21 -0700419 ulong addr;
420 int ret;
421
422 addr = gd->relocaddr;
423 ret = video_reserve(&addr);
424 if (ret)
425 return ret;
426 gd->relocaddr = addr;
Simon Glass0f079eb2017-03-31 08:40:30 -0600427#elif defined(CONFIG_LCD)
Simon Glass5a541942016-01-18 19:52:21 -0700428# ifdef CONFIG_FB_ADDR
Simon Glass1938f4a2013-03-11 06:49:53 +0000429 gd->fb_base = CONFIG_FB_ADDR;
Simon Glass5a541942016-01-18 19:52:21 -0700430# else
Simon Glass1938f4a2013-03-11 06:49:53 +0000431 /* reserve memory for LCD display (always full pages) */
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000432 gd->relocaddr = lcd_setmem(gd->relocaddr);
433 gd->fb_base = gd->relocaddr;
Simon Glass5a541942016-01-18 19:52:21 -0700434# endif /* CONFIG_FB_ADDR */
Simon Glass0f079eb2017-03-31 08:40:30 -0600435#endif
Simon Glass8703ef32016-01-18 19:52:20 -0700436
437 return 0;
438}
Simon Glass8703ef32016-01-18 19:52:20 -0700439
Simon Glass71c52db2013-06-11 11:14:42 -0700440static int reserve_trace(void)
441{
442#ifdef CONFIG_TRACE
443 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
444 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
Heinrich Schuchardt7ea33572019-06-14 21:52:22 +0200445 debug("Reserving %luk for trace data at: %08lx\n",
446 (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
Simon Glass71c52db2013-06-11 11:14:42 -0700447#endif
448
449 return 0;
450}
451
Simon Glass1938f4a2013-03-11 06:49:53 +0000452static int reserve_uboot(void)
453{
Alexey Brodkinff2b2ba2018-05-25 16:08:14 +0300454 if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
455 /*
456 * reserve memory for U-Boot code, data & bss
457 * round down to next 4 kB limit
458 */
459 gd->relocaddr -= gd->mon_len;
460 gd->relocaddr &= ~(4096 - 1);
461 #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
462 /* round down to next 64 kB limit so that IVPR stays aligned */
463 gd->relocaddr &= ~(65536 - 1);
464 #endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000465
Alexey Brodkinff2b2ba2018-05-25 16:08:14 +0300466 debug("Reserving %ldk for U-Boot at: %08lx\n",
467 gd->mon_len >> 10, gd->relocaddr);
468 }
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000469
470 gd->start_addr_sp = gd->relocaddr;
471
Simon Glass1938f4a2013-03-11 06:49:53 +0000472 return 0;
473}
474
Vikas Manocha5f7adb52019-08-16 09:57:44 -0700475#ifdef CONFIG_SYS_NONCACHED_MEMORY
476static int reserve_noncached(void)
477{
Stephen Warren5e0404f2019-08-27 11:54:31 -0600478 /*
479 * The value of gd->start_addr_sp must match the value of malloc_start
480 * calculated in boatrd_f.c:initr_malloc(), which is passed to
481 * board_r.c:mem_malloc_init() and then used by
482 * cache.c:noncached_init()
483 *
484 * These calculations must match the code in cache.c:noncached_init()
485 */
486 gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) -
487 MMU_SECTION_SIZE;
488 gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
489 MMU_SECTION_SIZE);
Vikas Manocha5f7adb52019-08-16 09:57:44 -0700490 debug("Reserving %dM for noncached_alloc() at: %08lx\n",
491 CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
492
493 return 0;
494}
495#endif
496
Simon Glass1938f4a2013-03-11 06:49:53 +0000497/* reserve memory for malloc() area */
498static int reserve_malloc(void)
499{
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000500 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
Simon Glass1938f4a2013-03-11 06:49:53 +0000501 debug("Reserving %dk for malloc() at: %08lx\n",
Mario Six16ef1472018-01-15 11:10:02 +0100502 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
Vikas Manocha5f7adb52019-08-16 09:57:44 -0700503#ifdef CONFIG_SYS_NONCACHED_MEMORY
504 reserve_noncached();
505#endif
506
Simon Glass1938f4a2013-03-11 06:49:53 +0000507 return 0;
508}
509
510/* (permanently) allocate a Board Info struct */
511static int reserve_board(void)
512{
Sonic Zhangd54d7eb2014-07-17 19:01:34 +0800513 if (!gd->bd) {
514 gd->start_addr_sp -= sizeof(bd_t);
515 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
516 memset(gd->bd, '\0', sizeof(bd_t));
517 debug("Reserving %zu Bytes for Board Info at: %08lx\n",
518 sizeof(bd_t), gd->start_addr_sp);
519 }
Simon Glass1938f4a2013-03-11 06:49:53 +0000520 return 0;
521}
522
523static int setup_machine(void)
524{
525#ifdef CONFIG_MACH_TYPE
526 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
527#endif
528 return 0;
529}
530
531static int reserve_global_data(void)
532{
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000533 gd->start_addr_sp -= sizeof(gd_t);
534 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
Simon Glass1938f4a2013-03-11 06:49:53 +0000535 debug("Reserving %zu Bytes for Global Data at: %08lx\n",
Mario Six16ef1472018-01-15 11:10:02 +0100536 sizeof(gd_t), gd->start_addr_sp);
Simon Glass1938f4a2013-03-11 06:49:53 +0000537 return 0;
538}
539
540static int reserve_fdt(void)
541{
Siva Durga Prasad Paladugue9acb9e2015-12-03 15:46:03 +0100542#ifndef CONFIG_OF_EMBED
Simon Glass1938f4a2013-03-11 06:49:53 +0000543 /*
Simon Glass4c509342015-04-28 20:25:03 -0600544 * If the device tree is sitting immediately above our image then we
Simon Glass1938f4a2013-03-11 06:49:53 +0000545 * must relocate it. If it is embedded in the data section, then it
546 * will be relocated with other data.
547 */
548 if (gd->fdt_blob) {
549 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
550
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000551 gd->start_addr_sp -= gd->fdt_size;
552 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
Simon Glassa733b062013-04-26 02:53:43 +0000553 debug("Reserving %lu Bytes for FDT at: %08lx\n",
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000554 gd->fdt_size, gd->start_addr_sp);
Simon Glass1938f4a2013-03-11 06:49:53 +0000555 }
Siva Durga Prasad Paladugue9acb9e2015-12-03 15:46:03 +0100556#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000557
558 return 0;
559}
560
Simon Glass25e7dc62017-05-22 05:05:30 -0600561static int reserve_bootstage(void)
562{
563#ifdef CONFIG_BOOTSTAGE
564 int size = bootstage_get_size();
565
566 gd->start_addr_sp -= size;
567 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
568 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
569 gd->start_addr_sp);
570#endif
571
572 return 0;
573}
574
Patrick Delaunayd6f87712018-03-13 13:57:00 +0100575__weak int arch_reserve_stacks(void)
Andreas Bießmann68145d42015-02-06 23:06:45 +0100576{
577 return 0;
578}
579
Simon Glass1938f4a2013-03-11 06:49:53 +0000580static int reserve_stacks(void)
581{
Andreas Bießmann68145d42015-02-06 23:06:45 +0100582 /* make stack pointer 16-byte aligned */
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000583 gd->start_addr_sp -= 16;
584 gd->start_addr_sp &= ~0xf;
Simon Glass1938f4a2013-03-11 06:49:53 +0000585
586 /*
Simon Glass4c509342015-04-28 20:25:03 -0600587 * let the architecture-specific code tailor gd->start_addr_sp and
Andreas Bießmann68145d42015-02-06 23:06:45 +0100588 * gd->irq_sp
Simon Glass1938f4a2013-03-11 06:49:53 +0000589 */
Andreas Bießmann68145d42015-02-06 23:06:45 +0100590 return arch_reserve_stacks();
Simon Glass1938f4a2013-03-11 06:49:53 +0000591}
592
Simon Glassf0293d32018-11-15 18:43:52 -0700593static int reserve_bloblist(void)
594{
595#ifdef CONFIG_BLOBLIST
Simon Glass5074a8a2019-10-21 17:26:46 -0600596 gd->start_addr_sp &= ~0xf;
Simon Glassf0293d32018-11-15 18:43:52 -0700597 gd->start_addr_sp -= CONFIG_BLOBLIST_SIZE;
598 gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE);
599#endif
600
601 return 0;
602}
603
Simon Glass1938f4a2013-03-11 06:49:53 +0000604static int display_new_sp(void)
605{
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000606 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
Simon Glass1938f4a2013-03-11 06:49:53 +0000607
608 return 0;
609}
610
Vladimir Zapolskiye2099d72016-11-28 00:15:24 +0200611#if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
612 defined(CONFIG_SH)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000613static int setup_board_part1(void)
614{
615 bd_t *bd = gd->bd;
616
617 /*
618 * Save local variables to board info struct
619 */
Simon Glasse4fef6c2013-03-11 14:30:42 +0000620 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
621 bd->bi_memsize = gd->ram_size; /* size in bytes */
622
623#ifdef CONFIG_SYS_SRAM_BASE
624 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
625 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
626#endif
627
Heiko Schocher50258972017-06-07 17:33:11 +0200628#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000629 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
630#endif
Heiko Schocher064b55c2017-06-14 05:49:40 +0200631#if defined(CONFIG_M68K)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000632 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
633#endif
634#if defined(CONFIG_MPC83xx)
635 bd->bi_immrbar = CONFIG_SYS_IMMR;
636#endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000637
638 return 0;
639}
Daniel Schwierzeckfb3db632015-11-01 17:36:13 +0100640#endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000641
Daniel Schwierzeckfb3db632015-11-01 17:36:13 +0100642#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000643static int setup_board_part2(void)
644{
645 bd_t *bd = gd->bd;
646
647 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
648 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
649#if defined(CONFIG_CPM2)
650 bd->bi_cpmfreq = gd->arch.cpm_clk;
651 bd->bi_brgfreq = gd->arch.brg_clk;
652 bd->bi_sccfreq = gd->arch.scc_clk;
653 bd->bi_vco = gd->arch.vco_out;
654#endif /* CONFIG_CPM2 */
Alison Wang1313db42015-02-12 18:33:15 +0800655#if defined(CONFIG_M68K) && defined(CONFIG_PCI)
656 bd->bi_pcifreq = gd->pci_clk;
657#endif
658#if defined(CONFIG_EXTRA_CLOCK)
659 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
660 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
661 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
662#endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000663
664 return 0;
665}
666#endif
667
Simon Glass1938f4a2013-03-11 06:49:53 +0000668#ifdef CONFIG_POST
669static int init_post(void)
670{
671 post_bootmode_init();
672 post_run(NULL, POST_ROM | post_bootmode_get(0));
673
674 return 0;
675}
676#endif
677
Simon Glass1938f4a2013-03-11 06:49:53 +0000678static int reloc_fdt(void)
679{
Siva Durga Prasad Paladugue9acb9e2015-12-03 15:46:03 +0100680#ifndef CONFIG_OF_EMBED
Simon Glassf05ad9b2015-08-04 12:33:39 -0600681 if (gd->flags & GD_FLG_SKIP_RELOC)
682 return 0;
Simon Glass1938f4a2013-03-11 06:49:53 +0000683 if (gd->new_fdt) {
684 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
685 gd->fdt_blob = gd->new_fdt;
686 }
Siva Durga Prasad Paladugue9acb9e2015-12-03 15:46:03 +0100687#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000688
689 return 0;
690}
691
Simon Glass25e7dc62017-05-22 05:05:30 -0600692static int reloc_bootstage(void)
693{
694#ifdef CONFIG_BOOTSTAGE
695 if (gd->flags & GD_FLG_SKIP_RELOC)
696 return 0;
697 if (gd->new_bootstage) {
698 int size = bootstage_get_size();
699
700 debug("Copying bootstage from %p to %p, size %x\n",
701 gd->bootstage, gd->new_bootstage, size);
702 memcpy(gd->new_bootstage, gd->bootstage, size);
703 gd->bootstage = gd->new_bootstage;
Simon Glassac9cd482019-10-21 17:26:50 -0600704 bootstage_relocate();
Simon Glass25e7dc62017-05-22 05:05:30 -0600705 }
706#endif
707
708 return 0;
709}
710
Simon Glassf0293d32018-11-15 18:43:52 -0700711static int reloc_bloblist(void)
712{
713#ifdef CONFIG_BLOBLIST
714 if (gd->flags & GD_FLG_SKIP_RELOC)
715 return 0;
716 if (gd->new_bloblist) {
717 int size = CONFIG_BLOBLIST_SIZE;
718
719 debug("Copying bloblist from %p to %p, size %x\n",
720 gd->bloblist, gd->new_bloblist, size);
721 memcpy(gd->new_bloblist, gd->bloblist, size);
722 gd->bloblist = gd->new_bloblist;
723 }
724#endif
725
726 return 0;
727}
728
Simon Glass1938f4a2013-03-11 06:49:53 +0000729static int setup_reloc(void)
730{
Simon Glassf05ad9b2015-08-04 12:33:39 -0600731 if (gd->flags & GD_FLG_SKIP_RELOC) {
732 debug("Skipping relocation due to flag\n");
733 return 0;
734 }
735
Sonic Zhangd54d7eb2014-07-17 19:01:34 +0800736#ifdef CONFIG_SYS_TEXT_BASE
Lothar Waßmann53207bf2017-06-08 10:18:25 +0200737#ifdef ARM
738 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
739#elif defined(CONFIG_M68K)
angelo@sysam.ite310b932015-02-12 01:40:17 +0100740 /*
741 * On all ColdFire arch cpu, monitor code starts always
742 * just after the default vector table location, so at 0x400
743 */
744 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
Simon Glass001d1882019-04-08 13:20:41 -0600745#elif !defined(CONFIG_SANDBOX)
Lothar Waßmann53207bf2017-06-08 10:18:25 +0200746 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
angelo@sysam.ite310b932015-02-12 01:40:17 +0100747#endif
Sonic Zhangd54d7eb2014-07-17 19:01:34 +0800748#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000749 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
750
751 debug("Relocation Offset is: %08lx\n", gd->reloc_off);
Simon Glassa733b062013-04-26 02:53:43 +0000752 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000753 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
754 gd->start_addr_sp);
Simon Glass1938f4a2013-03-11 06:49:53 +0000755
756 return 0;
757}
758
mario.six@gdsys.cc2a792752017-02-22 16:07:22 +0100759#ifdef CONFIG_OF_BOARD_FIXUP
760static int fix_fdt(void)
761{
762 return board_fix_fdt((void *)gd->fdt_blob);
763}
764#endif
765
Simon Glass1938f4a2013-03-11 06:49:53 +0000766/* ARM calls relocate_code from its crt0.S */
Simon Glass530f27e2017-01-16 07:03:49 -0700767#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
768 !CONFIG_IS_ENABLED(X86_64)
Simon Glass1938f4a2013-03-11 06:49:53 +0000769
770static int jump_to_copy(void)
771{
Simon Glassf05ad9b2015-08-04 12:33:39 -0600772 if (gd->flags & GD_FLG_SKIP_RELOC)
773 return 0;
Simon Glass48a33802013-03-05 14:39:52 +0000774 /*
775 * x86 is special, but in a nice way. It uses a trampoline which
776 * enables the dcache if possible.
777 *
778 * For now, other archs use relocate_code(), which is implemented
779 * similarly for all archs. When we do generic relocation, hopefully
780 * we can make all archs enable the dcache prior to relocation.
781 */
Alexey Brodkin3fb80162015-02-24 19:40:36 +0300782#if defined(CONFIG_X86) || defined(CONFIG_ARC)
Simon Glass48a33802013-03-05 14:39:52 +0000783 /*
784 * SDRAM and console are now initialised. The final stack can now
785 * be setup in SDRAM. Code execution will continue in Flash, but
786 * with the stack in SDRAM and Global Data in temporary memory
787 * (CPU cache)
788 */
Simon Glassf0c7d9c2015-08-10 20:44:32 -0600789 arch_setup_gd(gd->new_gd);
Simon Glass48a33802013-03-05 14:39:52 +0000790 board_init_f_r_trampoline(gd->start_addr_sp);
791#else
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000792 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
Simon Glass48a33802013-03-05 14:39:52 +0000793#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000794
795 return 0;
796}
797#endif
798
799/* Record the board_init_f() bootstage (after arch_cpu_init()) */
Simon Glassb383d6c2017-05-22 05:05:25 -0600800static int initf_bootstage(void)
Simon Glass1938f4a2013-03-11 06:49:53 +0000801{
Simon Glassbaa7d342017-06-07 10:28:46 -0600802 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
803 IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
Simon Glassb383d6c2017-05-22 05:05:25 -0600804 int ret;
805
Simon Glass824bb1b2017-05-22 05:05:35 -0600806 ret = bootstage_init(!from_spl);
Simon Glassb383d6c2017-05-22 05:05:25 -0600807 if (ret)
808 return ret;
Simon Glass824bb1b2017-05-22 05:05:35 -0600809 if (from_spl) {
810 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
811 CONFIG_BOOTSTAGE_STASH_SIZE);
812
813 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
814 if (ret && ret != -ENOENT) {
815 debug("Failed to unstash bootstage: err=%d\n", ret);
816 return ret;
817 }
818 }
Simon Glassb383d6c2017-05-22 05:05:25 -0600819
Simon Glass1938f4a2013-03-11 06:49:53 +0000820 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
821
822 return 0;
823}
824
Simon Glass9854a872015-11-08 23:47:48 -0700825static int initf_console_record(void)
826{
Andy Yanf1896c42017-07-24 17:43:34 +0800827#if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
Simon Glass9854a872015-11-08 23:47:48 -0700828 return console_record_init();
829#else
830 return 0;
831#endif
832}
833
Simon Glassab7cd622014-07-23 06:55:04 -0600834static int initf_dm(void)
835{
Andy Yanf1896c42017-07-24 17:43:34 +0800836#if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
Simon Glassab7cd622014-07-23 06:55:04 -0600837 int ret;
838
Simon Glass63c5bf42017-05-22 05:05:32 -0600839 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
Simon Glassab7cd622014-07-23 06:55:04 -0600840 ret = dm_init_and_scan(true);
Simon Glass63c5bf42017-05-22 05:05:32 -0600841 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F);
Simon Glassab7cd622014-07-23 06:55:04 -0600842 if (ret)
843 return ret;
844#endif
Simon Glass1057e6c2016-02-24 09:14:50 -0700845#ifdef CONFIG_TIMER_EARLY
846 ret = dm_timer_init();
847 if (ret)
848 return ret;
849#endif
Simon Glassab7cd622014-07-23 06:55:04 -0600850
851 return 0;
852}
853
Simon Glass146251f2015-01-19 22:16:12 -0700854/* Architecture-specific memory reservation */
855__weak int reserve_arch(void)
856{
857 return 0;
858}
859
Simon Glassd4c671c2015-03-05 12:25:16 -0700860__weak int arch_cpu_init_dm(void)
861{
862 return 0;
863}
864
Simon Glass4acff452017-01-16 07:03:50 -0700865static const init_fnc_t init_sequence_f[] = {
Simon Glass1938f4a2013-03-11 06:49:53 +0000866 setup_mon_len,
Simon Glassb45122f2015-02-27 22:06:34 -0700867#ifdef CONFIG_OF_CONTROL
Simon Glass08793612015-02-27 22:06:35 -0700868 fdtdec_setup,
Simon Glassb45122f2015-02-27 22:06:34 -0700869#endif
Heinrich Schuchardt7ef8e9b2019-06-02 00:53:24 +0200870#ifdef CONFIG_TRACE_EARLY
Simon Glass71c52db2013-06-11 11:14:42 -0700871 trace_early_init,
Kevin Hilmand2107182014-12-09 15:03:58 -0800872#endif
Simon Glass768e0f52014-11-10 18:00:18 -0700873 initf_malloc,
Simon Glassaf1bc0c2017-12-04 13:48:28 -0700874 log_init,
Simon Glass5ac44a52017-05-22 05:05:31 -0600875 initf_bootstage, /* uses its own timer, so does not need DM */
Simon Glassf0293d32018-11-15 18:43:52 -0700876#ifdef CONFIG_BLOBLIST
877 bloblist_init,
878#endif
Simon Glassb0edea32018-11-15 18:44:09 -0700879 setup_spl_handoff,
Simon Glass9854a872015-11-08 23:47:48 -0700880 initf_console_record,
Simon Glass671549e2017-03-28 10:27:18 -0600881#if defined(CONFIG_HAVE_FSP)
882 arch_fsp_init,
Bin Menga52a068e2015-08-20 06:40:18 -0700883#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000884 arch_cpu_init, /* basic arch cpu dependent setup */
Paul Burton8ebf5062016-09-21 11:18:46 +0100885 mach_cpu_init, /* SoC/machine dependent CPU setup */
Simon Glass3ea09532014-09-03 17:36:59 -0600886 initf_dm,
Simon Glassd4c671c2015-03-05 12:25:16 -0700887 arch_cpu_init_dm,
Simon Glass1938f4a2013-03-11 06:49:53 +0000888#if defined(CONFIG_BOARD_EARLY_INIT_F)
889 board_early_init_f,
890#endif
Simon Glass727e94a2017-03-28 10:27:26 -0600891#if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
Simon Glassc252c062017-03-28 10:27:19 -0600892 /* get CPU and bus clocks according to the environment variable */
Simon Glasse4fef6c2013-03-11 14:30:42 +0000893 get_clocks, /* get CPU and bus clocks (etc.) */
Simon Glass1793e782017-03-28 10:27:23 -0600894#endif
Angelo Dureghello0ce45282017-05-10 23:58:06 +0200895#if !defined(CONFIG_M68K)
Simon Glass1938f4a2013-03-11 06:49:53 +0000896 timer_init, /* initialize timer */
Angelo Dureghello0ce45282017-05-10 23:58:06 +0200897#endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000898#if defined(CONFIG_BOARD_POSTCLK_INIT)
899 board_postclk_init,
900#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000901 env_init, /* initialize environment */
902 init_baud_rate, /* initialze baudrate settings */
903 serial_init, /* serial communications setup */
904 console_init_f, /* stage 1 init of console */
905 display_options, /* say that we are here */
906 display_text_info, /* show debugging info if required */
Angelo Dureghellob9153fe32017-08-20 00:01:55 +0200907#if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000908 checkcpu,
909#endif
Mario Six23471ae2018-08-06 10:23:34 +0200910#if defined(CONFIG_SYSRESET)
911 print_resetinfo,
912#endif
Simon Glasscc664002017-01-23 13:31:25 -0700913#if defined(CONFIG_DISPLAY_CPUINFO)
Simon Glass1938f4a2013-03-11 06:49:53 +0000914 print_cpuinfo, /* display cpu info (and speed) */
Simon Glasscc664002017-01-23 13:31:25 -0700915#endif
Cooper Jr., Franklinaf9e6ad2017-06-16 17:25:12 -0500916#if defined(CONFIG_DTB_RESELECT)
917 embedded_dtb_select,
918#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000919#if defined(CONFIG_DISPLAY_BOARDINFO)
Masahiro Yamada0365ffc2015-01-14 17:07:05 +0900920 show_board_info,
Simon Glass1938f4a2013-03-11 06:49:53 +0000921#endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000922 INIT_FUNC_WATCHDOG_INIT
923#if defined(CONFIG_MISC_INIT_F)
924 misc_init_f,
925#endif
926 INIT_FUNC_WATCHDOG_RESET
Simon Glass69153982017-05-12 21:09:56 -0600927#if defined(CONFIG_SYS_I2C)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000928 init_func_i2c,
929#endif
Rajesh Bhagat1fab98f2018-01-17 16:13:08 +0530930#if defined(CONFIG_VID) && !defined(CONFIG_SPL)
931 init_func_vid,
932#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000933 announce_dram_init,
Simon Glass1938f4a2013-03-11 06:49:53 +0000934 dram_init, /* configure available RAM banks */
Simon Glasse4fef6c2013-03-11 14:30:42 +0000935#ifdef CONFIG_POST
936 post_init_f,
937#endif
938 INIT_FUNC_WATCHDOG_RESET
939#if defined(CONFIG_SYS_DRAM_TEST)
940 testdram,
941#endif /* CONFIG_SYS_DRAM_TEST */
942 INIT_FUNC_WATCHDOG_RESET
943
Simon Glass1938f4a2013-03-11 06:49:53 +0000944#ifdef CONFIG_POST
945 init_post,
946#endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000947 INIT_FUNC_WATCHDOG_RESET
Simon Glass1938f4a2013-03-11 06:49:53 +0000948 /*
949 * Now that we have DRAM mapped and working, we can
950 * relocate the code and continue running from DRAM.
951 *
952 * Reserve memory at end of RAM for (top down in that order):
953 * - area that won't get touched by U-Boot and Linux (optional)
954 * - kernel log buffer
955 * - protected RAM
956 * - LCD framebuffer
957 * - monitor code
958 * - board info struct
959 */
960 setup_dest_addr,
Simon Glass1938f4a2013-03-11 06:49:53 +0000961#ifdef CONFIG_PRAM
962 reserve_pram,
963#endif
964 reserve_round_4k,
Simon Glass80d4bcd2017-03-31 08:40:29 -0600965#ifdef CONFIG_ARM
Simon Glass1938f4a2013-03-11 06:49:53 +0000966 reserve_mmu,
967#endif
Simon Glass5a541942016-01-18 19:52:21 -0700968 reserve_video,
Simon Glass8703ef32016-01-18 19:52:20 -0700969 reserve_trace,
Simon Glass1938f4a2013-03-11 06:49:53 +0000970 reserve_uboot,
971 reserve_malloc,
972 reserve_board,
Simon Glass1938f4a2013-03-11 06:49:53 +0000973 setup_machine,
974 reserve_global_data,
975 reserve_fdt,
Simon Glass25e7dc62017-05-22 05:05:30 -0600976 reserve_bootstage,
Simon Glassf0293d32018-11-15 18:43:52 -0700977 reserve_bloblist,
Simon Glass146251f2015-01-19 22:16:12 -0700978 reserve_arch,
Simon Glass1938f4a2013-03-11 06:49:53 +0000979 reserve_stacks,
Simon Glass76b00ac2017-03-31 08:40:32 -0600980 dram_init_banksize,
Simon Glass1938f4a2013-03-11 06:49:53 +0000981 show_dram_config,
Vladimir Zapolskiye2099d72016-11-28 00:15:24 +0200982#if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
983 defined(CONFIG_SH)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000984 setup_board_part1,
Daniel Schwierzeckfb3db632015-11-01 17:36:13 +0100985#endif
986#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000987 INIT_FUNC_WATCHDOG_RESET
988 setup_board_part2,
989#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000990 display_new_sp,
mario.six@gdsys.cc2a792752017-02-22 16:07:22 +0100991#ifdef CONFIG_OF_BOARD_FIXUP
992 fix_fdt,
993#endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000994 INIT_FUNC_WATCHDOG_RESET
Simon Glass1938f4a2013-03-11 06:49:53 +0000995 reloc_fdt,
Simon Glass25e7dc62017-05-22 05:05:30 -0600996 reloc_bootstage,
Simon Glassf0293d32018-11-15 18:43:52 -0700997 reloc_bloblist,
Simon Glass1938f4a2013-03-11 06:49:53 +0000998 setup_reloc,
Alexey Brodkin3fb80162015-02-24 19:40:36 +0300999#if defined(CONFIG_X86) || defined(CONFIG_ARC)
Simon Glass313aef32015-01-01 16:18:09 -07001000 copy_uboot_to_ram,
Simon Glass313aef32015-01-01 16:18:09 -07001001 do_elf_reloc_fixups,
Simon Glass6bda55a2017-01-16 07:03:52 -07001002 clear_bss,
Simon Glass313aef32015-01-01 16:18:09 -07001003#endif
Chris Zankelde5e5ce2016-08-10 18:36:43 +03001004#if defined(CONFIG_XTENSA)
1005 clear_bss,
1006#endif
Simon Glass530f27e2017-01-16 07:03:49 -07001007#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
1008 !CONFIG_IS_ENABLED(X86_64)
Simon Glass1938f4a2013-03-11 06:49:53 +00001009 jump_to_copy,
1010#endif
1011 NULL,
1012};
1013
1014void board_init_f(ulong boot_flags)
1015{
Simon Glass1938f4a2013-03-11 06:49:53 +00001016 gd->flags = boot_flags;
Alexey Brodkin9aed5a22013-11-27 22:32:40 +04001017 gd->have_console = 0;
Simon Glass1938f4a2013-03-11 06:49:53 +00001018
1019 if (initcall_run_list(init_sequence_f))
1020 hang();
1021
Ben Stoltz9b217492015-07-31 09:31:37 -06001022#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
Alexey Brodkin264d2982015-12-16 19:24:10 +03001023 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
1024 !defined(CONFIG_ARC)
Simon Glass1938f4a2013-03-11 06:49:53 +00001025 /* NOTREACHED - jump_to_copy() does not return */
1026 hang();
1027#endif
1028}
1029
Alexey Brodkin3fb80162015-02-24 19:40:36 +03001030#if defined(CONFIG_X86) || defined(CONFIG_ARC)
Simon Glass48a33802013-03-05 14:39:52 +00001031/*
1032 * For now this code is only used on x86.
1033 *
1034 * init_sequence_f_r is the list of init functions which are run when
1035 * U-Boot is executing from Flash with a semi-limited 'C' environment.
1036 * The following limitations must be considered when implementing an
1037 * '_f_r' function:
1038 * - 'static' variables are read-only
1039 * - Global Data (gd->xxx) is read/write
1040 *
1041 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
1042 * supported). It _should_, if possible, copy global data to RAM and
1043 * initialise the CPU caches (to speed up the relocation process)
1044 *
1045 * NOTE: At present only x86 uses this route, but it is intended that
1046 * all archs will move to this when generic relocation is implemented.
1047 */
Simon Glass4acff452017-01-16 07:03:50 -07001048static const init_fnc_t init_sequence_f_r[] = {
Simon Glass530f27e2017-01-16 07:03:49 -07001049#if !CONFIG_IS_ENABLED(X86_64)
Simon Glass48a33802013-03-05 14:39:52 +00001050 init_cache_f_r,
Simon Glass530f27e2017-01-16 07:03:49 -07001051#endif
Simon Glass48a33802013-03-05 14:39:52 +00001052
1053 NULL,
1054};
1055
1056void board_init_f_r(void)
1057{
1058 if (initcall_run_list(init_sequence_f_r))
1059 hang();
1060
1061 /*
Simon Glasse4d6ab02016-03-11 22:06:51 -07001062 * The pre-relocation drivers may be using memory that has now gone
1063 * away. Mark serial as unavailable - this will fall back to the debug
1064 * UART if available.
Simon Glassaf1bc0c2017-12-04 13:48:28 -07001065 *
1066 * Do the same with log drivers since the memory may not be available.
Simon Glasse4d6ab02016-03-11 22:06:51 -07001067 */
Simon Glassaf1bc0c2017-12-04 13:48:28 -07001068 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
Simon Glass5ee94b42017-09-05 19:49:45 -06001069#ifdef CONFIG_TIMER
1070 gd->timer = NULL;
1071#endif
Simon Glasse4d6ab02016-03-11 22:06:51 -07001072
1073 /*
Simon Glass48a33802013-03-05 14:39:52 +00001074 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
1075 * Transfer execution from Flash to RAM by calculating the address
1076 * of the in-RAM copy of board_init_r() and calling it
1077 */
Alexey Brodkin7bf9f202015-02-25 17:59:02 +03001078 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
Simon Glass48a33802013-03-05 14:39:52 +00001079
1080 /* NOTREACHED - board_init_r() does not return */
1081 hang();
1082}
Alexey Brodkin5bcd19a2015-03-24 11:12:47 +03001083#endif /* CONFIG_X86 */