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stroese071d8972003-05-23 11:35:47 +00001/*
2 * (C) Copyright 2001-2003
Stefan Roese2076d0a2006-01-18 20:03:15 +01003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Matthias Fuchs2f6eb912009-02-15 22:27:47 +01005 * (C) Copyright 2005-2009
Stefan Roese2076d0a2006-01-18 20:03:15 +01006 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
stroese071d8972003-05-23 11:35:47 +00007 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <asm/processor.h>
Matthias Fuchs2f6eb912009-02-15 22:27:47 +010029#include <asm/io.h>
stroese071d8972003-05-23 11:35:47 +000030#include <command.h>
stroese071d8972003-05-23 11:35:47 +000031#include <malloc.h>
32
Wolfgang Denkd87080b2006-03-31 18:32:53 +020033DECLARE_GLOBAL_DATA_PTR;
stroese071d8972003-05-23 11:35:47 +000034
stroese4510a7b2004-12-16 18:40:02 +000035extern void lxt971_no_sleep(void);
36
wdenkc837dcb2004-01-20 23:12:12 +000037int board_early_init_f (void)
stroese071d8972003-05-23 11:35:47 +000038{
39 /*
40 * IRQ 0-15 405GP internally generated; active high; level sensitive
41 * IRQ 16 405GP internally generated; active low; level sensitive
42 * IRQ 17-24 RESERVED
43 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
44 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
45 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
46 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
47 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
48 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
49 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
50 */
Stefan Roese952e7762009-09-24 09:55:50 +020051 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
52 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
53 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
54 mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
55 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
56 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */
57 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
stroese071d8972003-05-23 11:35:47 +000058
59 /*
Matthias Fuchsc553b5f2009-02-15 22:26:54 +010060 * EBC Configuration Register:
61 * set ready timeout to 512 ebc-clks -> ca. 15 us
stroese071d8972003-05-23 11:35:47 +000062 */
Stefan Roesed1c3b272009-09-09 16:25:29 +020063 mtebc (EBC0_CFG, 0xa8400000);
stroese071d8972003-05-23 11:35:47 +000064
stroese4510a7b2004-12-16 18:40:02 +000065 /*
Stefan Roese2076d0a2006-01-18 20:03:15 +010066 * Setup GPIO pins
stroese4510a7b2004-12-16 18:40:02 +000067 */
Stefan Roesed1c3b272009-09-09 16:25:29 +020068 mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_FPGA_INIT |
Stefan Roesef50fe4b2009-02-18 14:05:37 +010069 CONFIG_SYS_FPGA_DONE |
70 CONFIG_SYS_XEREADY |
71 CONFIG_SYS_NONMONARCH |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072 CONFIG_SYS_REV1_2) << 5));
Stefan Roese2076d0a2006-01-18 20:03:15 +010073
Stefan Roesef50fe4b2009-02-18 14:05:37 +010074 if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) {
Stefan Roese2076d0a2006-01-18 20:03:15 +010075 /* rev 1.2 boards */
Stefan Roesed1c3b272009-09-09 16:25:29 +020076 mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_INTA_FAKE |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077 CONFIG_SYS_SELF_RST) << 5));
Stefan Roese2076d0a2006-01-18 20:03:15 +010078 }
79
Stefan Roesef50fe4b2009-02-18 14:05:37 +010080 out_be32((void *)GPIO0_OR, CONFIG_SYS_VPEN);
Matthias Fuchsc553b5f2009-02-15 22:26:54 +010081 /* setup for output */
Stefan Roesef50fe4b2009-02-18 14:05:37 +010082 out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK |
83 CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN);
Stefan Roese2076d0a2006-01-18 20:03:15 +010084
Matthias Fuchsc553b5f2009-02-15 22:26:54 +010085 /*
86 * - check if rev1_2 is low, then:
87 * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST
88 * in TCR to assert INTA# or SELFRST#
stroese4510a7b2004-12-16 18:40:02 +000089 */
stroese071d8972003-05-23 11:35:47 +000090 return 0;
91}
92
stroese071d8972003-05-23 11:35:47 +000093int misc_init_r (void)
94{
stroese4510a7b2004-12-16 18:40:02 +000095 /* adjust flash start and offset */
96 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
97 gd->bd->bi_flashoffset = 0;
98
Matthias Fuchsc553b5f2009-02-15 22:26:54 +010099 /* deassert EREADY# */
Stefan Roesef50fe4b2009-02-18 14:05:37 +0100100 out_be32((void *)GPIO0_OR,
101 in_be32((void *)GPIO0_OR) | CONFIG_SYS_XEREADY);
stroese071d8972003-05-23 11:35:47 +0000102 return (0);
103}
104
Stefan Roese2076d0a2006-01-18 20:03:15 +0100105ushort pmc405_pci_subsys_deviceid(void)
106{
107 ulong val;
Stefan Roesef50fe4b2009-02-18 14:05:37 +0100108
109 val = in_be32((void *)GPIO0_IR);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110 if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100111 /* check monarch# signal */
112 if (val & CONFIG_SYS_NONMONARCH)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113 return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114 return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH;
Stefan Roese2076d0a2006-01-18 20:03:15 +0100115 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116 return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
Stefan Roese2076d0a2006-01-18 20:03:15 +0100117}
stroese071d8972003-05-23 11:35:47 +0000118
119/*
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100120 * Check Board Identity
stroese071d8972003-05-23 11:35:47 +0000121 */
stroese071d8972003-05-23 11:35:47 +0000122int checkboard (void)
123{
Stefan Roese2076d0a2006-01-18 20:03:15 +0100124 ulong val;
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200125 char str[64];
Stefan Roesef50fe4b2009-02-18 14:05:37 +0100126 int i = getenv_r("serial#", str, sizeof(str));
stroese071d8972003-05-23 11:35:47 +0000127
128 puts ("Board: ");
129
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100130 if (i == -1)
stroeseef9e8682003-09-12 08:46:58 +0000131 puts ("### No HW ID - assuming PMC405");
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100132 else
stroese071d8972003-05-23 11:35:47 +0000133 puts(str);
stroese071d8972003-05-23 11:35:47 +0000134
Stefan Roesef50fe4b2009-02-18 14:05:37 +0100135 val = in_be32((void *)GPIO0_IR);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136 if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
Stefan Roese2076d0a2006-01-18 20:03:15 +0100137 puts(" rev1.2 (");
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100138 if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */
Stefan Roese2076d0a2006-01-18 20:03:15 +0100139 puts("non-");
Stefan Roese2076d0a2006-01-18 20:03:15 +0100140 puts("monarch)");
Matthias Fuchsc553b5f2009-02-15 22:26:54 +0100141 } else
Stefan Roese2076d0a2006-01-18 20:03:15 +0100142 puts(" <=rev1.1");
stroese071d8972003-05-23 11:35:47 +0000143
Stefan Roese2076d0a2006-01-18 20:03:15 +0100144 putc ('\n');
stroese4510a7b2004-12-16 18:40:02 +0000145
stroese071d8972003-05-23 11:35:47 +0000146 return 0;
147}
148
Stefan Roese2076d0a2006-01-18 20:03:15 +0100149void reset_phy(void)
stroese071d8972003-05-23 11:35:47 +0000150{
Stefan Roese2076d0a2006-01-18 20:03:15 +0100151#ifdef CONFIG_LXT971_NO_SLEEP
stroese071d8972003-05-23 11:35:47 +0000152
Stefan Roese2076d0a2006-01-18 20:03:15 +0100153 /*
154 * Disable sleep mode in LXT971
155 */
156 lxt971_no_sleep();
157#endif
stroese071d8972003-05-23 11:35:47 +0000158}