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Michael Schwingenea99e8f2008-01-16 19:50:37 +01001/*
2 * (C) Copyright 2007
3 * Michael Schwingen, michael@schwingen.org
4 *
5 * Configuration settings for the AcTux-1 board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
Michael Schwingenea99e8f2008-01-16 19:50:37 +010029#define CONFIG_IXP425 1
30#define CONFIG_ACTUX1 1
31
Marek Vasut8e807ec2012-03-06 00:45:35 +010032#define CONFIG_MACH_TYPE 1479
33
Michael Schwingenea99e8f2008-01-16 19:50:37 +010034#define CONFIG_DISPLAY_CPUINFO 1
35#define CONFIG_DISPLAY_BOARDINFO 1
36
Jean-Christophe PLAGNIOL-VILLARD930590f2009-01-31 09:10:48 +010037#define CONFIG_IXP_SERIAL
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2
Michael Schwingenea99e8f2008-01-16 19:50:37 +010039#define CONFIG_BAUDRATE 115200
40#define CONFIG_BOOTDELAY 3
41#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
Michael Schwingen517c5df2011-05-23 00:00:04 +020042#define CONFIG_BOARD_EARLY_INIT_F 1
43#define CONFIG_SYS_LDSCRIPT "board/actux1/u-boot.lds"
Michael Schwingenea99e8f2008-01-16 19:50:37 +010044
45/***************************************************************
46 * U-boot generic defines start here.
47 ***************************************************************/
Michael Schwingenea99e8f2008-01-16 19:50:37 +010048/*
49 * Size of malloc() pool
50 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
Michael Schwingenea99e8f2008-01-16 19:50:37 +010052
53/* allow to overwrite serial and ethaddr */
54#define CONFIG_ENV_OVERWRITE
55
56/* Command line configuration. */
57#include <config_cmd_default.h>
58
59#define CONFIG_CMD_ELF
Michael Schwingen517c5df2011-05-23 00:00:04 +020060#ifdef CONFIG_PCI
61#define CONFIG_CMD_PCI
62#define CONFIG_PCI_PNP
63#define CONFIG_IXP_PCI
64#define CONFIG_PCI_SCAN_SHOW
65#define CONFIG_CMD_PCI_ENUM
66#endif
Michael Schwingenea99e8f2008-01-16 19:50:37 +010067
68#define CONFIG_BOOTCOMMAND "run boot_flash"
69/* enable passing of ATAGs */
70#define CONFIG_CMDLINE_TAG 1
71#define CONFIG_SETUP_MEMORY_TAGS 1
72#define CONFIG_INITRD_TAG 1
73#define CONFIG_REVISION_TAG 1
74
75#if defined(CONFIG_CMD_KGDB)
76# define CONFIG_KGDB_BAUDRATE 230400
77/* which serial port to use */
78# define CONFIG_KGDB_SER_INDEX 1
79#endif
80
81/* Miscellaneous configurable options */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_LONGHELP
83#define CONFIG_SYS_PROMPT "=> "
Michael Schwingenea99e8f2008-01-16 19:50:37 +010084/* Console I/O Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_CBSIZE 256
Michael Schwingenea99e8f2008-01-16 19:50:37 +010086/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
Michael Schwingenea99e8f2008-01-16 19:50:37 +010088/* max number of command args */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_MAXARGS 16
Michael Schwingenea99e8f2008-01-16 19:50:37 +010090/* Boot Argument Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Michael Schwingenea99e8f2008-01-16 19:50:37 +010092
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_MEMTEST_START 0x00400000
94#define CONFIG_SYS_MEMTEST_END 0x00800000
Michael Schwingenea99e8f2008-01-16 19:50:37 +010095
Michael Schwingen517c5df2011-05-23 00:00:04 +020096/* timer clock - 2* OSC_IN system clock */
97#define CONFIG_IXP425_TIMER_CLK 66666666
98#define CONFIG_SYS_HZ 1000
Michael Schwingenea99e8f2008-01-16 19:50:37 +010099
100/* default load address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_LOAD_ADDR 0x00010000
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100102
103/* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100105 115200, 230400 }
106#define CONFIG_SERIAL_RTS_ACTIVE 1
107
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100108/* Expansion bus settings */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_EXP_CS0 0xbd113842
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100110
111/* SDRAM settings */
112#define CONFIG_NR_DRAM_BANKS 1
113#define PHYS_SDRAM_1 0x00000000
Michael Schwingen517c5df2011-05-23 00:00:04 +0200114#define CONFIG_SYS_SDRAM_BASE 0x00000000
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100115
Michael Schwingen517c5df2011-05-23 00:00:04 +0200116#ifdef CONFIG_RAM_32MB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117# define CONFIG_SYS_SDR_CONFIG 0x18
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100118# define PHYS_SDRAM_1_SIZE 0x02000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
120# define CONFIG_SYS_SDR_MODE_CONFIG 0x1
121# define CONFIG_SYS_DRAM_SIZE 0x02000000
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100122#else /* 16MB SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123# define CONFIG_SYS_SDR_CONFIG 0x3A
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100124# define PHYS_SDRAM_1_SIZE 0x01000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
126# define CONFIG_SYS_SDR_MODE_CONFIG 0x1
127# define CONFIG_SYS_DRAM_SIZE 0x01000000
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100128#endif
129
130/* FLASH organization */
Michael Schwingen517c5df2011-05-23 00:00:04 +0200131#define CONFIG_SYS_TEXT_BASE 0x50000000
132#ifdef CONFIG_FLASH2X2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133# define CONFIG_SYS_MAX_FLASH_BANKS 2
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100134/* max number of sectors on one chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135# define CONFIG_SYS_MAX_FLASH_SECT 40
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100136# define PHYS_FLASH_1 0x50000000
137# define PHYS_FLASH_2 0x50200000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100139#endif
Michael Schwingen517c5df2011-05-23 00:00:04 +0200140#ifdef CONFIG_FLASH1X8
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141# define CONFIG_SYS_MAX_FLASH_BANKS 1
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100142/* max number of sectors on one chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143# define CONFIG_SYS_MAX_FLASH_SECT 140
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100144# define PHYS_FLASH_1 0x50000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100146#endif
147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
149#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
150#define CONFIG_SYS_MONITOR_LEN (256 << 10)
Michael Schwingen517c5df2011-05-23 00:00:04 +0200151#define CONFIG_BOARD_SIZE_LIMIT 262144
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100152
153/* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200155#define CONFIG_FLASH_CFI_DRIVER
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100156/* no byte writes on IXP4xx */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100158/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_FLASH_EMPTY_INFO
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100160
161/* Ethernet */
162
163/* include IXP4xx NPE support */
164#define CONFIG_IXP4XX_NPE 1
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100165/* NPE0 PHY address */
166#define CONFIG_PHY_ADDR 0
Michael Schwingen517c5df2011-05-23 00:00:04 +0200167/* NPE1 PHY address (HW Release E only) */
168#define CONFIG_PHY1_ADDR 1
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100169/* MII PHY management */
170#define CONFIG_MII 1
171/* Number of ethernet rx buffers & descriptors */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_RX_ETH_BUFFER 16
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100173#define CONFIG_RESET_PHY_R 1
174
Michael Schwingen517c5df2011-05-23 00:00:04 +0200175#define CONFIG_HAS_ETH1 1
176
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100177#define CONFIG_CMD_DHCP
178#define CONFIG_CMD_NET
179#define CONFIG_CMD_MII
180#define CONFIG_CMD_PING
181#undef CONFIG_CMD_NFS
182
183/* BOOTP options */
184#define CONFIG_BOOTP_BOOTFILESIZE
185#define CONFIG_BOOTP_BOOTPATH
186#define CONFIG_BOOTP_GATEWAY
187#define CONFIG_BOOTP_HOSTNAME
188
189/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_CACHELINE_SIZE 32
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100191
192/*
193 * environment organization:
194 * one flash sector, embedded in uboot area (bottom bootblock flash)
195 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200196#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200197#define CONFIG_ENV_SIZE 0x2000
198#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_USE_PPCENV 1
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100200
Michael Schwingen517c5df2011-05-23 00:00:04 +0200201#define CONFIG_EXTRA_ENV_SETTINGS \
Jean-Christophe PLAGNIOL-VILLARDb4e2f892009-01-31 09:53:39 +0100202 "npe_ucode=50040000\0" \
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100203 "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
204 "kerneladdr=50050000\0" \
Michael Schwingen517c5df2011-05-23 00:00:04 +0200205 "kernelfile=actux1/uImage\0" \
206 "rootfile=actux1/rootfs\0" \
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100207 "rootaddr=50170000\0" \
208 "loadaddr=10000\0" \
209 "updateboot_ser=mw.b 10000 ff 40000;" \
210 " loady ${loadaddr};" \
211 " run eraseboot writeboot\0" \
212 "updateboot_net=mw.b 10000 ff 40000;" \
Michael Schwingen517c5df2011-05-23 00:00:04 +0200213 " tftp ${loadaddr} actux1/u-boot.bin;" \
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100214 " run eraseboot writeboot\0" \
215 "eraseboot=protect off 50000000 50003fff;" \
216 " protect off 50006000 5003ffff;" \
217 " erase 50000000 50003fff;" \
218 " erase 50006000 5003ffff\0" \
219 "writeboot=cp.b 10000 50000000 4000;" \
220 " cp.b 16000 50006000 3a000\0" \
Michael Schwingen517c5df2011-05-23 00:00:04 +0200221 "updateucode=loady;" \
222 " era ${npe_ucode} +${filesize};" \
223 " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100224 "updateroot=tftp ${loadaddr} ${rootfile};" \
225 " era ${rootaddr} +${filesize};" \
226 " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
227 "updatekern=tftp ${loadaddr} ${kernelfile};" \
228 " era ${kerneladdr} +${filesize};" \
229 " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
230 "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
231 " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
232 "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
233 " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
Michael Schwingen517c5df2011-05-23 00:00:04 +0200234 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100235 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
236 "boot_flash=run flashargs addtty addeth;" \
237 " bootm ${kerneladdr}\0" \
238 "boot_net=run netargs addtty addeth;" \
239 " tftpboot ${loadaddr} ${kernelfile};" \
240 " bootm\0"
241
Michael Schwingen517c5df2011-05-23 00:00:04 +0200242/* additions for new relocation code, must be added to all boards */
243#define CONFIG_SYS_INIT_SP_ADDR \
244 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
245
Michael Schwingenea99e8f2008-01-16 19:50:37 +0100246#endif /* __CONFIG_H */