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Allen Martin77c42e82013-03-16 18:58:13 +00001/*
2 * NVIDIA Tegra SPI controller (T114 and later)
3 *
4 * Copyright (c) 2010-2013 NVIDIA Corporation
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
Simon Glassfda6fac2014-10-13 23:42:13 -060025#include <dm.h>
Allen Martin77c42e82013-03-16 18:58:13 +000026#include <asm/io.h>
Allen Martin77c42e82013-03-16 18:58:13 +000027#include <asm/arch/clock.h>
28#include <asm/arch-tegra/clk_rst.h>
Allen Martin77c42e82013-03-16 18:58:13 +000029#include <spi.h>
30#include <fdtdec.h>
Simon Glassfda6fac2014-10-13 23:42:13 -060031#include "tegra_spi.h"
Allen Martin77c42e82013-03-16 18:58:13 +000032
33DECLARE_GLOBAL_DATA_PTR;
34
35/* COMMAND1 */
36#define SPI_CMD1_GO (1 << 31)
37#define SPI_CMD1_M_S (1 << 30)
38#define SPI_CMD1_MODE_MASK 0x3
39#define SPI_CMD1_MODE_SHIFT 28
40#define SPI_CMD1_CS_SEL_MASK 0x3
41#define SPI_CMD1_CS_SEL_SHIFT 26
42#define SPI_CMD1_CS_POL_INACTIVE3 (1 << 25)
43#define SPI_CMD1_CS_POL_INACTIVE2 (1 << 24)
44#define SPI_CMD1_CS_POL_INACTIVE1 (1 << 23)
45#define SPI_CMD1_CS_POL_INACTIVE0 (1 << 22)
46#define SPI_CMD1_CS_SW_HW (1 << 21)
47#define SPI_CMD1_CS_SW_VAL (1 << 20)
48#define SPI_CMD1_IDLE_SDA_MASK 0x3
49#define SPI_CMD1_IDLE_SDA_SHIFT 18
50#define SPI_CMD1_BIDIR (1 << 17)
51#define SPI_CMD1_LSBI_FE (1 << 16)
52#define SPI_CMD1_LSBY_FE (1 << 15)
53#define SPI_CMD1_BOTH_EN_BIT (1 << 14)
54#define SPI_CMD1_BOTH_EN_BYTE (1 << 13)
55#define SPI_CMD1_RX_EN (1 << 12)
56#define SPI_CMD1_TX_EN (1 << 11)
57#define SPI_CMD1_PACKED (1 << 5)
58#define SPI_CMD1_BIT_LEN_MASK 0x1F
59#define SPI_CMD1_BIT_LEN_SHIFT 0
60
61/* COMMAND2 */
62#define SPI_CMD2_TX_CLK_TAP_DELAY (1 << 6)
63#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6)
64#define SPI_CMD2_RX_CLK_TAP_DELAY (1 << 0)
65#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0)
66
67/* TRANSFER STATUS */
68#define SPI_XFER_STS_RDY (1 << 30)
69
70/* FIFO STATUS */
71#define SPI_FIFO_STS_CS_INACTIVE (1 << 31)
72#define SPI_FIFO_STS_FRAME_END (1 << 30)
73#define SPI_FIFO_STS_RX_FIFO_FLUSH (1 << 15)
74#define SPI_FIFO_STS_TX_FIFO_FLUSH (1 << 14)
75#define SPI_FIFO_STS_ERR (1 << 8)
76#define SPI_FIFO_STS_TX_FIFO_OVF (1 << 7)
77#define SPI_FIFO_STS_TX_FIFO_UNR (1 << 6)
78#define SPI_FIFO_STS_RX_FIFO_OVF (1 << 5)
79#define SPI_FIFO_STS_RX_FIFO_UNR (1 << 4)
80#define SPI_FIFO_STS_TX_FIFO_FULL (1 << 3)
81#define SPI_FIFO_STS_TX_FIFO_EMPTY (1 << 2)
82#define SPI_FIFO_STS_RX_FIFO_FULL (1 << 1)
83#define SPI_FIFO_STS_RX_FIFO_EMPTY (1 << 0)
84
85#define SPI_TIMEOUT 1000
86#define TEGRA_SPI_MAX_FREQ 52000000
87
88struct spi_regs {
89 u32 command1; /* 000:SPI_COMMAND1 register */
90 u32 command2; /* 004:SPI_COMMAND2 register */
91 u32 timing1; /* 008:SPI_CS_TIM1 register */
92 u32 timing2; /* 00c:SPI_CS_TIM2 register */
93 u32 xfer_status;/* 010:SPI_TRANS_STATUS register */
94 u32 fifo_status;/* 014:SPI_FIFO_STATUS register */
95 u32 tx_data; /* 018:SPI_TX_DATA register */
96 u32 rx_data; /* 01c:SPI_RX_DATA register */
97 u32 dma_ctl; /* 020:SPI_DMA_CTL register */
98 u32 dma_blk; /* 024:SPI_DMA_BLK register */
99 u32 rsvd[56]; /* 028-107 reserved */
100 u32 tx_fifo; /* 108:SPI_FIFO1 register */
101 u32 rsvd2[31]; /* 10c-187 reserved */
102 u32 rx_fifo; /* 188:SPI_FIFO2 register */
103 u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */
104};
105
Simon Glassfda6fac2014-10-13 23:42:13 -0600106struct tegra114_spi_priv {
Allen Martin77c42e82013-03-16 18:58:13 +0000107 struct spi_regs *regs;
108 unsigned int freq;
109 unsigned int mode;
110 int periph_id;
111 int valid;
Simon Glassfda6fac2014-10-13 23:42:13 -0600112 int last_transaction_us;
Allen Martin77c42e82013-03-16 18:58:13 +0000113};
114
Simon Glassfda6fac2014-10-13 23:42:13 -0600115static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
Allen Martin77c42e82013-03-16 18:58:13 +0000116{
Simon Glassfda6fac2014-10-13 23:42:13 -0600117 struct tegra_spi_platdata *plat = bus->platdata;
118 const void *blob = gd->fdt_blob;
119 int node = bus->of_offset;
120
121 plat->base = fdtdec_get_addr(blob, node, "reg");
122 plat->periph_id = clock_decode_periph_id(blob, node);
123
124 if (plat->periph_id == PERIPH_ID_NONE) {
125 debug("%s: could not decode periph id %d\n", __func__,
126 plat->periph_id);
127 return -FDT_ERR_NOTFOUND;
128 }
129
130 /* Use 500KHz as a suitable default */
131 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
132 500000);
133 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
134 "spi-deactivate-delay", 0);
135 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
136 __func__, plat->base, plat->periph_id, plat->frequency,
137 plat->deactivate_delay_us);
138
139 return 0;
Allen Martin77c42e82013-03-16 18:58:13 +0000140}
141
Simon Glassfda6fac2014-10-13 23:42:13 -0600142static int tegra114_spi_probe(struct udevice *bus)
Allen Martin77c42e82013-03-16 18:58:13 +0000143{
Simon Glassfda6fac2014-10-13 23:42:13 -0600144 struct tegra_spi_platdata *plat = dev_get_platdata(bus);
145 struct tegra114_spi_priv *priv = dev_get_priv(bus);
Simon Glass635c2512015-06-05 14:39:33 -0600146 struct spi_regs *regs;
Simon Glass20edd1a2015-06-05 14:39:35 -0600147 ulong rate;
Simon Glassfda6fac2014-10-13 23:42:13 -0600148
149 priv->regs = (struct spi_regs *)plat->base;
Simon Glass635c2512015-06-05 14:39:33 -0600150 regs = priv->regs;
Simon Glassfda6fac2014-10-13 23:42:13 -0600151
152 priv->last_transaction_us = timer_get_us();
153 priv->freq = plat->frequency;
154 priv->periph_id = plat->periph_id;
155
Simon Glass20edd1a2015-06-05 14:39:35 -0600156 /*
157 * Change SPI clock to correct frequency, PLLP_OUT0 source, falling
158 * back to the oscillator if that is too fast.
159 */
160 rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
161 priv->freq);
162 if (rate > priv->freq + 100000) {
163 rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_OSC,
164 priv->freq);
165 if (rate != priv->freq) {
166 printf("Warning: SPI '%s' requested clock %u, actual clock %lu\n",
167 bus->name, priv->freq, rate);
168 }
169 }
Allen Martin77c42e82013-03-16 18:58:13 +0000170
171 /* Clear stale status here */
172 setbits_le32(&regs->fifo_status,
173 SPI_FIFO_STS_ERR |
174 SPI_FIFO_STS_TX_FIFO_OVF |
175 SPI_FIFO_STS_TX_FIFO_UNR |
176 SPI_FIFO_STS_RX_FIFO_OVF |
177 SPI_FIFO_STS_RX_FIFO_UNR |
178 SPI_FIFO_STS_TX_FIFO_FULL |
179 SPI_FIFO_STS_TX_FIFO_EMPTY |
180 SPI_FIFO_STS_RX_FIFO_FULL |
181 SPI_FIFO_STS_RX_FIFO_EMPTY);
182 debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
183
Simon Glass635c2512015-06-05 14:39:33 -0600184 setbits_le32(&priv->regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
185 (priv->mode << SPI_CMD1_MODE_SHIFT) | SPI_CMD1_CS_SW_VAL);
Allen Martin77c42e82013-03-16 18:58:13 +0000186 debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
187
188 return 0;
189}
190
Simon Glassfda6fac2014-10-13 23:42:13 -0600191/**
192 * Activate the CS by driving it LOW
193 *
194 * @param slave Pointer to spi_slave to which controller has to
195 * communicate with
196 */
197static void spi_cs_activate(struct udevice *dev)
Allen Martin77c42e82013-03-16 18:58:13 +0000198{
Simon Glassfda6fac2014-10-13 23:42:13 -0600199 struct udevice *bus = dev->parent;
200 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
201 struct tegra114_spi_priv *priv = dev_get_priv(bus);
Allen Martin77c42e82013-03-16 18:58:13 +0000202
Simon Glassfda6fac2014-10-13 23:42:13 -0600203 /* If it's too soon to do another transaction, wait */
204 if (pdata->deactivate_delay_us &&
205 priv->last_transaction_us) {
206 ulong delay_us; /* The delay completed so far */
207 delay_us = timer_get_us() - priv->last_transaction_us;
208 if (delay_us < pdata->deactivate_delay_us)
209 udelay(pdata->deactivate_delay_us - delay_us);
210 }
211
212 clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
Allen Martin77c42e82013-03-16 18:58:13 +0000213}
214
Simon Glassfda6fac2014-10-13 23:42:13 -0600215/**
216 * Deactivate the CS by driving it HIGH
217 *
218 * @param slave Pointer to spi_slave to which controller has to
219 * communicate with
220 */
221static void spi_cs_deactivate(struct udevice *dev)
Allen Martin77c42e82013-03-16 18:58:13 +0000222{
Simon Glassfda6fac2014-10-13 23:42:13 -0600223 struct udevice *bus = dev->parent;
224 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
225 struct tegra114_spi_priv *priv = dev_get_priv(bus);
Allen Martin77c42e82013-03-16 18:58:13 +0000226
Simon Glassfda6fac2014-10-13 23:42:13 -0600227 setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
228
229 /* Remember time of this transaction so we can honour the bus delay */
230 if (pdata->deactivate_delay_us)
231 priv->last_transaction_us = timer_get_us();
232
233 debug("Deactivate CS, bus '%s'\n", bus->name);
Allen Martin77c42e82013-03-16 18:58:13 +0000234}
235
Simon Glassfda6fac2014-10-13 23:42:13 -0600236static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen,
237 const void *data_out, void *data_in,
238 unsigned long flags)
Allen Martin77c42e82013-03-16 18:58:13 +0000239{
Simon Glassfda6fac2014-10-13 23:42:13 -0600240 struct udevice *bus = dev->parent;
241 struct tegra114_spi_priv *priv = dev_get_priv(bus);
242 struct spi_regs *regs = priv->regs;
Allen Martin77c42e82013-03-16 18:58:13 +0000243 u32 reg, tmpdout, tmpdin = 0;
244 const u8 *dout = data_out;
245 u8 *din = data_in;
246 int num_bytes;
247 int ret;
248
249 debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
Simon Glassfda6fac2014-10-13 23:42:13 -0600250 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
Allen Martin77c42e82013-03-16 18:58:13 +0000251 if (bitlen % 8)
252 return -1;
253 num_bytes = bitlen / 8;
254
255 ret = 0;
256
Simon Glass635c2512015-06-05 14:39:33 -0600257 if (flags & SPI_XFER_BEGIN)
258 spi_cs_activate(dev);
259
Allen Martin77c42e82013-03-16 18:58:13 +0000260 /* clear all error status bits */
261 reg = readl(&regs->fifo_status);
262 writel(reg, &regs->fifo_status);
263
Allen Martin77c42e82013-03-16 18:58:13 +0000264 clrsetbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL,
265 SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE |
Simon Glassfda6fac2014-10-13 23:42:13 -0600266 (spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT));
Allen Martin77c42e82013-03-16 18:58:13 +0000267
268 /* set xfer size to 1 block (32 bits) */
269 writel(0, &regs->dma_blk);
270
Allen Martin77c42e82013-03-16 18:58:13 +0000271 /* handle data in 32-bit chunks */
272 while (num_bytes > 0) {
273 int bytes;
Allen Martin77c42e82013-03-16 18:58:13 +0000274 int tm, i;
275
276 tmpdout = 0;
277 bytes = (num_bytes > 4) ? 4 : num_bytes;
278
279 if (dout != NULL) {
280 for (i = 0; i < bytes; ++i)
281 tmpdout = (tmpdout << 8) | dout[i];
282 dout += bytes;
283 }
284
285 num_bytes -= bytes;
286
Yen Lin60acde42013-12-18 11:18:46 -0700287 /* clear ready bit */
288 setbits_le32(&regs->xfer_status, SPI_XFER_STS_RDY);
289
Allen Martin77c42e82013-03-16 18:58:13 +0000290 clrsetbits_le32(&regs->command1,
291 SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT,
292 (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT);
293 writel(tmpdout, &regs->tx_fifo);
294 setbits_le32(&regs->command1, SPI_CMD1_GO);
295
296 /*
297 * Wait for SPI transmit FIFO to empty, or to time out.
298 * The RX FIFO status will be read and cleared last
299 */
Yen Lin60acde42013-12-18 11:18:46 -0700300 for (tm = 0; tm < SPI_TIMEOUT; ++tm) {
Allen Martin77c42e82013-03-16 18:58:13 +0000301 u32 fifo_status, xfer_status;
302
Allen Martin77c42e82013-03-16 18:58:13 +0000303 xfer_status = readl(&regs->xfer_status);
304 if (!(xfer_status & SPI_XFER_STS_RDY))
305 continue;
306
Yen Lin60acde42013-12-18 11:18:46 -0700307 fifo_status = readl(&regs->fifo_status);
Allen Martin77c42e82013-03-16 18:58:13 +0000308 if (fifo_status & SPI_FIFO_STS_ERR) {
309 debug("%s: got a fifo error: ", __func__);
310 if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF)
311 debug("tx FIFO overflow ");
312 if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR)
313 debug("tx FIFO underrun ");
314 if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF)
315 debug("rx FIFO overflow ");
316 if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR)
317 debug("rx FIFO underrun ");
318 if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL)
319 debug("tx FIFO full ");
320 if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY)
321 debug("tx FIFO empty ");
322 if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL)
323 debug("rx FIFO full ");
324 if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)
325 debug("rx FIFO empty ");
326 debug("\n");
327 break;
328 }
329
330 if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) {
331 tmpdin = readl(&regs->rx_fifo);
Allen Martin77c42e82013-03-16 18:58:13 +0000332
333 /* swap bytes read in */
334 if (din != NULL) {
335 for (i = bytes - 1; i >= 0; --i) {
336 din[i] = tmpdin & 0xff;
337 tmpdin >>= 8;
338 }
339 din += bytes;
340 }
Yen Lin60acde42013-12-18 11:18:46 -0700341
342 /* We can exit when we've had both RX and TX */
343 break;
Allen Martin77c42e82013-03-16 18:58:13 +0000344 }
345 }
346
347 if (tm >= SPI_TIMEOUT)
348 ret = tm;
349
350 /* clear ACK RDY, etc. bits */
351 writel(readl(&regs->fifo_status), &regs->fifo_status);
352 }
353
354 if (flags & SPI_XFER_END)
Simon Glassfda6fac2014-10-13 23:42:13 -0600355 spi_cs_deactivate(dev);
Allen Martin77c42e82013-03-16 18:58:13 +0000356
357 debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
358 __func__, tmpdin, readl(&regs->fifo_status));
359
360 if (ret) {
361 printf("%s: timeout during SPI transfer, tm %d\n",
362 __func__, ret);
363 return -1;
364 }
365
Simon Glassfda6fac2014-10-13 23:42:13 -0600366 return ret;
367}
368
369static int tegra114_spi_set_speed(struct udevice *bus, uint speed)
370{
371 struct tegra_spi_platdata *plat = bus->platdata;
372 struct tegra114_spi_priv *priv = dev_get_priv(bus);
373
374 if (speed > plat->frequency)
375 speed = plat->frequency;
376 priv->freq = speed;
377 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
378
Allen Martin77c42e82013-03-16 18:58:13 +0000379 return 0;
380}
Simon Glassfda6fac2014-10-13 23:42:13 -0600381
382static int tegra114_spi_set_mode(struct udevice *bus, uint mode)
383{
384 struct tegra114_spi_priv *priv = dev_get_priv(bus);
385
386 priv->mode = mode;
387 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
388
389 return 0;
390}
391
392static const struct dm_spi_ops tegra114_spi_ops = {
Simon Glassfda6fac2014-10-13 23:42:13 -0600393 .xfer = tegra114_spi_xfer,
394 .set_speed = tegra114_spi_set_speed,
395 .set_mode = tegra114_spi_set_mode,
396 /*
397 * cs_info is not needed, since we require all chip selects to be
398 * in the device tree explicitly
399 */
400};
401
402static const struct udevice_id tegra114_spi_ids[] = {
403 { .compatible = "nvidia,tegra114-spi" },
404 { }
405};
406
407U_BOOT_DRIVER(tegra114_spi) = {
408 .name = "tegra114_spi",
409 .id = UCLASS_SPI,
410 .of_match = tegra114_spi_ids,
411 .ops = &tegra114_spi_ops,
412 .ofdata_to_platdata = tegra114_spi_ofdata_to_platdata,
413 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
414 .priv_auto_alloc_size = sizeof(struct tegra114_spi_priv),
Simon Glassfda6fac2014-10-13 23:42:13 -0600415 .probe = tegra114_spi_probe,
416};