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York Sunee52b182012-10-11 07:13:37 +00001/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
York Sunee52b182012-10-11 07:13:37 +00005 */
6
7/*
8 * Corenet DS style board configuration file
9 */
York Sun1cb19fb2013-06-27 10:48:29 -070010#ifndef __T4QDS_H
11#define __T4QDS_H
Liu Gang69fdf902013-05-07 16:30:50 +080012
York Sun15672c62014-04-30 14:43:49 -070013#define CONFIG_SYS_GENERIC_BOARD
14#define CONFIG_DISPLAY_BOARDINFO
York Sunee52b182012-10-11 07:13:37 +000015#define CONFIG_CMD_REGINFO
16
17/* High Level Configuration Options */
18#define CONFIG_BOOKE
York Sunee52b182012-10-11 07:13:37 +000019#define CONFIG_E500 /* BOOKE e500 family */
20#define CONFIG_E500MC /* BOOKE e500mc family */
21#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
York Sunee52b182012-10-11 07:13:37 +000022#define CONFIG_MP /* support multiple processors */
23
24#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053025#define CONFIG_SYS_TEXT_BASE 0xeff40000
York Sunee52b182012-10-11 07:13:37 +000026#endif
27
28#ifndef CONFIG_RESET_VECTOR_ADDRESS
29#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
30#endif
31
32#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
33#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
34#define CONFIG_FSL_IFC /* Enable IFC Support */
35#define CONFIG_PCI /* Enable PCI/PCIE */
36#define CONFIG_PCIE1 /* PCIE controler 1 */
37#define CONFIG_PCIE2 /* PCIE controler 2 */
38#define CONFIG_PCIE3 /* PCIE controler 3 */
39#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
40#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
41
42#define CONFIG_SYS_SRIO
43#define CONFIG_SRIO1 /* SRIO port 1 */
44#define CONFIG_SRIO2 /* SRIO port 2 */
45
46#define CONFIG_FSL_LAW /* Use common FSL init code */
47
48#define CONFIG_ENV_OVERWRITE
49
York Sunee52b182012-10-11 07:13:37 +000050/*
51 * These can be toggled for performance analysis, otherwise use default.
52 */
53#define CONFIG_SYS_CACHE_STASHING
54#define CONFIG_BTB /* toggle branch predition */
York Sunee52b182012-10-11 07:13:37 +000055#ifdef CONFIG_DDR_ECC
56#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
57#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
58#endif
59
60#define CONFIG_ENABLE_36BIT_PHYS
61
York Sunee52b182012-10-11 07:13:37 +000062#define CONFIG_ADDR_MAP
63#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
York Sunee52b182012-10-11 07:13:37 +000064
York Sunee52b182012-10-11 07:13:37 +000065#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
66#define CONFIG_SYS_MEMTEST_END 0x00400000
67#define CONFIG_SYS_ALT_MEMTEST
68#define CONFIG_PANIC_HANG /* do not reset board on panic */
69
70/*
71 * Config the L3 Cache as L3 SRAM
72 */
Shaohui Xieb6036992014-04-22 15:10:44 +080073#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
74#define CONFIG_SYS_L3_SIZE (512 << 10)
75#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
76#ifdef CONFIG_RAMBOOT_PBL
77#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
78#endif
79#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
80#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
81#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
82#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
York Sunee52b182012-10-11 07:13:37 +000083
York Sunee52b182012-10-11 07:13:37 +000084#define CONFIG_SYS_DCSRBAR 0xf0000000
85#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
York Sunee52b182012-10-11 07:13:37 +000086
York Sunee52b182012-10-11 07:13:37 +000087/*
88 * DDR Setup
89 */
90#define CONFIG_VERY_BIG_RAM
91#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
92#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
93
94/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
95#define CONFIG_DIMM_SLOTS_PER_CTLR 2
96#define CONFIG_CHIP_SELECTS_PER_CTRL 4
97#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
98
99#define CONFIG_DDR_SPD
York Sun5614e712013-09-30 09:22:09 -0700100#define CONFIG_SYS_FSL_DDR3
York Sunee52b182012-10-11 07:13:37 +0000101
York Sunee52b182012-10-11 07:13:37 +0000102
103/*
104 * IFC Definitions
105 */
106#define CONFIG_SYS_FLASH_BASE 0xe0000000
York Sunee52b182012-10-11 07:13:37 +0000107#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
York Sunee52b182012-10-11 07:13:37 +0000108
York Sunee52b182012-10-11 07:13:37 +0000109
Shaohui Xieb6036992014-04-22 15:10:44 +0800110#ifdef CONFIG_SPL_BUILD
111#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
112#else
113#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
114#endif
York Sunee52b182012-10-11 07:13:37 +0000115
York Sunee52b182012-10-11 07:13:37 +0000116#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
117#define CONFIG_MISC_INIT_R
118
119#define CONFIG_HWCONFIG
120
121/* define to use L1 as initial stack */
122#define CONFIG_L1_INIT_RAM
123#define CONFIG_SYS_INIT_RAM_LOCK
124#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
York Sunee52b182012-10-11 07:13:37 +0000125#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
126#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
127/* The assembler doesn't like typecast */
128#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
129 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
130 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
York Sunee52b182012-10-11 07:13:37 +0000131#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
132
133#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
134 GENERATED_GBL_DATA_SIZE)
135#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
136
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530137#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
York Sunee52b182012-10-11 07:13:37 +0000138#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
139
140/* Serial Port - controlled on board with jumper J8
141 * open - index 2
142 * shorted - index 1
143 */
144#define CONFIG_CONS_INDEX 1
145#define CONFIG_SYS_NS16550
146#define CONFIG_SYS_NS16550_SERIAL
147#define CONFIG_SYS_NS16550_REG_SIZE 1
148#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
149
150#define CONFIG_SYS_BAUDRATE_TABLE \
151 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
152
153#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
154#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
155#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
156#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
157
158/* Use the HUSH parser */
159#define CONFIG_SYS_HUSH_PARSER
160#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
161
162/* pass open firmware flat tree */
163#define CONFIG_OF_LIBFDT
164#define CONFIG_OF_BOARD_SETUP
165#define CONFIG_OF_STDOUT_VIA_ALIAS
166
167/* new uImage format support */
168#define CONFIG_FIT
169#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
170
171/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200172#define CONFIG_SYS_I2C
173#define CONFIG_SYS_I2C_FSL
Heiko Schocher00f792e2012-10-24 13:48:22 +0200174#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
175#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
Heiko Schocher00f792e2012-10-24 13:48:22 +0200176#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
177#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
178
York Sunee52b182012-10-11 07:13:37 +0000179/*
180 * RapidIO
181 */
182#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
York Sunee52b182012-10-11 07:13:37 +0000183#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
York Sunee52b182012-10-11 07:13:37 +0000184#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
185
186#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
York Sunee52b182012-10-11 07:13:37 +0000187#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
York Sunee52b182012-10-11 07:13:37 +0000188#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
189
190/*
York Sunee52b182012-10-11 07:13:37 +0000191 * General PCI
192 * Memory space is mapped 1-1, but I/O space must start from 0.
193 */
194
195/* controller 1, direct to uli, tgtid 3, Base address 20000 */
196#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
York Sunee52b182012-10-11 07:13:37 +0000197#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
198#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
York Sunee52b182012-10-11 07:13:37 +0000199#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
200#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
201#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
York Sunee52b182012-10-11 07:13:37 +0000202#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
York Sunee52b182012-10-11 07:13:37 +0000203#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
204
205/* controller 2, Slot 2, tgtid 2, Base address 201000 */
206#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
York Sunee52b182012-10-11 07:13:37 +0000207#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
208#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
York Sunee52b182012-10-11 07:13:37 +0000209#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
210#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
211#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
York Sunee52b182012-10-11 07:13:37 +0000212#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
York Sunee52b182012-10-11 07:13:37 +0000213#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
214
215/* controller 3, Slot 1, tgtid 1, Base address 202000 */
216#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
York Sunee52b182012-10-11 07:13:37 +0000217#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
218#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
York Sunee52b182012-10-11 07:13:37 +0000219#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
220#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
221#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
York Sunee52b182012-10-11 07:13:37 +0000222#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
York Sunee52b182012-10-11 07:13:37 +0000223#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
224
225/* controller 4, Base address 203000 */
226#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
227#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
228#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
229#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
230#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
231#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
232
York Sunee52b182012-10-11 07:13:37 +0000233#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000234#define CONFIG_PCI_INDIRECT_BRIDGE
York Sunee52b182012-10-11 07:13:37 +0000235#define CONFIG_PCI_PNP /* do pci plug-and-play */
236#define CONFIG_E1000
237
238#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
239#define CONFIG_DOS_PARTITION
240#endif /* CONFIG_PCI */
241
242/* SATA */
243#ifdef CONFIG_FSL_SATA_V2
244#define CONFIG_LIBATA
245#define CONFIG_FSL_SATA
246
247#define CONFIG_SYS_SATA_MAX_DEVICE 2
248#define CONFIG_SATA1
249#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
250#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
251#define CONFIG_SATA2
252#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
253#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
254
255#define CONFIG_LBA48
256#define CONFIG_CMD_SATA
257#define CONFIG_DOS_PARTITION
258#define CONFIG_CMD_EXT2
259#endif
260
261#ifdef CONFIG_FMAN_ENET
262#define CONFIG_MII /* MII PHY management */
263#define CONFIG_ETHPRIME "FM1@DTSEC1"
264#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
265#endif
266
267/*
268 * Environment
269 */
270#define CONFIG_LOADS_ECHO /* echo on for serial download */
271#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
272
273/*
274 * Command line configuration.
275 */
York Sunee52b182012-10-11 07:13:37 +0000276#define CONFIG_CMD_DHCP
277#define CONFIG_CMD_ELF
278#define CONFIG_CMD_ERRATA
279#define CONFIG_CMD_GREPENV
280#define CONFIG_CMD_IRQ
281#define CONFIG_CMD_I2C
282#define CONFIG_CMD_MII
283#define CONFIG_CMD_PING
York Sunee52b182012-10-11 07:13:37 +0000284
285#ifdef CONFIG_PCI
286#define CONFIG_CMD_PCI
York Sunee52b182012-10-11 07:13:37 +0000287#endif
288
289/*
York Sunee52b182012-10-11 07:13:37 +0000290 * Miscellaneous configurable options
291 */
292#define CONFIG_SYS_LONGHELP /* undef to save memory */
293#define CONFIG_CMDLINE_EDITING /* Command-line editing */
294#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
295#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
York Sunee52b182012-10-11 07:13:37 +0000296#ifdef CONFIG_CMD_KGDB
297#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
298#else
299#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
300#endif
301#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
302#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
303#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
York Sunee52b182012-10-11 07:13:37 +0000304
305/*
306 * For booting Linux, the board info and command line data
307 * have to be in the first 64 MB of memory, since this is
308 * the maximum mapped by the Linux kernel during initialization.
309 */
310#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
311#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
312
313#ifdef CONFIG_CMD_KGDB
314#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
York Sunee52b182012-10-11 07:13:37 +0000315#endif
316
317/*
318 * Environment Configuration
319 */
320#define CONFIG_ROOTPATH "/opt/nfsroot"
321#define CONFIG_BOOTFILE "uImage"
322#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
323
324/* default location for tftp and bootm */
325#define CONFIG_LOADADDR 1000000
326
York Sunee52b182012-10-11 07:13:37 +0000327
328#define CONFIG_BAUDRATE 115200
329
York Sunee52b182012-10-11 07:13:37 +0000330#define CONFIG_HVBOOT \
331 "setenv bootargs config-addr=0x60000000; " \
332 "bootm 0x01000000 - 0x00f00000"
333
York Sunee52b182012-10-11 07:13:37 +0000334#endif /* __CONFIG_H */