blob: 5377c2eb5bed2c7d5c1dde187c76249ab8719656 [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
2 * MPC85xx Internal Memory Map
3 *
4 * Copyright(c) 2002,2003 Motorola Inc.
5 * Xianghua Xiao (x.xiao@motorola.com)
6 *
7 */
8
9#ifndef __IMMAP_85xx__
10#define __IMMAP_85xx__
11
Jon Loeliger3dfa9cf2006-10-20 17:16:35 -050012#include <asm/types.h>
13#include <asm/fsl_i2c.h>
14
Jon Loeligerde1d0a62005-08-01 13:20:47 -050015/*
16 * Local-Access Registers and ECM Registers(0x0000-0x2000)
17 */
wdenk42d1f032003-10-15 23:53:47 +000018typedef struct ccsr_local_ecm {
19 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
20 char res1[4];
21 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
22 char res2[4];
23 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
24 char res3[12];
25 uint bptr; /* 0x20 - Boot Page Translation Register */
26 char res4[3044];
27 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
28 char res5[4];
29 uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
30 char res6[20];
31 uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
32 char res7[4];
33 uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
34 char res8[20];
35 uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
36 char res9[4];
37 uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
38 char res10[20];
39 uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
40 char res11[4];
41 uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
42 char res12[20];
43 uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
44 char res13[4];
45 uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
46 char res14[20];
47 uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
48 char res15[4];
49 uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
50 char res16[20];
51 uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
52 char res17[4];
53 uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
54 char res18[20];
55 uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
56 char res19[4];
57 uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
58 char res20[780];
59 uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */
60 char res21[12];
61 uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */
62 char res22[3564];
63 uint eedr; /* 0x1e00 - ECM Error Detect Register */
64 char res23[4];
65 uint eeer; /* 0x1e08 - ECM Error Enable Register */
66 uint eeatr; /* 0x1e0c - ECM Error Attributes Capture Register */
67 uint eeadr; /* 0x1e10 - ECM Error Address Capture Register */
68 char res24[492];
69} ccsr_local_ecm_t;
70
Jon Loeligerde1d0a62005-08-01 13:20:47 -050071/*
72 * DDR memory controller registers(0x2000-0x3000)
73 */
wdenk42d1f032003-10-15 23:53:47 +000074typedef struct ccsr_ddr {
75 uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
76 char res1[4];
77 uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
78 char res2[4];
79 uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
80 char res3[4];
81 uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
82 char res4[100];
83 uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
84 uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
85 uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
86 uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050087 char res5[112];
88 uint ext_refrec; /* 0x2100 - DDR SDRAM Extended Refresh Recovery */
89 uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
wdenk42d1f032003-10-15 23:53:47 +000090 uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
91 uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
92 uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050093 uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
wdenk42d1f032003-10-15 23:53:47 +000094 uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050095 uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2*/
96 uint sdram_md_cntl; /* 0x2120 - DDR SDRAM Mode Control */
wdenk42d1f032003-10-15 23:53:47 +000097 uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050098 uint sdram_data_init; /* 0x2128 - DDR SDRAM Data initialization */
99 char res6[4];
wdenk547b4cb2004-06-09 00:51:50 +0000100 uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500101 char res7[20];
102 uint init_address; /* 0x2148 - DDR training initialization address */
103 uint init_ext_address; /* 0x214C - DDR training initialization extended address */
104 char res8_1[2728];
105 uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
106 uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
107 char res8_2[512];
wdenk42d1f032003-10-15 23:53:47 +0000108 uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
109 uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
110 uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
111 char res9[20];
112 uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
113 uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
114 uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
115 char res10[20];
116 uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
117 uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
118 uint err_int_en; /* 0x2e48 - DDR */
119 uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
120 uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
121 uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
122 uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
123 char res11[164];
124 uint debug_1; /* 0x2f00 */
125 uint debug_2;
126 uint debug_3;
127 uint debug_4;
128 char res12[240];
129} ccsr_ddr_t;
130
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500131/*
132 * I2C Registers(0x3000-0x4000)
133 */
wdenk42d1f032003-10-15 23:53:47 +0000134typedef struct ccsr_i2c {
Jon Loeliger3dfa9cf2006-10-20 17:16:35 -0500135 struct fsl_i2c i2c[1];
136 u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
wdenk42d1f032003-10-15 23:53:47 +0000137} ccsr_i2c_t;
138
wdenk03f5c552004-10-10 21:21:55 +0000139#if defined(CONFIG_MPC8540) \
140 || defined(CONFIG_MPC8541) \
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500141 || defined(CONFIG_MPC8548) \
wdenk03f5c552004-10-10 21:21:55 +0000142 || defined(CONFIG_MPC8555)
wdenk42d1f032003-10-15 23:53:47 +0000143/* DUART Registers(0x4000-0x5000) */
144typedef struct ccsr_duart {
145 char res1[1280];
146 u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
147 u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
148 u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
149 u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
150 u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
151 u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
152 u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
153 u_char uscr1; /* 0x4507 - UART1 Scratch Register */
154 char res2[8];
155 u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
156 char res3[239];
157 u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
158 u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
159 u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
160 u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
161 u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
162 u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
163 u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
164 u_char uscr2; /* 0x4607 - UART2 Scratch Register */
165 char res4[8];
166 u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
167 char res5[2543];
168} ccsr_duart_t;
169#else /* MPC8560 uses UART on its CPM */
170typedef struct ccsr_duart {
171 char res[4096];
172} ccsr_duart_t;
173#endif
174
175/* Local Bus Controller Registers(0x5000-0x6000) */
176/* Omitting OCeaN(0x6000) and Reserved(0x7000) block */
177
178typedef struct ccsr_lbc {
179 uint br0; /* 0x5000 - LBC Base Register 0 */
180 uint or0; /* 0x5004 - LBC Options Register 0 */
181 uint br1; /* 0x5008 - LBC Base Register 1 */
182 uint or1; /* 0x500c - LBC Options Register 1 */
183 uint br2; /* 0x5010 - LBC Base Register 2 */
184 uint or2; /* 0x5014 - LBC Options Register 2 */
185 uint br3; /* 0x5018 - LBC Base Register 3 */
186 uint or3; /* 0x501c - LBC Options Register 3 */
187 uint br4; /* 0x5020 - LBC Base Register 4 */
188 uint or4; /* 0x5024 - LBC Options Register 4 */
189 uint br5; /* 0x5028 - LBC Base Register 5 */
190 uint or5; /* 0x502c - LBC Options Register 5 */
191 uint br6; /* 0x5030 - LBC Base Register 6 */
192 uint or6; /* 0x5034 - LBC Options Register 6 */
193 uint br7; /* 0x5038 - LBC Base Register 7 */
194 uint or7; /* 0x503c - LBC Options Register 7 */
195 char res1[40];
196 uint mar; /* 0x5068 - LBC UPM Address Register */
197 char res2[4];
198 uint mamr; /* 0x5070 - LBC UPMA Mode Register */
199 uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
200 uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
201 char res3[8];
202 uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
203 uint mdr; /* 0x5088 - LBC UPM Data Register */
204 char res4[8];
205 uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
206 char res5[8];
207 uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
208 uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
209 char res6[8];
210 uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
211 uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
212 uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
213 uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
214 uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
215 char res7[12];
216 uint lbcr; /* 0x50d0 - LBC Configuration Register */
217 uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
218 char res8[12072];
219} ccsr_lbc_t;
220
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500221/*
222 * PCI Registers(0x8000-0x9000)
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500223 */
wdenk42d1f032003-10-15 23:53:47 +0000224typedef struct ccsr_pcix {
225 uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
226 uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */
227 uint int_ack; /* 0x8008 - PCIX Interrupt Acknowledge Register */
228 char res1[3060];
229 uint potar0; /* 0x8c00 - PCIX Outbound Transaction Address Register 0 */
230 uint potear0; /* 0x8c04 - PCIX Outbound Translation Extended Address Register 0 */
231 uint powbar0; /* 0x8c08 - PCIX Outbound Window Base Address Register 0 */
232 uint powbear0; /* 0x8c0c - PCIX Outbound Window Base Extended Address Register 0 */
233 uint powar0; /* 0x8c10 - PCIX Outbound Window Attributes Register 0 */
234 char res2[12];
235 uint potar1; /* 0x8c20 - PCIX Outbound Transaction Address Register 1 */
236 uint potear1; /* 0x8c24 - PCIX Outbound Translation Extended Address Register 1 */
237 uint powbar1; /* 0x8c28 - PCIX Outbound Window Base Address Register 1 */
238 uint powbear1; /* 0x8c2c - PCIX Outbound Window Base Extended Address Register 1 */
239 uint powar1; /* 0x8c30 - PCIX Outbound Window Attributes Register 1 */
240 char res3[12];
241 uint potar2; /* 0x8c40 - PCIX Outbound Transaction Address Register 2 */
242 uint potear2; /* 0x8c44 - PCIX Outbound Translation Extended Address Register 2 */
243 uint powbar2; /* 0x8c48 - PCIX Outbound Window Base Address Register 2 */
244 uint powbear2; /* 0x8c4c - PCIX Outbound Window Base Extended Address Register 2 */
245 uint powar2; /* 0x8c50 - PCIX Outbound Window Attributes Register 2 */
246 char res4[12];
247 uint potar3; /* 0x8c60 - PCIX Outbound Transaction Address Register 3 */
248 uint potear3; /* 0x8c64 - PCIX Outbound Translation Extended Address Register 3 */
249 uint powbar3; /* 0x8c68 - PCIX Outbound Window Base Address Register 3 */
250 uint powbear3; /* 0x8c6c - PCIX Outbound Window Base Extended Address Register 3 */
251 uint powar3; /* 0x8c70 - PCIX Outbound Window Attributes Register 3 */
252 char res5[12];
253 uint potar4; /* 0x8c80 - PCIX Outbound Transaction Address Register 4 */
254 uint potear4; /* 0x8c84 - PCIX Outbound Translation Extended Address Register 4 */
255 uint powbar4; /* 0x8c88 - PCIX Outbound Window Base Address Register 4 */
256 uint powbear4; /* 0x8c8c - PCIX Outbound Window Base Extended Address Register 4 */
257 uint powar4; /* 0x8c90 - PCIX Outbound Window Attributes Register 4 */
258 char res6[268];
259 uint pitar3; /* 0x8da0 - PCIX Inbound Translation Address Register 3 */
260 uint pitear3; /* 0x8da4 - PCIX Inbound Translation Extended Address Register 3 */
261 uint piwbar3; /* 0x8da8 - PCIX Inbound Window Base Address Register 3 */
262 uint piwbear3; /* 0x8dac - PCIX Inbound Window Base Extended Address Register 3 */
263 uint piwar3; /* 0x8db0 - PCIX Inbound Window Attributes Register 3 */
264 char res7[12];
265 uint pitar2; /* 0x8dc0 - PCIX Inbound Translation Address Register 2 */
266 uint pitear2; /* 0x8dc4 - PCIX Inbound Translation Extended Address Register 2 */
267 uint piwbar2; /* 0x8dc8 - PCIX Inbound Window Base Address Register 2 */
268 uint piwbear2; /* 0x8dcc - PCIX Inbound Window Base Extended Address Register 2 */
269 uint piwar2; /* 0x8dd0 - PCIX Inbound Window Attributes Register 2 */
270 char res8[12];
271 uint pitar1; /* 0x8de0 - PCIX Inbound Translation Address Register 1 */
272 uint pitear1; /* 0x8de4 - PCIX Inbound Translation Extended Address Register 1 */
273 uint piwbar1; /* 0x8de8 - PCIX Inbound Window Base Address Register 1 */
274 char res9[4];
275 uint piwar1; /* 0x8df0 - PCIX Inbound Window Attributes Register 1 */
276 char res10[12];
277 uint pedr; /* 0x8e00 - PCIX Error Detect Register */
278 uint pecdr; /* 0x8e04 - PCIX Error Capture Disable Register */
279 uint peer; /* 0x8e08 - PCIX Error Enable Register */
280 uint peattrcr; /* 0x8e0c - PCIX Error Attributes Capture Register */
281 uint peaddrcr; /* 0x8e10 - PCIX Error Address Capture Register */
282 uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */
283 uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */
284 uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */
Matthew McClintock97074ed2006-06-28 10:45:17 -0500285 uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */
286 char res11[476];
wdenk42d1f032003-10-15 23:53:47 +0000287} ccsr_pcix_t;
288
Matthew McClintock97074ed2006-06-28 10:45:17 -0500289#define PCIX_COMMAND 0x62
290#define POWAR_EN 0x80000000
291#define POWAR_IO_READ 0x00080000
292#define POWAR_MEM_READ 0x00040000
293#define POWAR_IO_WRITE 0x00008000
294#define POWAR_MEM_WRITE 0x00004000
295#define POWAR_MEM_512M 0x0000001c
296#define POWAR_IO_1M 0x00000013
297
298#define PIWAR_EN 0x80000000
299#define PIWAR_PF 0x20000000
300#define PIWAR_LOCAL 0x00f00000
301#define PIWAR_READ_SNOOP 0x00050000
302#define PIWAR_WRITE_SNOOP 0x00005000
303#define PIWAR_MEM_2G 0x0000001e
304
305
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500306/*
307 * L2 Cache Registers(0x2_0000-0x2_1000)
308 */
wdenk42d1f032003-10-15 23:53:47 +0000309typedef struct ccsr_l2cache {
310 uint l2ctl; /* 0x20000 - L2 configuration register 0 */
311 char res1[12];
312 uint l2cewar0; /* 0x20010 - L2 cache external write address register 0 */
313 char res2[4];
314 uint l2cewcr0; /* 0x20018 - L2 cache external write control register 0 */
315 char res3[4];
316 uint l2cewar1; /* 0x20020 - L2 cache external write address register 1 */
317 char res4[4];
318 uint l2cewcr1; /* 0x20028 - L2 cache external write control register 1 */
319 char res5[4];
320 uint l2cewar2; /* 0x20030 - L2 cache external write address register 2 */
321 char res6[4];
322 uint l2cewcr2; /* 0x20038 - L2 cache external write control register 2 */
323 char res7[4];
324 uint l2cewar3; /* 0x20040 - L2 cache external write address register 3 */
325 char res8[4];
326 uint l2cewcr3; /* 0x20048 - L2 cache external write control register 3 */
327 char res9[180];
328 uint l2srbar0; /* 0x20100 - L2 memory-mapped SRAM base address register 0 */
329 char res10[4];
330 uint l2srbar1; /* 0x20108 - L2 memory-mapped SRAM base address register 1 */
331 char res11[3316];
332 uint l2errinjhi; /* 0x20e00 - L2 error injection mask high register */
333 uint l2errinjlo; /* 0x20e04 - L2 error injection mask low register */
334 uint l2errinjctl; /* 0x20e08 - L2 error injection tag/ECC control register */
335 char res12[20];
336 uint l2captdatahi; /* 0x20e20 - L2 error data high capture register */
337 uint l2captdatalo; /* 0x20e24 - L2 error data low capture register */
338 uint l2captecc; /* 0x20e28 - L2 error ECC capture register */
339 char res13[20];
340 uint l2errdet; /* 0x20e40 - L2 error detect register */
341 uint l2errdis; /* 0x20e44 - L2 error disable register */
342 uint l2errinten; /* 0x20e48 - L2 error interrupt enable register */
343 uint l2errattr; /* 0x20e4c - L2 error attributes capture register */
344 uint l2erraddr; /* 0x20e50 - L2 error address capture register */
345 char res14[4];
346 uint l2errctl; /* 0x20e58 - L2 error control register */
347 char res15[420];
348} ccsr_l2cache_t;
349
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500350/*
351 * DMA Registers(0x2_1000-0x2_2000)
352 */
wdenk42d1f032003-10-15 23:53:47 +0000353typedef struct ccsr_dma {
354 char res1[256];
355 uint mr0; /* 0x21100 - DMA 0 Mode Register */
356 uint sr0; /* 0x21104 - DMA 0 Status Register */
357 char res2[4];
358 uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */
359 uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */
360 uint sar0; /* 0x21114 - DMA 0 Source Address Register */
361 uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */
362 uint dar0; /* 0x2111c - DMA 0 Destination Address Register */
363 uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */
364 char res3[4];
365 uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */
366 char res4[8];
367 uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
368 char res5[4];
369 uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */
370 uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */
371 uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */
372 char res6[56];
373 uint mr1; /* 0x21180 - DMA 1 Mode Register */
374 uint sr1; /* 0x21184 - DMA 1 Status Register */
375 char res7[4];
376 uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */
377 uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */
378 uint sar1; /* 0x21194 - DMA 1 Source Address Register */
379 uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */
380 uint dar1; /* 0x2119c - DMA 1 Destination Address Register */
381 uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */
382 char res8[4];
383 uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
384 char res9[8];
385 uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
386 char res10[4];
387 uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */
388 uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */
389 uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */
390 char res11[56];
391 uint mr2; /* 0x21200 - DMA 2 Mode Register */
392 uint sr2; /* 0x21204 - DMA 2 Status Register */
393 char res12[4];
394 uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */
395 uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */
396 uint sar2; /* 0x21214 - DMA 2 Source Address Register */
397 uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */
398 uint dar2; /* 0x2121c - DMA 2 Destination Address Register */
399 uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */
400 char res13[4];
401 uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */
402 char res14[8];
403 uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
404 char res15[4];
405 uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */
406 uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */
407 uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */
408 char res16[56];
409 uint mr3; /* 0x21280 - DMA 3 Mode Register */
410 uint sr3; /* 0x21284 - DMA 3 Status Register */
411 char res17[4];
412 uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */
413 uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */
414 uint sar3; /* 0x21294 - DMA 3 Source Address Register */
415 uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */
416 uint dar3; /* 0x2129c - DMA 3 Destination Address Register */
417 uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */
418 char res18[4];
419 uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
420 char res19[8];
421 uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
422 char res20[4];
423 uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */
424 uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */
425 uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */
426 char res21[56];
427 uint dgsr; /* 0x21300 - DMA General Status Register */
428 char res22[11516];
429} ccsr_dma_t;
430
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500431/*
432 * tsec1 tsec2: 24000-26000
433 */
wdenk42d1f032003-10-15 23:53:47 +0000434typedef struct ccsr_tsec {
435 char res1[16];
436 uint ievent; /* 0x24010 - Interrupt Event Register */
437 uint imask; /* 0x24014 - Interrupt Mask Register */
438 uint edis; /* 0x24018 - Error Disabled Register */
439 char res2[4];
440 uint ecntrl; /* 0x24020 - Ethernet Control Register */
441 uint minflr; /* 0x24024 - Minimum Frame Length Register */
442 uint ptv; /* 0x24028 - Pause Time Value Register */
443 uint dmactrl; /* 0x2402c - DMA Control Register */
444 uint tbipa; /* 0x24030 - TBI PHY Address Register */
445 char res3[88];
446 uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
447 char res4[8];
448 uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
449 uint fifo_tx_starve_shutoff; /* 0x2409c - FIFO transmit starve shutoff register */
450 char res5[96];
451 uint tctrl; /* 0x24100 - Transmit Control Register */
452 uint tstat; /* 0x24104 - Transmit Status Register */
453 char res6[4];
454 uint tbdlen; /* 0x2410c - Transmit Buffer Descriptor Data Length Register */
455 char res7[16];
456 uint ctbptrh; /* 0x24120 - Current Transmit Buffer Descriptor Pointer High Register */
457 uint ctbptr; /* 0x24124 - Current Transmit Buffer Descriptor Pointer Register */
458 char res8[88];
459 uint tbptrh; /* 0x24180 - Transmit Buffer Descriptor Pointer High Register */
460 uint tbptr; /* 0x24184 - Transmit Buffer Descriptor Pointer Low Register */
461 char res9[120];
462 uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
463 uint tbase; /* 0x24204 - Transmit Descriptor Base Address Register */
464 char res10[168];
465 uint ostbd; /* 0x242b0 - Out-of-Sequence Transmit Buffer Descriptor Register */
466 uint ostbdp; /* 0x242b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */
467 uint os32tbdp; /* 0x242b8 - Out-of-Sequence 32 Bytes Transmit Data Buffer Pointer Low Register */
468 uint os32iptrh; /* 0x242bc - Out-of-Sequence 32 Bytes Transmit Insert Pointer High Register */
469 uint os32iptrl; /* 0x242c0 - Out-of-Sequence 32 Bytes Transmit Insert Pointer Low Register */
470 uint os32tbdr; /* 0x242c4 - Out-of-Sequence 32 Bytes Transmit Reserved Register */
471 uint os32iil; /* 0x242c8 - Out-of-Sequence 32 Bytes Transmit Insert Index/Length Register */
472 char res11[52];
473 uint rctrl; /* 0x24300 - Receive Control Register */
474 uint rstat; /* 0x24304 - Receive Status Register */
475 char res12[4];
476 uint rbdlen; /* 0x2430c - RxBD Data Length Register */
477 char res13[16];
478 uint crbptrh; /* 0x24320 - Current Receive Buffer Descriptor Pointer High */
479 uint crbptr; /* 0x24324 - Current Receive Buffer Descriptor Pointer */
480 char res14[24];
481 uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
482 uint mrblr2r3; /* 0x24344 - Maximum Receive Buffer Length R2R3 Register */
483 char res15[56];
484 uint rbptrh; /* 0x24380 - Receive Buffer Descriptor Pointer High 0 */
485 uint rbptr; /* 0x24384 - Receive Buffer Descriptor Pointer */
486 uint rbptrh1; /* 0x24388 - Receive Buffer Descriptor Pointer High 1 */
487 uint rbptrl1; /* 0x2438c - Receive Buffer Descriptor Pointer Low 1 */
488 uint rbptrh2; /* 0x24390 - Receive Buffer Descriptor Pointer High 2 */
489 uint rbptrl2; /* 0x24394 - Receive Buffer Descriptor Pointer Low 2 */
490 uint rbptrh3; /* 0x24398 - Receive Buffer Descriptor Pointer High 3 */
491 uint rbptrl3; /* 0x2439c - Receive Buffer Descriptor Pointer Low 3 */
492 char res16[96];
493 uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
494 uint rbase; /* 0x24404 - Receive Descriptor Base Address */
495 uint rbaseh1; /* 0x24408 - Receive Descriptor Base Address High 1 */
496 uint rbasel1; /* 0x2440c - Receive Descriptor Base Address Low 1 */
497 uint rbaseh2; /* 0x24410 - Receive Descriptor Base Address High 2 */
498 uint rbasel2; /* 0x24414 - Receive Descriptor Base Address Low 2 */
499 uint rbaseh3; /* 0x24418 - Receive Descriptor Base Address High 3 */
500 uint rbasel3; /* 0x2441c - Receive Descriptor Base Address Low 3 */
501 char res17[224];
502 uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
503 uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
504 uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
505 uint hafdup; /* 0x2450c - Half Duplex Register */
506 uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
507 char res18[12];
508 uint miimcfg; /* 0x24520 - MII Management Configuration Register */
509 uint miimcom; /* 0x24524 - MII Management Command Register */
510 uint miimadd; /* 0x24528 - MII Management Address Register */
511 uint miimcon; /* 0x2452c - MII Management Control Register */
512 uint miimstat; /* 0x24530 - MII Management Status Register */
513 uint miimind; /* 0x24534 - MII Management Indicator Register */
514 char res19[4];
515 uint ifstat; /* 0x2453c - Interface Status Register */
516 uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
517 uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
518 char res20[312];
519 uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
520 uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
521 uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
522 uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
523 uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
524 uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
525 uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
526 uint rbyt; /* 0x2469c - Receive Byte Counter */
527 uint rpkt; /* 0x246a0 - Receive Packet Counter */
528 uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
529 uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
530 uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
531 uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
532 uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
533 uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
534 uint raln; /* 0x246bc - Receive Alignment Error Counter */
535 uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
536 uint rcde; /* 0x246c4 - Receive Code Error Counter */
537 uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
538 uint rund; /* 0x246cc - Receive Undersize Packet Counter */
539 uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
540 uint rfrg; /* 0x246d4 - Receive Fragments Counter */
541 uint rjbr; /* 0x246d8 - Receive Jabber Counter */
542 uint rdrp; /* 0x246dc - Receive Drop Counter */
543 uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
544 uint tpkt; /* 0x246e4 - Transmit Packet Counter */
545 uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
546 uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
547 uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
548 uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
549 uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
550 uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
551 uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
552 uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
553 uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
554 uint tncl; /* 0x2470c - Transmit Total Collision Counter */
555 char res21[4];
556 uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
557 uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
558 uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
559 uint txcf; /* 0x24720 - Transmit Control Frame Counter */
560 uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
561 uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
562 uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
563 uint car1; /* 0x24730 - Carry Register One */
564 uint car2; /* 0x24734 - Carry Register Two */
565 uint cam1; /* 0x24738 - Carry Mask Register One */
566 uint cam2; /* 0x2473c - Carry Mask Register Two */
567 char res22[192];
568 uint iaddr0; /* 0x24800 - Indivdual address register 0 */
569 uint iaddr1; /* 0x24804 - Indivdual address register 1 */
570 uint iaddr2; /* 0x24808 - Indivdual address register 2 */
571 uint iaddr3; /* 0x2480c - Indivdual address register 3 */
572 uint iaddr4; /* 0x24810 - Indivdual address register 4 */
573 uint iaddr5; /* 0x24814 - Indivdual address register 5 */
574 uint iaddr6; /* 0x24818 - Indivdual address register 6 */
575 uint iaddr7; /* 0x2481c - Indivdual address register 7 */
576 char res23[96];
577 uint gaddr0; /* 0x24880 - Global address register 0 */
578 uint gaddr1; /* 0x24884 - Global address register 1 */
579 uint gaddr2; /* 0x24888 - Global address register 2 */
580 uint gaddr3; /* 0x2488c - Global address register 3 */
581 uint gaddr4; /* 0x24890 - Global address register 4 */
582 uint gaddr5; /* 0x24894 - Global address register 5 */
583 uint gaddr6; /* 0x24898 - Global address register 6 */
584 uint gaddr7; /* 0x2489c - Global address register 7 */
585 char res24[96];
586 uint pmd0; /* 0x24900 - Pattern Match Data Register */
587 char res25[4];
588 uint pmask0; /* 0x24908 - Pattern Mask Register */
589 char res26[4];
590 uint pcntrl0; /* 0x24910 - Pattern Match Control Register */
591 char res27[4];
592 uint pattrb0; /* 0x24918 - Pattern Match Attributes Register */
593 uint pattrbeli0; /* 0x2491c - Pattern Match Attributes Extract Length and Extract Index Register */
594 uint pmd1; /* 0x24920 - Pattern Match Data Register */
595 char res28[4];
596 uint pmask1; /* 0x24928 - Pattern Mask Register */
597 char res29[4];
598 uint pcntrl1; /* 0x24930 - Pattern Match Control Register */
599 char res30[4];
600 uint pattrb1; /* 0x24938 - Pattern Match Attributes Register */
601 uint pattrbeli1; /* 0x2493c - Pattern Match Attributes Extract Length and Extract Index Register */
602 uint pmd2; /* 0x24940 - Pattern Match Data Register */
603 char res31[4];
604 uint pmask2; /* 0x24948 - Pattern Mask Register */
605 char res32[4];
606 uint pcntrl2; /* 0x24950 - Pattern Match Control Register */
607 char res33[4];
608 uint pattrb2; /* 0x24958 - Pattern Match Attributes Register */
609 uint pattrbeli2; /* 0x2495c - Pattern Match Attributes Extract Length and Extract Index Register */
610 uint pmd3; /* 0x24960 - Pattern Match Data Register */
611 char res34[4];
612 uint pmask3; /* 0x24968 - Pattern Mask Register */
613 char res35[4];
614 uint pcntrl3; /* 0x24970 - Pattern Match Control Register */
615 char res36[4];
616 uint pattrb3; /* 0x24978 - Pattern Match Attributes Register */
617 uint pattrbeli3; /* 0x2497c - Pattern Match Attributes Extract Length and Extract Index Register */
618 uint pmd4; /* 0x24980 - Pattern Match Data Register */
619 char res37[4];
620 uint pmask4; /* 0x24988 - Pattern Mask Register */
621 char res38[4];
622 uint pcntrl4; /* 0x24990 - Pattern Match Control Register */
623 char res39[4];
624 uint pattrb4; /* 0x24998 - Pattern Match Attributes Register */
625 uint pattrbeli4; /* 0x2499c - Pattern Match Attributes Extract Length and Extract Index Register */
626 uint pmd5; /* 0x249a0 - Pattern Match Data Register */
627 char res40[4];
628 uint pmask5; /* 0x249a8 - Pattern Mask Register */
629 char res41[4];
630 uint pcntrl5; /* 0x249b0 - Pattern Match Control Register */
631 char res42[4];
632 uint pattrb5; /* 0x249b8 - Pattern Match Attributes Register */
633 uint pattrbeli5; /* 0x249bc - Pattern Match Attributes Extract Length and Extract Index Register */
634 uint pmd6; /* 0x249c0 - Pattern Match Data Register */
635 char res43[4];
636 uint pmask6; /* 0x249c8 - Pattern Mask Register */
637 char res44[4];
638 uint pcntrl6; /* 0x249d0 - Pattern Match Control Register */
639 char res45[4];
640 uint pattrb6; /* 0x249d8 - Pattern Match Attributes Register */
641 uint pattrbeli6; /* 0x249dc - Pattern Match Attributes Extract Length and Extract Index Register */
642 uint pmd7; /* 0x249e0 - Pattern Match Data Register */
643 char res46[4];
644 uint pmask7; /* 0x249e8 - Pattern Mask Register */
645 char res47[4];
646 uint pcntrl7; /* 0x249f0 - Pattern Match Control Register */
647 char res48[4];
648 uint pattrb7; /* 0x249f8 - Pattern Match Attributes Register */
649 uint pattrbeli7; /* 0x249fc - Pattern Match Attributes Extract Length and Extract Index Register */
650 uint pmd8; /* 0x24a00 - Pattern Match Data Register */
651 char res49[4];
652 uint pmask8; /* 0x24a08 - Pattern Mask Register */
653 char res50[4];
654 uint pcntrl8; /* 0x24a10 - Pattern Match Control Register */
655 char res51[4];
656 uint pattrb8; /* 0x24a18 - Pattern Match Attributes Register */
657 uint pattrbeli8; /* 0x24a1c - Pattern Match Attributes Extract Length and Extract Index Register */
658 uint pmd9; /* 0x24a20 - Pattern Match Data Register */
659 char res52[4];
660 uint pmask9; /* 0x24a28 - Pattern Mask Register */
661 char res53[4];
662 uint pcntrl9; /* 0x24a30 - Pattern Match Control Register */
663 char res54[4];
664 uint pattrb9; /* 0x24a38 - Pattern Match Attributes Register */
665 uint pattrbeli9; /* 0x24a3c - Pattern Match Attributes Extract Length and Extract Index Register */
666 uint pmd10; /* 0x24a40 - Pattern Match Data Register */
667 char res55[4];
668 uint pmask10; /* 0x24a48 - Pattern Mask Register */
669 char res56[4];
670 uint pcntrl10; /* 0x24a50 - Pattern Match Control Register */
671 char res57[4];
672 uint pattrb10; /* 0x24a58 - Pattern Match Attributes Register */
673 uint pattrbeli10; /* 0x24a5c - Pattern Match Attributes Extract Length and Extract Index Register */
674 uint pmd11; /* 0x24a60 - Pattern Match Data Register */
675 char res58[4];
676 uint pmask11; /* 0x24a68 - Pattern Mask Register */
677 char res59[4];
678 uint pcntrl11; /* 0x24a70 - Pattern Match Control Register */
679 char res60[4];
680 uint pattrb11; /* 0x24a78 - Pattern Match Attributes Register */
681 uint pattrbeli11; /* 0x24a7c - Pattern Match Attributes Extract Length and Extract Index Register */
682 uint pmd12; /* 0x24a80 - Pattern Match Data Register */
683 char res61[4];
684 uint pmask12; /* 0x24a88 - Pattern Mask Register */
685 char res62[4];
686 uint pcntrl12; /* 0x24a90 - Pattern Match Control Register */
687 char res63[4];
688 uint pattrb12; /* 0x24a98 - Pattern Match Attributes Register */
689 uint pattrbeli12; /* 0x24a9c - Pattern Match Attributes Extract Length and Extract Index Register */
690 uint pmd13; /* 0x24aa0 - Pattern Match Data Register */
691 char res64[4];
692 uint pmask13; /* 0x24aa8 - Pattern Mask Register */
693 char res65[4];
694 uint pcntrl13; /* 0x24ab0 - Pattern Match Control Register */
695 char res66[4];
696 uint pattrb13; /* 0x24ab8 - Pattern Match Attributes Register */
697 uint pattrbeli13; /* 0x24abc - Pattern Match Attributes Extract Length and Extract Index Register */
698 uint pmd14; /* 0x24ac0 - Pattern Match Data Register */
699 char res67[4];
700 uint pmask14; /* 0x24ac8 - Pattern Mask Register */
701 char res68[4];
702 uint pcntrl14; /* 0x24ad0 - Pattern Match Control Register */
703 char res69[4];
704 uint pattrb14; /* 0x24ad8 - Pattern Match Attributes Register */
705 uint pattrbeli14; /* 0x24adc - Pattern Match Attributes Extract Length and Extract Index Register */
706 uint pmd15; /* 0x24ae0 - Pattern Match Data Register */
707 char res70[4];
708 uint pmask15; /* 0x24ae8 - Pattern Mask Register */
709 char res71[4];
710 uint pcntrl15; /* 0x24af0 - Pattern Match Control Register */
711 char res72[4];
712 uint pattrb15; /* 0x24af8 - Pattern Match Attributes Register */
713 uint pattrbeli15; /* 0x24afc - Pattern Match Attributes Extract Length and Extract Index Register */
714 char res73[248];
715 uint attr; /* 0x24bf8 - Attributes Register */
716 uint attreli; /* 0x24bfc - Attributes Extract Length and Extract Index Register */
717 char res74[1024];
718} ccsr_tsec_t;
719
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500720/*
721 * PIC Registers(0x2_6000-0x4_0000-0x8_0000)
722 */
wdenk42d1f032003-10-15 23:53:47 +0000723typedef struct ccsr_pic {
724 char res0[106496]; /* 0x26000-0x40000 */
725 char res1[64];
726 uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
727 char res2[12];
728 uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
729 char res3[12];
730 uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
731 char res4[12];
732 uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
733 char res5[12];
734 uint ctpr; /* 0x40080 - Current Task Priority Register */
735 char res6[12];
736 uint whoami; /* 0x40090 - Who Am I Register */
737 char res7[12];
738 uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
739 char res8[12];
740 uint eoi; /* 0x400b0 - End Of Interrupt Register */
741 char res9[3916];
742 uint frr; /* 0x41000 - Feature Reporting Register */
743 char res10[28];
744 uint gcr; /* 0x41020 - Global Configuration Register */
wdenk343117b2005-05-13 22:49:36 +0000745#define MPC85xx_PICGCR_RST 0x80000000
746#define MPC85xx_PICGCR_M 0x20000000
wdenk42d1f032003-10-15 23:53:47 +0000747 char res11[92];
748 uint vir; /* 0x41080 - Vendor Identification Register */
749 char res12[12];
750 uint pir; /* 0x41090 - Processor Initialization Register */
751 char res13[12];
752 uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
753 char res14[12];
754 uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
755 char res15[12];
756 uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
757 char res16[12];
758 uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
759 char res17[12];
760 uint svr; /* 0x410e0 - Spurious Vector Register */
761 char res18[12];
762 uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
763 char res19[12];
764 uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
765 char res20[12];
766 uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
767 char res21[12];
768 uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
769 char res22[12];
770 uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
771 char res23[12];
772 uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
773 char res24[12];
774 uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
775 char res25[12];
776 uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
777 char res26[12];
778 uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
779 char res27[12];
780 uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
781 char res28[12];
782 uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
783 char res29[12];
784 uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
785 char res30[12];
786 uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
787 char res31[12];
788 uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
789 char res32[12];
790 uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
791 char res33[12];
792 uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
793 char res34[12];
794 uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
795 char res35[268];
796 uint tcr; /* 0x41300 - Timer Control Register */
797 char res36[12];
798 uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
799 char res37[12];
800 uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
801 char res38[12];
802 uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
803 char res39[12];
804 uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
805 char res40[188];
806 uint msgr0; /* 0x41400 - Message Register 0 */
807 char res41[12];
808 uint msgr1; /* 0x41410 - Message Register 1 */
809 char res42[12];
810 uint msgr2; /* 0x41420 - Message Register 2 */
811 char res43[12];
812 uint msgr3; /* 0x41430 - Message Register 3 */
813 char res44[204];
814 uint mer; /* 0x41500 - Message Enable Register */
815 char res45[12];
816 uint msr; /* 0x41510 - Message Status Register */
817 char res46[60140];
818 uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
819 char res47[12];
820 uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
821 char res48[12];
822 uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
823 char res49[12];
824 uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
825 char res50[12];
826 uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
827 char res51[12];
828 uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
829 char res52[12];
830 uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
831 char res53[12];
832 uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
833 char res54[12];
834 uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
835 char res55[12];
836 uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
837 char res56[12];
838 uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
839 char res57[12];
840 uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
841 char res58[12];
842 uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
843 char res59[12];
844 uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
845 char res60[12];
846 uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
847 char res61[12];
848 uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
849 char res62[12];
850 uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
851 char res63[12];
852 uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
853 char res64[12];
854 uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
855 char res65[12];
856 uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
857 char res66[12];
858 uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
859 char res67[12];
860 uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
861 char res68[12];
862 uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
863 char res69[12];
864 uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
865 char res70[140];
866 uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
867 char res71[12];
868 uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
869 char res72[12];
870 uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
871 char res73[12];
872 uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
873 char res74[12];
874 uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
875 char res75[12];
876 uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
877 char res76[12];
878 uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
879 char res77[12];
880 uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
881 char res78[12];
882 uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
883 char res79[12];
884 uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
885 char res80[12];
886 uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
887 char res81[12];
888 uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
889 char res82[12];
890 uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
891 char res83[12];
892 uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
893 char res84[12];
894 uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
895 char res85[12];
896 uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
897 char res86[12];
898 uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
899 char res87[12];
900 uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
901 char res88[12];
902 uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
903 char res89[12];
904 uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
905 char res90[12];
906 uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
907 char res91[12];
908 uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
909 char res92[12];
910 uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
911 char res93[12];
912 uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
913 char res94[12];
914 uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
915 char res95[12];
916 uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
917 char res96[12];
918 uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
919 char res97[12];
920 uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
921 char res98[12];
922 uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
923 char res99[12];
924 uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
925 char res100[12];
926 uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
927 char res101[12];
928 uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
929 char res102[12];
930 uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
931 char res103[12];
932 uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
933 char res104[12];
934 uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
935 char res105[12];
936 uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
937 char res106[12];
938 uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
939 char res107[12];
940 uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
941 char res108[12];
942 uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
943 char res109[12];
944 uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
945 char res110[12];
946 uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
947 char res111[12];
948 uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
949 char res112[12];
950 uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
951 char res113[12];
952 uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
953 char res114[12];
954 uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
955 char res115[12];
956 uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
957 char res116[12];
958 uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
959 char res117[12];
960 uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
961 char res118[12];
962 uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
963 char res119[12];
964 uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
965 char res120[12];
966 uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
967 char res121[12];
968 uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
969 char res122[12];
970 uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
971 char res123[12];
972 uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
973 char res124[12];
974 uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
975 char res125[12];
976 uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
977 char res126[12];
978 uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
979 char res127[12];
980 uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
981 char res128[12];
982 uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
983 char res129[12];
984 uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
985 char res130[12];
986 uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
987 char res131[12];
988 uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
989 char res132[12];
990 uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
991 char res133[12];
992 uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
993 char res134[4108];
994 uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
995 char res135[12];
996 uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
997 char res136[12];
998 uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
999 char res137[12];
1000 uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
1001 char res138[12];
1002 uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
1003 char res139[12];
1004 uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
1005 char res140[12];
1006 uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
1007 char res141[12];
1008 uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
1009 char res142[59852];
1010 uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
1011 char res143[12];
1012 uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
1013 char res144[12];
1014 uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
1015 char res145[12];
1016 uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
1017 char res146[12];
1018 uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
1019 char res147[12];
1020 uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
1021 char res148[12];
1022 uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
1023 char res149[12];
1024 uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
1025 char res150[130892];
1026} ccsr_pic_t;
1027
Jon Loeligerde1d0a62005-08-01 13:20:47 -05001028/*
1029 * CPM Block(0x8_0000-0xc_0000)
1030 */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -05001031#ifndef CONFIG_CPM2
wdenk42d1f032003-10-15 23:53:47 +00001032typedef struct ccsr_cpm {
1033 char res[262144];
1034} ccsr_cpm_t;
1035#else
Jon Loeligerde1d0a62005-08-01 13:20:47 -05001036/*
1037 * 0x8000-0x8ffff:DPARM
1038 * 0x9000-0x90bff: General SIU
1039 */
wdenk42d1f032003-10-15 23:53:47 +00001040typedef struct ccsr_cpm_siu {
1041 char res1[80];
1042 uint smaer;
1043 uint smser;
1044 uint smevr;
1045 char res2[4];
1046 uint lmaer;
1047 uint lmser;
1048 uint lmevr;
1049 char res3[2964];
1050} ccsr_cpm_siu_t;
1051
1052/* 0x90c00-0x90cff: Interrupt Controller */
1053typedef struct ccsr_cpm_intctl {
1054 ushort sicr;
1055 char res1[2];
1056 uint sivec;
1057 uint sipnrh;
1058 uint sipnrl;
1059 uint siprr;
1060 uint scprrh;
1061 uint scprrl;
1062 uint simrh;
1063 uint simrl;
1064 uint siexr;
1065 char res2[88];
1066 uint sccr;
1067 char res3[124];
1068} ccsr_cpm_intctl_t;
1069
1070/* 0x90d00-0x90d7f: input/output port */
1071typedef struct ccsr_cpm_iop {
1072 uint pdira;
1073 uint ppara;
1074 uint psora;
1075 uint podra;
1076 uint pdata;
1077 char res1[12];
1078 uint pdirb;
1079 uint pparb;
1080 uint psorb;
1081 uint podrb;
1082 uint pdatb;
1083 char res2[12];
1084 uint pdirc;
1085 uint pparc;
1086 uint psorc;
1087 uint podrc;
1088 uint pdatc;
1089 char res3[12];
1090 uint pdird;
1091 uint ppard;
1092 uint psord;
1093 uint podrd;
1094 uint pdatd;
1095 char res4[12];
1096} ccsr_cpm_iop_t;
1097
1098/* 0x90d80-0x91017: CPM timers */
1099typedef struct ccsr_cpm_timer {
1100 u_char tgcr1;
1101 char res1[3];
1102 u_char tgcr2;
1103 char res2[11];
1104 ushort tmr1;
1105 ushort tmr2;
1106 ushort trr1;
1107 ushort trr2;
1108 ushort tcr1;
1109 ushort tcr2;
1110 ushort tcn1;
1111 ushort tcn2;
1112 ushort tmr3;
1113 ushort tmr4;
1114 ushort trr3;
1115 ushort trr4;
1116 ushort tcr3;
1117 ushort tcr4;
1118 ushort tcn3;
1119 ushort tcn4;
1120 ushort ter1;
1121 ushort ter2;
1122 ushort ter3;
1123 ushort ter4;
1124 char res3[608];
1125} ccsr_cpm_timer_t;
1126
1127/* 0x91018-0x912ff: SDMA */
1128typedef struct ccsr_cpm_sdma {
1129 uchar sdsr;
1130 char res1[3];
1131 uchar sdmr;
1132 char res2[739];
1133} ccsr_cpm_sdma_t;
1134
1135/* 0x91300-0x9131f: FCC1 */
1136typedef struct ccsr_cpm_fcc1 {
1137 uint gfmr;
1138 uint fpsmr;
1139 ushort ftodr;
1140 char res1[2];
1141 ushort fdsr;
1142 char res2[2];
1143 ushort fcce;
1144 char res3[2];
1145 ushort fccm;
1146 char res4[2];
1147 u_char fccs;
1148 char res5[3];
1149 u_char ftirr_phy[4];
1150} ccsr_cpm_fcc1_t;
1151
1152/* 0x91320-0x9133f: FCC2 */
1153typedef struct ccsr_cpm_fcc2 {
1154 uint gfmr;
1155 uint fpsmr;
1156 ushort ftodr;
1157 char res1[2];
1158 ushort fdsr;
1159 char res2[2];
1160 ushort fcce;
1161 char res3[2];
1162 ushort fccm;
1163 char res4[2];
1164 u_char fccs;
1165 char res5[3];
1166 u_char ftirr_phy[4];
1167} ccsr_cpm_fcc2_t;
1168
1169/* 0x91340-0x9137f: FCC3 */
1170typedef struct ccsr_cpm_fcc3 {
1171 uint gfmr;
1172 uint fpsmr;
1173 ushort ftodr;
1174 char res1[2];
1175 ushort fdsr;
1176 char res2[2];
1177 ushort fcce;
1178 char res3[2];
1179 ushort fccm;
1180 char res4[2];
1181 u_char fccs;
1182 char res5[3];
1183 char res[36];
1184} ccsr_cpm_fcc3_t;
1185
1186/* 0x91380-0x9139f: FCC1 extended */
1187typedef struct ccsr_cpm_fcc1_ext {
1188 uint firper;
1189 uint firer;
1190 uint firsr_h;
1191 uint firsr_l;
1192 u_char gfemr;
1193 char res[15];
1194
1195} ccsr_cpm_fcc1_ext_t;
1196
1197/* 0x913a0-0x913cf: FCC2 extended */
1198typedef struct ccsr_cpm_fcc2_ext {
1199 uint firper;
1200 uint firer;
1201 uint firsr_h;
1202 uint firsr_l;
1203 u_char gfemr;
1204 char res[31];
1205} ccsr_cpm_fcc2_ext_t;
1206
1207/* 0x913d0-0x913ff: FCC3 extended */
1208typedef struct ccsr_cpm_fcc3_ext {
1209 u_char gfemr;
1210 char res[47];
1211} ccsr_cpm_fcc3_ext_t;
1212
1213/* 0x91400-0x915ef: TC layers */
1214typedef struct ccsr_cpm_tmp1 {
1215 char res[496];
1216} ccsr_cpm_tmp1_t;
1217
1218/* 0x915f0-0x9185f: BRGs:5,6,7,8 */
1219typedef struct ccsr_cpm_brg2 {
1220 uint brgc5;
1221 uint brgc6;
1222 uint brgc7;
1223 uint brgc8;
1224 char res[608];
1225} ccsr_cpm_brg2_t;
1226
1227/* 0x91860-0x919bf: I2C */
1228typedef struct ccsr_cpm_i2c {
1229 u_char i2mod;
1230 char res1[3];
1231 u_char i2add;
1232 char res2[3];
1233 u_char i2brg;
1234 char res3[3];
1235 u_char i2com;
1236 char res4[3];
1237 u_char i2cer;
1238 char res5[3];
1239 u_char i2cmr;
1240 char res6[331];
1241} ccsr_cpm_i2c_t;
1242
1243/* 0x919c0-0x919ef: CPM core */
1244typedef struct ccsr_cpm_cp {
1245 uint cpcr;
1246 uint rccr;
1247 char res1[14];
1248 ushort rter;
1249 char res2[2];
1250 ushort rtmr;
1251 ushort rtscr;
1252 char res3[2];
1253 uint rtsr;
1254 char res4[12];
1255} ccsr_cpm_cp_t;
1256
1257/* 0x919f0-0x919ff: BRGs:1,2,3,4 */
1258typedef struct ccsr_cpm_brg1 {
1259 uint brgc1;
1260 uint brgc2;
1261 uint brgc3;
1262 uint brgc4;
1263} ccsr_cpm_brg1_t;
1264
1265/* 0x91a00-0x91a9f: SCC1-SCC4 */
1266typedef struct ccsr_cpm_scc {
1267 uint gsmrl;
1268 uint gsmrh;
1269 ushort psmr;
1270 char res1[2];
1271 ushort todr;
1272 ushort dsr;
1273 ushort scce;
1274 char res2[2];
1275 ushort sccm;
1276 char res3;
1277 u_char sccs;
1278 char res4[8];
1279} ccsr_cpm_scc_t;
1280
1281/* 0x91a80-0x91a9f */
1282typedef struct ccsr_cpm_tmp2 {
1283 char res[32];
1284} ccsr_cpm_tmp2_t;
1285
1286/* 0x91aa0-0x91aff: SPI */
1287typedef struct ccsr_cpm_spi {
1288 ushort spmode;
1289 char res1[4];
1290 u_char spie;
1291 char res2[3];
1292 u_char spim;
1293 char res3[2];
1294 u_char spcom;
1295 char res4[82];
1296} ccsr_cpm_spi_t;
1297
1298/* 0x91b00-0x91b1f: CPM MUX */
1299typedef struct ccsr_cpm_mux {
1300 u_char cmxsi1cr;
1301 char res1;
1302 u_char cmxsi2cr;
1303 char res2;
1304 uint cmxfcr;
1305 uint cmxscr;
1306 char res3[2];
1307 ushort cmxuar;
1308 char res4[16];
1309} ccsr_cpm_mux_t;
1310
1311/* 0x91b20-0xbffff: SI,MCC,etc */
1312typedef struct ccsr_cpm_tmp3 {
1313 char res[58592];
1314} ccsr_cpm_tmp3_t;
1315
1316typedef struct ccsr_cpm_iram {
1317 unsigned long iram[8192];
1318 char res[98304];
1319} ccsr_cpm_iram_t;
1320
1321typedef struct ccsr_cpm {
1322 /* Some references are into the unique and known dpram spaces,
1323 * others are from the generic base.
1324 */
1325#define im_dprambase im_dpram1
1326 u_char im_dpram1[16*1024];
1327 char res1[16*1024];
1328 u_char im_dpram2[16*1024];
1329 char res2[16*1024];
wdenk42d1f032003-10-15 23:53:47 +00001330 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
1331 ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
1332 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
1333 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
1334 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
1335 ccsr_cpm_fcc1_t im_cpm_fcc1;
1336 ccsr_cpm_fcc2_t im_cpm_fcc2;
1337 ccsr_cpm_fcc3_t im_cpm_fcc3;
1338 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1339 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1340 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1341 ccsr_cpm_tmp1_t im_cpm_tmp1;
1342 ccsr_cpm_brg2_t im_cpm_brg2;
1343 ccsr_cpm_i2c_t im_cpm_i2c;
1344 ccsr_cpm_cp_t im_cpm_cp;
1345 ccsr_cpm_brg1_t im_cpm_brg1;
1346 ccsr_cpm_scc_t im_cpm_scc[4];
1347 ccsr_cpm_tmp2_t im_cpm_tmp2;
1348 ccsr_cpm_spi_t im_cpm_spi;
1349 ccsr_cpm_mux_t im_cpm_mux;
1350 ccsr_cpm_tmp3_t im_cpm_tmp3;
1351 ccsr_cpm_iram_t im_cpm_iram;
1352} ccsr_cpm_t;
1353#endif
wdenk42d1f032003-10-15 23:53:47 +00001354
Jon Loeligerde1d0a62005-08-01 13:20:47 -05001355/*
1356 * RapidIO Registers(0xc_0000-0xe_0000)
1357 */
wdenk42d1f032003-10-15 23:53:47 +00001358typedef struct ccsr_rio {
1359 uint didcar; /* 0xc0000 - Device Identity Capability Register */
1360 uint dicar; /* 0xc0004 - Device Information Capability Register */
1361 uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
1362 uint aicar; /* 0xc000c - Assembly Information Capability Register */
1363 uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
1364 uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
1365 uint socar; /* 0xc0018 - Source Operations Capability Register */
1366 uint docar; /* 0xc001c - Destination Operations Capability Register */
1367 char res1[32];
1368 uint msr; /* 0xc0040 - Mailbox Command And Status Register */
1369 uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
1370 char res2[4];
1371 uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
1372 char res3[12];
1373 uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
1374 uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
1375 char res4[4];
1376 uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
1377 uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
1378 char res5[144];
1379 uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
1380 char res6[28];
1381 uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
1382 uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
1383 char res7[20];
1384 uint pgccsr; /* 0xc013c - Port General Command and Status Register */
1385 uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
1386 uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
1387 uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
1388 char res8[12];
1389 uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
1390 uint pccsr; /* 0xc015c - Port Control Command and Status Register */
1391 char res9[65184];
1392 uint cr; /* 0xd0000 - Port Control Command and Status Register */
1393 char res10[12];
1394 uint pcr; /* 0xd0010 - Port Configuration Register */
1395 uint peir; /* 0xd0014 - Port Error Injection Register */
1396 char res11[3048];
1397 uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
1398 char res12[12];
1399 uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
1400 char res13[12];
1401 uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
1402 char res14[4];
1403 uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
1404 char res15[4];
1405 uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
1406 char res16[12];
1407 uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
1408 char res17[4];
1409 uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
1410 char res18[4];
1411 uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
1412 char res19[12];
1413 uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
1414 char res20[4];
1415 uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
1416 char res21[4];
1417 uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
1418 char res22[12];
1419 uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
1420 char res23[4];
1421 uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
1422 char res24[4];
1423 uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
1424 char res25[12];
1425 uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
1426 char res26[4];
1427 uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
1428 char res27[4];
1429 uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
1430 char res28[12];
1431 uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
1432 char res29[4];
1433 uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
1434 char res30[4];
1435 uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
1436 char res31[12];
1437 uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
1438 char res32[4];
1439 uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
1440 char res33[4];
1441 uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
1442 char res34[12];
1443 uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
1444 char res35[4];
1445 uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
1446 char res36[4];
1447 uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
1448 char res37[76];
1449 uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
1450 char res38[4];
1451 uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
1452 char res39[4];
1453 uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
1454 char res40[12];
1455 uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
1456 char res41[4];
1457 uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
1458 char res42[4];
1459 uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
1460 char res43[12];
1461 uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
1462 char res44[4];
1463 uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
1464 char res45[4];
1465 uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
1466 char res46[12];
1467 uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
1468 char res47[4];
1469 uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
1470 char res48[4];
1471 uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
1472 char res49[12];
1473 uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
1474 char res50[12];
1475 uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
1476 char res51[12];
1477 uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
1478 uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
1479 uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
1480 uint pecr; /* 0xd0e0c - Port Error Control Register */
1481 uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
1482 uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
1483 uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
1484 char res52[4];
1485 uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
1486 char res53[4];
1487 uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
1488 uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
1489 char res54[464];
1490 uint omr; /* 0xd1000 - Outbound Mode Register */
1491 uint osr; /* 0xd1004 - Outbound Status Register */
1492 uint eodqtpar; /* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
1493 uint odqtpar; /* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */
1494 uint eosar; /* 0xd1010 - Extended Outbound Unit Source Address Register */
1495 uint osar; /* 0xd1014 - Outbound Unit Source Address Register */
1496 uint odpr; /* 0xd1018 - Outbound Destination Port Register */
1497 uint odatr; /* 0xd101c - Outbound Destination Attributes Register */
1498 uint odcr; /* 0xd1020 - Outbound Doubleword Count Register */
1499 uint eodqhpar; /* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
1500 uint odqhpar; /* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */
1501 char res55[52];
1502 uint imr; /* 0xd1060 - Outbound Mode Register */
1503 uint isr; /* 0xd1064 - Inbound Status Register */
1504 uint eidqtpar; /* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
1505 uint idqtpar; /* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */
1506 uint eifqhpar; /* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */
1507 uint ifqhpar; /* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */
1508 char res56[1000];
1509 uint dmr; /* 0xd1460 - Doorbell Mode Register */
1510 uint dsr; /* 0xd1464 - Doorbell Status Register */
1511 uint edqtpar; /* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */
1512 uint dqtpar; /* 0xd146c - Doorbell Queue Tail Pointer Address Register */
1513 uint edqhpar; /* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */
1514 uint dqhpar; /* 0xd1474 - Doorbell Queue Head Pointer Address Register */
1515 char res57[104];
1516 uint pwmr; /* 0xd14e0 - Port-Write Mode Register */
1517 uint pwsr; /* 0xd14e4 - Port-Write Status Register */
1518 uint epwqbar; /* 0xd14e8 - Extended Port-Write Queue Base Address Register */
1519 uint pwqbar; /* 0xd14ec - Port-Write Queue Base Address Register */
1520 char res58[60176];
1521} ccsr_rio_t;
1522
Jon Loeligerde1d0a62005-08-01 13:20:47 -05001523/*
1524 * Global Utilities Register Block(0xe_0000-0xf_ffff)
1525 */
wdenk42d1f032003-10-15 23:53:47 +00001526typedef struct ccsr_gur {
1527 uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
1528 uint porbmsr; /* 0xe0004 - POR boot mode status register */
1529 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
1530 uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
1531 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
1532 char res1[12];
1533 uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
1534 char res2[12];
1535 uint gpiocr; /* 0xe0030 - GPIO control register */
1536 char res3[12];
1537 uint gpoutdr; /* 0xe0040 - General-purpose output data register */
1538 char res4[12];
1539 uint gpindr; /* 0xe0050 - General-purpose input data register */
1540 char res5[12];
1541 uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
1542 char res6[12];
1543 uint devdisr; /* 0xe0070 - Device disable control */
1544 char res7[12];
1545 uint powmgtcsr; /* 0xe0080 - Power management status and control register */
1546 char res8[12];
1547 uint mcpsumr; /* 0xe0090 - Machine check summary register */
1548 char res9[12];
1549 uint pvr; /* 0xe00a0 - Processor version register */
1550 uint svr; /* 0xe00a4 - System version register */
1551 char res10[3416];
1552 uint clkocr; /* 0xe0e00 - Clock out select register */
1553 char res11[12];
1554 uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
1555 char res12[12];
1556 uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001557 char res13[248];
1558 uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */
1559 uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */
1560 uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */
1561 uint res14; /* 0xe0f28 */
1562 uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
1563 char res15[61651];
wdenk42d1f032003-10-15 23:53:47 +00001564} ccsr_gur_t;
1565
Matthew McClintock97074ed2006-06-28 10:45:17 -05001566#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
1567
wdenk42d1f032003-10-15 23:53:47 +00001568typedef struct immap {
1569 ccsr_local_ecm_t im_local_ecm;
1570 ccsr_ddr_t im_ddr;
1571 ccsr_i2c_t im_i2c;
1572 ccsr_duart_t im_duart;
1573 ccsr_lbc_t im_lbc;
1574 ccsr_pcix_t im_pcix;
Matthew McClintock97074ed2006-06-28 10:45:17 -05001575 ccsr_pcix_t im_pcix2;
1576 char reserved[90112];
wdenk42d1f032003-10-15 23:53:47 +00001577 ccsr_l2cache_t im_l2cache;
1578 ccsr_dma_t im_dma;
1579 ccsr_tsec_t im_tsec1;
1580 ccsr_tsec_t im_tsec2;
1581 ccsr_pic_t im_pic;
1582 ccsr_cpm_t im_cpm;
1583 ccsr_rio_t im_rio;
1584 ccsr_gur_t im_gur;
1585} immap_t;
1586
1587extern immap_t *immr;
1588
1589#endif /*__IMMAP_85xx__*/