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wdenk8ed96042005-01-09 23:16:25 +00001/*
2 * (C) Copyright 2004
3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Kshitij Gupta <kshitij@ti.com>
6 *
7 * Configuration settings for the 242x TI H4 board.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 */
34#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
35#define CONFIG_OMAP 1 /* in a TI OMAP core */
36#define CONFIG_OMAP2420 1 /* which is in a 2420 */
37#define CONFIG_OMAP2420H4 1 /* and on a H4 board */
wdenk082acfd2005-01-10 00:01:04 +000038/*#define CONFIG_APTIX 1 #* define if on APTIX test chip */
39/*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */
wdenk8ed96042005-01-09 23:16:25 +000040
wdenk289f9322005-01-12 00:15:14 +000041/* Clock config to target*/
Wolfgang Denk49a75812005-09-25 18:41:04 +020042#define PRCM_CONFIG_II 1
Wolfgang Denk716c1dc2005-09-25 18:49:35 +020043/* #define PRCM_CONFIG_III 1 */
wdenk8ed96042005-01-09 23:16:25 +000044
45#include <asm/arch/omap2420.h> /* get chip and board defs */
46
wdenk289f9322005-01-12 00:15:14 +000047/* On H4, NOR and NAND flash are mutual exclusive.
48 Define this if you want to use NAND
49 */
wdenk5a95f6f2005-01-12 00:38:03 +000050/*#define CFG_NAND_BOOT */
wdenk289f9322005-01-12 00:15:14 +000051
wdenk8ed96042005-01-09 23:16:25 +000052#ifdef CONFIG_APTIX
53#define V_SCLK 1500000
54#else
55#define V_SCLK 12000000
56#endif
57
58/* input clock of PLL */
59/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
60#define CONFIG_SYS_CLK_FREQ V_SCLK
61
62#undef CONFIG_USE_IRQ /* no support for IRQs */
63#define CONFIG_MISC_INIT_R
64
65#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
66#define CONFIG_SETUP_MEMORY_TAGS 1
67#define CONFIG_INITRD_TAG 1
wdenk289f9322005-01-12 00:15:14 +000068#define CONFIG_REVISION_TAG 1
wdenk8ed96042005-01-09 23:16:25 +000069
70/*
71 * Size of malloc() pool
72 */
73#define CFG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
74#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K)
75#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
76
77/*
78 * Hardware drivers
79 */
wdenk082acfd2005-01-10 00:01:04 +000080
wdenk8ed96042005-01-09 23:16:25 +000081/*
82 * SMC91c96 Etherent
83 */
84#define CONFIG_DRIVER_LAN91C96
85#define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300)
86#define CONFIG_LAN91C96_EXT_PHY
87
88/*
89 * NS16550 Configuration
90 */
91#ifdef CONFIG_APTIX
92#define V_NS16550_CLK (6000000) /* 6MHz in current MaxSet */
93#else
94#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
95#endif
96
97#define CFG_NS16550
98#define CFG_NS16550_SERIAL
99#define CFG_NS16550_REG_SIZE (-4)
100#define CFG_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */
101#define CFG_NS16550_COM1 OMAP2420_UART1
102
103/*
104 * select serial console configuration
105 */
106#define CONFIG_SERIAL1 1 /* UART1 on H4 */
107
108 /*
109 * I2C configuration
110 */
111#define CONFIG_HARD_I2C
112#define CFG_I2C_SPEED 100000
113#define CFG_I2C_SLAVE 1
114#define CONFIG_DRIVER_OMAP24XX_I2C
115
116/* allow to overwrite serial and ethaddr */
117#define CONFIG_ENV_OVERWRITE
118#define CONFIG_CONS_INDEX 1
119#define CONFIG_BAUDRATE 115200
120#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
121
wdenk289f9322005-01-12 00:15:14 +0000122#ifdef CFG_NAND_BOOT
123#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_NAND | CFG_CMD_JFFS2)
124#else
Wolfgang Denk49a75812005-09-25 18:41:04 +0200125#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT)
wdenk289f9322005-01-12 00:15:14 +0000126#endif
wdenk8ed96042005-01-09 23:16:25 +0000127#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
128
129/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
130#include <cmd_confdefs.h>
131
wdenk289f9322005-01-12 00:15:14 +0000132/*
133 * Board NAND Info.
134 */
Marian Balakowicz6db39702006-04-08 19:08:06 +0200135#define CFG_NAND_LEGACY
wdenk289f9322005-01-12 00:15:14 +0000136#define CFG_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/
137
138#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
139#define SECTORSIZE 512
140
141#define ADDR_COLUMN 1
142#define ADDR_PAGE 2
143#define ADDR_COLUMN_PAGE 3
144
145#define NAND_ChipID_UNKNOWN 0x00
146#define NAND_MAX_FLOORS 1
147#define NAND_MAX_CHIPS 1
148
149#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0)
150#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0)
151#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0)
152#define READ_NAND(adr) (*(volatile u16 *)0x6800A084)
153#define NAND_WAIT_READY(nand) udelay(10)
154
155#define NAND_NO_RB 1
156
157#define CFG_NAND_WP
158#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
159#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
160
wdenk289f9322005-01-12 00:15:14 +0000161#define NAND_CTL_CLRALE(nandptr)
162#define NAND_CTL_SETALE(nandptr)
163#define NAND_CTL_CLRCLE(nandptr)
164#define NAND_CTL_SETCLE(nandptr)
165#define NAND_DISABLE_CE(nand)
166#define NAND_ENABLE_CE(nand)
167
wdenk8ed96042005-01-09 23:16:25 +0000168#define CONFIG_BOOTDELAY 3
169
170#ifdef NFS_BOOT_DEFAULTS
171#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp"
172#else
173#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
174#endif
175
176#define CONFIG_NETMASK 255.255.254.0
177#define CONFIG_IPADDR 128.247.77.90
178#define CONFIG_SERVERIP 128.247.77.158
179#define CONFIG_BOOTFILE "uImage"
180
181/*
182 * Miscellaneous configurable options
183 */
184#ifdef CONFIG_APTIX
185#define V_PROMPT "OMAP2420 Aptix # "
186#else
187#define V_PROMPT "OMAP242x H4 # "
188#endif
189
190#define CFG_LONGHELP /* undef to save memory */
191#define CFG_PROMPT V_PROMPT
192#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
193/* Print Buffer Size */
194#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
195#define CFG_MAXARGS 16 /* max number of command args */
196#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
197
198#define CFG_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */
199#define CFG_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
200
201#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
202
203#define CFG_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */
204
205/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
206 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
207 */
208#ifdef CONFIG_APTIX
209#define V_PVT 3
210#else
211#define V_PVT 7 /* use with 12MHz/128 */
212#endif
213
214#define CFG_TIMERBASE OMAP2420_GPT2
215#define CFG_PVT V_PVT /* 2^(pvt+1) */
216#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
217
218/*-----------------------------------------------------------------------
219 * Stack sizes
220 *
221 * The stack sizes are set up in start.S using the settings below
222 */
223#define CONFIG_STACKSIZE SZ_128K /* regular stack */
224#ifdef CONFIG_USE_IRQ
225#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
226#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
227#endif
228
229/*-----------------------------------------------------------------------
230 * Physical Memory Map
231 */
232#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
233#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0
234#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
235#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
236
Wolfgang Denk49a75812005-09-25 18:41:04 +0200237#define PHYS_FLASH_SECT_SIZE SZ_128K
wdenk8ed96042005-01-09 23:16:25 +0000238#define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */
239#define PHYS_FLASH_SIZE_1 SZ_32M
240#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
241#define PHYS_FLASH_SIZE_2 SZ_32M
wdenk8ed96042005-01-09 23:16:25 +0000242
243/*-----------------------------------------------------------------------
244 * FLASH and environment organization
245 */
Wolfgang Denk49a75812005-09-25 18:41:04 +0200246#define CFG_FLASH_BASE PHYS_FLASH_1
wdenk8ed96042005-01-09 23:16:25 +0000247#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
248#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
Wolfgang Denk49a75812005-09-25 18:41:04 +0200249#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
250#define CFG_MONITOR_LEN SZ_128K /* Reserve 1 sector */
251#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE_1 }
wdenk8ed96042005-01-09 23:16:25 +0000252
wdenk289f9322005-01-12 00:15:14 +0000253#ifdef CFG_NAND_BOOT
254#define CFG_ENV_IS_IN_NAND 1
255#define CFG_ENV_OFFSET 0x80000 /* environment starts here */
256#else
wdenk8ed96042005-01-09 23:16:25 +0000257#define CFG_ENV_ADDR (CFG_FLASH_BASE + SZ_128K)
258#define CFG_ENV_IS_IN_FLASH 1
Wolfgang Denk49a75812005-09-25 18:41:04 +0200259#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
260#define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */
wdenk289f9322005-01-12 00:15:14 +0000261#endif
wdenk8ed96042005-01-09 23:16:25 +0000262
Wolfgang Denk49a75812005-09-25 18:41:04 +0200263/*-----------------------------------------------------------------------
264 * CFI FLASH driver setup
265 */
266#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
267#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
268#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
269#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
270
wdenk8ed96042005-01-09 23:16:25 +0000271/* timeout values are in ticks */
Wolfgang Denk49a75812005-09-25 18:41:04 +0200272#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */
273#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */
wdenk289f9322005-01-12 00:15:14 +0000274
wdenk289f9322005-01-12 00:15:14 +0000275#define CFG_JFFS2_MEM_NAND
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200276
277/*
278 * JFFS2 partitions
279 */
280/* No command line, one static partition, whole device */
281#undef CONFIG_JFFS2_CMDLINE
282#define CONFIG_JFFS2_DEV "nor1"
283#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
284#define CONFIG_JFFS2_PART_OFFSET 0x00000000
285
286/* mtdparts command line support */
287/* Note: fake mtd_id used, no linux mtd map file */
288/*
289#define CONFIG_JFFS2_CMDLINE
290#define MTDIDS_DEFAULT "nor1=omap2420-1"
291#define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)"
292*/
wdenk8ed96042005-01-09 23:16:25 +0000293
294#endif /* __CONFIG_H */