blob: 0e7d8608a262752cd9529b414f75b3a215fe7642 [file] [log] [blame]
Vikas Manocha9fa32b12014-11-18 10:42:22 -08001/*
2 * (C) Copyright 2014
3 * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef __CONFIG_STV0991_H
9#define __CONFIG_STV0991_H
Vikas Manocha9fa32b12014-11-18 10:42:22 -080010#define CONFIG_SYS_DCACHE_OFF
Vikas Manocha9fa32b12014-11-18 10:42:22 -080011#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
Vikas Manocha2ce4eaf2014-11-18 10:42:23 -080012
Vikas Manocha9fa32b12014-11-18 10:42:22 -080013#define CONFIG_SYS_CORTEX_R4
14
Vikas Manocha9fa32b12014-11-18 10:42:22 -080015#define CONFIG_SYS_NO_FLASH
16
17/* ram memory-related information */
18#define CONFIG_NR_DRAM_BANKS 1
19#define PHYS_SDRAM_1 0x00000000
20#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
21#define PHYS_SDRAM_1_SIZE 0x00198000
22
23#define CONFIG_ENV_SIZE 0x10000
Vikas Manocha137d5b92015-07-02 18:29:37 -070024#define CONFIG_ENV_IS_IN_SPI_FLASH
25#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
26#define CONFIG_ENV_OFFSET 0x30000
Vikas Manocha9fa32b12014-11-18 10:42:22 -080027#define CONFIG_ENV_ADDR \
28 (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE)
29#define CONFIG_SYS_MAXARGS 16
30#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024)
31
32/* serial port (PL011) configuration */
Vikas Manocha9fa32b12014-11-18 10:42:22 -080033#define CONFIG_BAUDRATE 115200
Vikas Manocha39e47952014-12-01 12:27:54 -080034#define CONFIG_PL01X_SERIAL
Vikas Manocha9fa32b12014-11-18 10:42:22 -080035
36/* user interface */
Vikas Manochac55e7592014-11-18 10:42:24 -080037#define CONFIG_SYS_CBSIZE 1024
Vikas Manocha9fa32b12014-11-18 10:42:22 -080038#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
39 +sizeof(CONFIG_SYS_PROMPT) + 16)
40
41/* MISC */
42#define CONFIG_SYS_LOAD_ADDR 0x00000000
Vikas Manocha498b7c22014-12-01 12:27:53 -080043#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
Vikas Manocha9fa32b12014-11-18 10:42:22 -080044#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000
45#define CONFIG_SYS_INIT_SP_OFFSET \
46 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Bin Menga1875592016-02-05 19:30:11 -080047/* U-Boot Load Address */
Vikas Manocha9fa32b12014-11-18 10:42:22 -080048#define CONFIG_SYS_TEXT_BASE 0x00010000
49#define CONFIG_SYS_INIT_SP_ADDR \
50 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
51
Vikas Manocha2ce4eaf2014-11-18 10:42:23 -080052/* GMAC related configs */
53
54#define CONFIG_MII
Vikas Manocha2ce4eaf2014-11-18 10:42:23 -080055#define CONFIG_DW_ALTDESCRIPTOR
56#define CONFIG_PHY_MICREL
57
58/* Command support defines */
Vikas Manocha2ce4eaf2014-11-18 10:42:23 -080059#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
60
Vikas Manochac55e7592014-11-18 10:42:24 -080061#define CONFIG_SYS_MEMTEST_START 0x0000
62#define CONFIG_SYS_MEMTEST_END 1024*1024
Vikas Manochac55e7592014-11-18 10:42:24 -080063
64/* Misc configuration */
65#define CONFIG_SYS_LONGHELP
66#define CONFIG_CMDLINE_EDITING
67
Vikas Manochac55e7592014-11-18 10:42:24 -080068#define CONFIG_BOOTCOMMAND "go 0x40040000"
Stefan Roesed126e012015-05-18 14:08:23 +020069
Vikas Manochae67abca2015-07-02 18:29:41 -070070/*
71+ * QSPI support
72+ */
73#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
Vikas Manochae67abca2015-07-02 18:29:41 -070074#define CONFIG_CQSPI_DECODER 0
75#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000
Vignesh R57897c12016-12-21 10:42:32 +053076#define CONFIG_BOUNCE_BUFFER
Vikas Manochae67abca2015-07-02 18:29:41 -070077
Vikas Manochae67abca2015-07-02 18:29:41 -070078#endif
79
Vikas Manocha9fa32b12014-11-18 10:42:22 -080080#endif /* __CONFIG_H */