Sergey Yanovich | c3442c1 | 2013-05-21 01:26:00 +0400 | [diff] [blame] | 1 | /* |
| 2 | * ICP DAS LP-8x4x configuration file |
| 3 | * |
| 4 | * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com> |
| 5 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Sergey Yanovich | c3442c1 | 2013-05-21 01:26:00 +0400 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __CONFIG_H |
| 10 | #define __CONFIG_H |
| 11 | |
| 12 | /* |
| 13 | * High Level Board Configuration Options |
| 14 | */ |
| 15 | #define CONFIG_CPU_PXA27X /* Marvell PXA270 CPU */ |
| 16 | #define MACH_TYPE_LP8X4X 4539 /* ICP DAS LP-8x4x */ |
| 17 | #define CONFIG_MACH_TYPE MACH_TYPE_LP8X4X |
| 18 | #define CONFIG_SYS_TEXT_BASE 0x00000000 |
| 19 | |
| 20 | #define CONFIG_SYS_MALLOC_LEN (128*1024) |
| 21 | #define CONFIG_ARCH_CPU_INIT |
| 22 | #define CONFIG_BOOTCOMMAND \ |
| 23 | "bootm 80000;" |
| 24 | |
| 25 | #define CONFIG_BOOTARGS \ |
| 26 | "console=ttySA0,115200 mem=128M root=/dev/mmcblk0p1 rw" \ |
| 27 | "init=/sbin/init rootfstype=ext3" |
| 28 | |
| 29 | #define CONFIG_TIMESTAMP |
| 30 | #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ |
| 31 | #define CONFIG_CMDLINE_TAG |
| 32 | #define CONFIG_SETUP_MEMORY_TAGS |
| 33 | #define CONFIG_LZMA /* LZMA compression support */ |
| 34 | #undef CONFIG_OF_LIBFDT |
| 35 | |
| 36 | /* |
| 37 | * Serial Console Configuration |
| 38 | */ |
| 39 | #define CONFIG_PXA_SERIAL |
| 40 | #define CONFIG_FFUART 1 |
| 41 | #define CONFIG_CONS_INDEX 3 |
| 42 | #define CONFIG_BAUDRATE 115200 |
| 43 | |
| 44 | /* |
| 45 | * Bootloader Components Configuration |
| 46 | */ |
| 47 | #include <config_cmd_default.h> |
| 48 | |
| 49 | #define CONFIG_CMD_NET |
| 50 | #define CONFIG_CMD_ENV |
| 51 | #undef CONFIG_CMD_IMLS |
| 52 | #define CONFIG_CMD_MMC |
| 53 | #define CONFIG_CMD_USB |
| 54 | #undef CONFIG_LCD |
| 55 | #undef CONFIG_CMD_IDE |
| 56 | |
| 57 | /* |
| 58 | * Networking Configuration |
| 59 | * chip on the ICPDAS LINPAC board |
| 60 | */ |
| 61 | #ifdef CONFIG_CMD_NET |
| 62 | #define CONFIG_CMD_PING |
| 63 | #define CONFIG_CMD_DHCP |
| 64 | |
| 65 | #define CONFIG_DRIVER_DM9000 1 |
| 66 | #define CONFIG_DM9000_BASE 0x0C000000 |
| 67 | #define DM9000_IO 0x0C000000 |
| 68 | #define DM9000_DATA 0x0C004000 |
| 69 | #define DM9000_IO_2 0x0D000000 |
| 70 | #define DM9000_DATA_2 0x0D004000 |
| 71 | #define CONFIG_NET_RETRY_COUNT 10 |
| 72 | |
| 73 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 74 | #define CONFIG_BOOTP_BOOTPATH |
| 75 | #define CONFIG_BOOTP_GATEWAY |
| 76 | #define CONFIG_BOOTP_HOSTNAME |
| 77 | #endif |
| 78 | |
| 79 | /* |
| 80 | * MMC Card Configuration |
| 81 | */ |
| 82 | #ifdef CONFIG_CMD_MMC |
| 83 | #define CONFIG_MMC |
| 84 | #define CONFIG_GENERIC_MMC |
| 85 | #define CONFIG_PXA_MMC_GENERIC |
| 86 | #define CONFIG_CMD_FAT |
| 87 | #define CONFIG_CMD_EXT2 |
| 88 | #define CONFIG_DOS_PARTITION |
| 89 | #endif |
| 90 | |
| 91 | /* |
| 92 | * KGDB |
| 93 | */ |
| 94 | #ifdef CONFIG_CMD_KGDB |
| 95 | #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ |
| 96 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 97 | #endif |
| 98 | |
| 99 | /* |
| 100 | * HUSH Shell Configuration |
| 101 | */ |
| 102 | #define CONFIG_SYS_HUSH_PARSER 1 |
| 103 | |
| 104 | #undef CONFIG_SYS_LONGHELP |
| 105 | #ifdef CONFIG_SYS_HUSH_PARSER |
| 106 | #define CONFIG_SYS_PROMPT "$ " |
| 107 | #else |
Sergey Yanovich | c3442c1 | 2013-05-21 01:26:00 +0400 | [diff] [blame] | 108 | #endif |
| 109 | #define CONFIG_SYS_CBSIZE 256 |
| 110 | #define CONFIG_SYS_PBSIZE \ |
| 111 | (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
| 112 | #define CONFIG_SYS_MAXARGS 16 |
| 113 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 114 | #define CONFIG_SYS_DEVICE_NULLDEV 1 |
| 115 | #define CONFIG_CMDLINE_EDITING 1 |
| 116 | #define CONFIG_AUTO_COMPLETE 1 |
| 117 | |
| 118 | /* |
Sergey Yanovich | c3442c1 | 2013-05-21 01:26:00 +0400 | [diff] [blame] | 119 | * DRAM Map |
| 120 | */ |
| 121 | #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ |
| 122 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ |
| 123 | #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ |
| 124 | |
| 125 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ |
| 126 | #define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */ |
| 127 | |
| 128 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ |
| 129 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ |
| 130 | |
| 131 | #define CONFIG_SYS_LOAD_ADDR 0xa0008000 |
| 132 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 133 | /* Use first 64kb bank of the internal SRAM */ |
| 134 | #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 |
| 135 | |
| 136 | /* |
| 137 | * NOR FLASH |
| 138 | */ |
| 139 | #define CONFIG_SYS_MONITOR_BASE 0x0 |
| 140 | #define CONFIG_SYS_MONITOR_LEN 0x40000 |
| 141 | #define CONFIG_ENV_ADDR \ |
| 142 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
| 143 | #define CONFIG_ENV_SIZE 0x40000 |
| 144 | #define CONFIG_ENV_SECT_SIZE 0x40000 |
| 145 | |
| 146 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
| 147 | #define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ |
| 148 | |
| 149 | #define CONFIG_SYS_FLASH_CFI |
| 150 | #define CONFIG_FLASH_CFI_DRIVER 1 |
| 151 | |
| 152 | #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) |
| 153 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 |
| 154 | #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } |
| 155 | |
| 156 | #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) |
| 157 | #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) |
| 158 | |
| 159 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
| 160 | #define CONFIG_SYS_FLASH_PROTECTION 1 |
| 161 | |
| 162 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 163 | |
| 164 | /* |
| 165 | * GPIO settings |
| 166 | */ |
| 167 | #define CONFIG_SYS_GPSR0_VAL 0x0808c014 |
| 168 | #define CONFIG_SYS_GPSR1_VAL 0x00cf0002 |
| 169 | #define CONFIG_SYS_GPSR2_VAL 0x0221c000 |
| 170 | #define CONFIG_SYS_GPSR3_VAL 0x00020000 |
| 171 | |
| 172 | #define CONFIG_SYS_GPCR0_VAL 0x00000000 |
| 173 | #define CONFIG_SYS_GPCR1_VAL 0x0000ab80 |
| 174 | #define CONFIG_SYS_GPCR2_VAL 0x00100000 |
| 175 | #define CONFIG_SYS_GPCR3_VAL 0x0 |
| 176 | |
| 177 | #define CONFIG_SYS_GPDR0_VAL 0xc0e9ddf4 |
| 178 | #define CONFIG_SYS_GPDR1_VAL 0xfcffab83 |
| 179 | #define CONFIG_SYS_GPDR2_VAL 0x02f1ffff |
| 180 | #define CONFIG_SYS_GPDR3_VAL 0x00021b81 |
| 181 | |
| 182 | #define CONFIG_SYS_GAFR0_L_VAL 0x80000000 |
| 183 | #define CONFIG_SYS_GAFR0_U_VAL 0xa5e54018 |
| 184 | #define CONFIG_SYS_GAFR1_L_VAL 0x999a955a |
| 185 | #define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a00a |
| 186 | #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa |
| 187 | #define CONFIG_SYS_GAFR2_U_VAL 0x55f0a402 |
| 188 | #define CONFIG_SYS_GAFR3_L_VAL 0x540a950c |
| 189 | #define CONFIG_SYS_GAFR3_U_VAL 0x00001599 |
| 190 | |
| 191 | #define CONFIG_SYS_PSSR_VAL 0x32 |
| 192 | |
| 193 | /* |
| 194 | * Clock settings |
| 195 | */ |
| 196 | #define CONFIG_SYS_CKEN 0x005002c0 |
| 197 | #define CONFIG_SYS_CCCR 0x02000290 |
| 198 | #define CONFIG_SYS_CLKCFG 0x0000000b |
| 199 | |
| 200 | /* |
| 201 | * Memory settings |
| 202 | */ |
| 203 | #define CONFIG_SYS_MSC0_VAL 0x2bd8aad2 |
| 204 | #define CONFIG_SYS_MSC1_VAL 0xb8c9b8dc |
| 205 | #define CONFIG_SYS_MSC2_VAL 0xfff9b8c9 |
| 206 | #define CONFIG_SYS_FLYCNFG_VAL 0x00010001 |
| 207 | #define CONFIG_SYS_MDREFR_VAL 0x2093e018 |
| 208 | #define CONFIG_SYS_MDCNFG_VAL 0x890009d1 |
| 209 | #define CONFIG_SYS_MDMRS_VAL 0x00220022 |
| 210 | #define CONFIG_SYS_SXCNFG_VAL 0x40044004 |
| 211 | |
| 212 | /* |
| 213 | * PCMCIA and CF Interfaces |
| 214 | */ |
| 215 | #define CONFIG_SYS_MECR_VAL 0x00000001 |
| 216 | #define CONFIG_SYS_MCMEM0_VAL 0x0000c497 |
| 217 | #define CONFIG_SYS_MCMEM1_VAL 0x0000c497 |
| 218 | #define CONFIG_SYS_MCATT0_VAL 0x0000c497 |
| 219 | #define CONFIG_SYS_MCATT1_VAL 0x0000c497 |
| 220 | #define CONFIG_SYS_MCIO0_VAL 0x00008407 |
| 221 | #define CONFIG_SYS_MCIO1_VAL 0x00008407 |
| 222 | |
| 223 | /* |
| 224 | * LCD |
| 225 | */ |
| 226 | #ifdef CONFIG_LCD |
| 227 | #define CONFIG_VOIPAC_LCD |
| 228 | #endif |
| 229 | |
| 230 | /* |
| 231 | * USB |
| 232 | */ |
| 233 | #ifdef CONFIG_CMD_USB |
| 234 | #define CONFIG_USB_OHCI_NEW |
| 235 | #define CONFIG_SYS_USB_OHCI_CPU_INIT |
| 236 | #define CONFIG_SYS_USB_OHCI_BOARD_INIT |
| 237 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 |
| 238 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 |
| 239 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "lp8x4x" |
| 240 | #define CONFIG_USB_STORAGE |
| 241 | #endif |
| 242 | |
| 243 | #endif /* __CONFIG_H */ |