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Masahiro Yamada238bd0b2015-01-13 12:44:37 +09001/*
Masahiro Yamada4e3d8402016-07-19 21:56:13 +09002 * Copyright (C) 2014 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada238bd0b2015-01-13 12:44:37 +09005 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <linux/types.h>
Masahiro Yamadaf6e7f072015-05-29 17:30:00 +090011#include <linux/io.h>
Masahiro Yamada336399f2016-03-24 22:32:40 +090012#include <linux/sizes.h>
Masahiro Yamada238bd0b2015-01-13 12:44:37 +090013#include <asm/errno.h>
14#include <dm/device.h>
15#include <dm/root.h>
16#include <i2c.h>
17#include <fdtdec.h>
18
Masahiro Yamada238bd0b2015-01-13 12:44:37 +090019struct uniphier_fi2c_regs {
20 u32 cr; /* control register */
21#define I2C_CR_MST (1 << 3) /* master mode */
22#define I2C_CR_STA (1 << 2) /* start condition */
23#define I2C_CR_STO (1 << 1) /* stop condition */
24#define I2C_CR_NACK (1 << 0) /* not ACK */
25 u32 dttx; /* send FIFO (write-only) */
26#define dtrx dttx /* receive FIFO (read-only) */
27#define I2C_DTTX_CMD (1 << 8) /* send command (slave addr) */
28#define I2C_DTTX_RD (1 << 0) /* read */
29 u32 __reserved; /* no register at offset 0x08 */
30 u32 slad; /* slave address */
31 u32 cyc; /* clock cycle control */
32 u32 lctl; /* clock low period control */
33 u32 ssut; /* restart/stop setup time control */
34 u32 dsut; /* data setup time control */
35 u32 intr; /* interrupt status */
36 u32 ie; /* interrupt enable */
37 u32 ic; /* interrupt clear */
38#define I2C_INT_TE (1 << 9) /* TX FIFO empty */
39#define I2C_INT_RB (1 << 4) /* received specified bytes */
40#define I2C_INT_NA (1 << 2) /* no answer */
41#define I2C_INT_AL (1 << 1) /* arbitration lost */
42 u32 sr; /* status register */
43#define I2C_SR_DB (1 << 12) /* device busy */
44#define I2C_SR_BB (1 << 8) /* bus busy */
45#define I2C_SR_RFF (1 << 3) /* Rx FIFO full */
46#define I2C_SR_RNE (1 << 2) /* Rx FIFO not empty */
47#define I2C_SR_TNF (1 << 1) /* Tx FIFO not full */
48#define I2C_SR_TFE (1 << 0) /* Tx FIFO empty */
49 u32 __reserved2; /* no register at offset 0x30 */
50 u32 rst; /* reset control */
51#define I2C_RST_TBRST (1 << 2) /* clear Tx FIFO */
52#define I2C_RST_RBRST (1 << 1) /* clear Rx FIFO */
53#define I2C_RST_RST (1 << 0) /* forcible bus reset */
54 u32 bm; /* bus monitor */
55 u32 noise; /* noise filter control */
56 u32 tbc; /* Tx byte count setting */
57 u32 rbc; /* Rx byte count setting */
58 u32 tbcm; /* Tx byte count monitor */
59 u32 rbcm; /* Rx byte count monitor */
60 u32 brst; /* bus reset */
61#define I2C_BRST_FOEN (1 << 1) /* normal operation */
62#define I2C_BRST_RSCLO (1 << 0) /* release SCL low fixing */
63};
64
65#define FIOCLK 50000000
66
67struct uniphier_fi2c_dev {
68 struct uniphier_fi2c_regs __iomem *regs; /* register base */
69 unsigned long fioclk; /* internal operation clock */
70 unsigned long timeout; /* time out (us) */
71};
72
73static int poll_status(u32 __iomem *reg, u32 flag)
74{
75 int wait = 1000000; /* 1 sec is long enough */
76
77 while (readl(reg) & flag) {
78 if (wait-- < 0)
79 return -EREMOTEIO;
80 udelay(1);
81 }
82
83 return 0;
84}
85
86static int reset_bus(struct uniphier_fi2c_regs __iomem *regs)
87{
88 int ret;
89
90 /* bus forcible reset */
91 writel(I2C_RST_RST, &regs->rst);
92 ret = poll_status(&regs->rst, I2C_RST_RST);
93 if (ret < 0)
94 debug("error: fail to reset I2C controller\n");
95
96 return ret;
97}
98
99static int check_device_busy(struct uniphier_fi2c_regs __iomem *regs)
100{
101 int ret;
102
103 ret = poll_status(&regs->sr, I2C_SR_DB);
104 if (ret < 0) {
105 debug("error: device busy too long. reset...\n");
106 ret = reset_bus(regs);
107 }
108
109 return ret;
110}
111
112static int uniphier_fi2c_probe(struct udevice *dev)
113{
114 fdt_addr_t addr;
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900115 struct uniphier_fi2c_dev *priv = dev_get_priv(dev);
116 int ret;
117
Masahiro Yamada336399f2016-03-24 22:32:40 +0900118 addr = dev_get_addr(dev);
119 if (addr == FDT_ADDR_T_NONE)
120 return -EINVAL;
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900121
Masahiro Yamada4e3d8402016-07-19 21:56:13 +0900122 priv->regs = devm_ioremap(dev, addr, SZ_128);
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900123 if (!priv->regs)
124 return -ENOMEM;
125
126 priv->fioclk = FIOCLK;
127
128 /* bus forcible reset */
129 ret = reset_bus(priv->regs);
130 if (ret < 0)
131 return ret;
132
133 writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &priv->regs->brst);
134
135 return 0;
136}
137
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900138static int wait_for_irq(struct uniphier_fi2c_dev *dev, u32 flags,
139 bool *stop)
140{
141 u32 irq;
142 unsigned long wait = dev->timeout;
143 int ret = -EREMOTEIO;
144
145 do {
146 udelay(1);
147 irq = readl(&dev->regs->intr);
148 } while (!(irq & flags) && wait--);
149
150 if (wait < 0) {
151 debug("error: time out\n");
152 return ret;
153 }
154
155 if (irq & I2C_INT_AL) {
156 debug("error: arbitration lost\n");
157 *stop = false;
158 return ret;
159 }
160
161 if (irq & I2C_INT_NA) {
162 debug("error: no answer\n");
163 return ret;
164 }
165
166 return 0;
167}
168
169static int issue_stop(struct uniphier_fi2c_dev *dev, int old_ret)
170{
171 int ret;
172
173 debug("stop condition\n");
174 writel(I2C_CR_MST | I2C_CR_STO, &dev->regs->cr);
175
176 ret = poll_status(&dev->regs->sr, I2C_SR_DB);
177 if (ret < 0)
178 debug("error: device busy after operation\n");
179
180 return old_ret ? old_ret : ret;
181}
182
183static int uniphier_fi2c_transmit(struct uniphier_fi2c_dev *dev, uint addr,
184 uint len, const u8 *buf, bool *stop)
185{
186 int ret;
187 const u32 irq_flags = I2C_INT_TE | I2C_INT_NA | I2C_INT_AL;
188 struct uniphier_fi2c_regs __iomem *regs = dev->regs;
189
190 debug("%s: addr = %x, len = %d\n", __func__, addr, len);
191
192 writel(I2C_DTTX_CMD | addr << 1, &regs->dttx);
193
194 writel(irq_flags, &regs->ie);
195 writel(irq_flags, &regs->ic);
196
197 debug("start condition\n");
198 writel(I2C_CR_MST | I2C_CR_STA, &regs->cr);
199
200 ret = wait_for_irq(dev, irq_flags, stop);
201 if (ret < 0)
202 goto error;
203
204 while (len--) {
205 debug("sending %x\n", *buf);
206 writel(*buf++, &regs->dttx);
207
208 writel(irq_flags, &regs->ic);
209
210 ret = wait_for_irq(dev, irq_flags, stop);
211 if (ret < 0)
212 goto error;
213 }
214
215error:
216 writel(irq_flags, &regs->ic);
217
218 if (*stop)
219 ret = issue_stop(dev, ret);
220
221 return ret;
222}
223
224static int uniphier_fi2c_receive(struct uniphier_fi2c_dev *dev, uint addr,
225 uint len, u8 *buf, bool *stop)
226{
227 int ret = 0;
228 const u32 irq_flags = I2C_INT_RB | I2C_INT_NA | I2C_INT_AL;
229 struct uniphier_fi2c_regs __iomem *regs = dev->regs;
230
231 debug("%s: addr = %x, len = %d\n", __func__, addr, len);
232
233 /*
234 * In case 'len == 0', only the slave address should be sent
235 * for probing, which is covered by the transmit function.
236 */
237 if (len == 0)
238 return uniphier_fi2c_transmit(dev, addr, len, buf, stop);
239
240 writel(I2C_DTTX_CMD | I2C_DTTX_RD | addr << 1, &regs->dttx);
241
242 writel(0, &regs->rbc);
243 writel(irq_flags, &regs->ie);
244 writel(irq_flags, &regs->ic);
245
246 debug("start condition\n");
247 writel(I2C_CR_MST | I2C_CR_STA | (len == 1 ? I2C_CR_NACK : 0),
248 &regs->cr);
249
250 while (len--) {
251 ret = wait_for_irq(dev, irq_flags, stop);
252 if (ret < 0)
253 goto error;
254
255 *buf++ = readl(&regs->dtrx);
256 debug("received %x\n", *(buf - 1));
257
258 if (len == 1)
259 writel(I2C_CR_MST | I2C_CR_NACK, &regs->cr);
260
261 writel(irq_flags, &regs->ic);
262 }
263
264error:
265 writel(irq_flags, &regs->ic);
266
267 if (*stop)
268 ret = issue_stop(dev, ret);
269
270 return ret;
271}
272
273static int uniphier_fi2c_xfer(struct udevice *bus, struct i2c_msg *msg,
274 int nmsgs)
275{
276 int ret;
277 struct uniphier_fi2c_dev *dev = dev_get_priv(bus);
278 bool stop;
279
280 ret = check_device_busy(dev->regs);
281 if (ret < 0)
282 return ret;
283
284 for (; nmsgs > 0; nmsgs--, msg++) {
285 /* If next message is read, skip the stop condition */
286 stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;
287
288 if (msg->flags & I2C_M_RD)
289 ret = uniphier_fi2c_receive(dev, msg->addr, msg->len,
290 msg->buf, &stop);
291 else
292 ret = uniphier_fi2c_transmit(dev, msg->addr, msg->len,
293 msg->buf, &stop);
294
295 if (ret < 0)
296 break;
297 }
298
299 return ret;
300}
301
302static int uniphier_fi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
303{
304 int ret;
305 unsigned int clk_count;
306 struct uniphier_fi2c_dev *dev = dev_get_priv(bus);
307 struct uniphier_fi2c_regs __iomem *regs = dev->regs;
308
309 /* max supported frequency is 400 kHz */
310 if (speed > 400000)
311 return -EINVAL;
312
313 ret = check_device_busy(dev->regs);
314 if (ret < 0)
315 return ret;
316
317 /* make sure the bus is idle when changing the frequency */
318 writel(I2C_BRST_RSCLO, &regs->brst);
319
320 clk_count = dev->fioclk / speed;
321
322 writel(clk_count, &regs->cyc);
323 writel(clk_count / 2, &regs->lctl);
324 writel(clk_count / 2, &regs->ssut);
325 writel(clk_count / 16, &regs->dsut);
326
327 writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &regs->brst);
328
329 /*
330 * Theoretically, each byte can be transferred in
331 * 1000000 * 9 / speed usec.
332 * This time out value is long enough.
333 */
334 dev->timeout = 100000000L / speed;
335
336 return 0;
337}
338
339static const struct dm_i2c_ops uniphier_fi2c_ops = {
340 .xfer = uniphier_fi2c_xfer,
341 .set_bus_speed = uniphier_fi2c_set_bus_speed,
342};
343
344static const struct udevice_id uniphier_fi2c_of_match[] = {
Masahiro Yamada6462cde2015-03-11 15:54:46 +0900345 { .compatible = "socionext,uniphier-fi2c" },
346 { /* sentinel */ }
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900347};
348
349U_BOOT_DRIVER(uniphier_fi2c) = {
350 .name = "uniphier-fi2c",
351 .id = UCLASS_I2C,
352 .of_match = uniphier_fi2c_of_match,
353 .probe = uniphier_fi2c_probe,
Masahiro Yamada238bd0b2015-01-13 12:44:37 +0900354 .priv_auto_alloc_size = sizeof(struct uniphier_fi2c_dev),
355 .ops = &uniphier_fi2c_ops,
356};