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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Yusuke Godac133c1f2008-03-11 12:55:12 +09002/*
3 * Configuation settings for the Renesas R7780MP board
4 *
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +09005 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Yusuke Godac133c1f2008-03-11 12:55:12 +09006 * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
Yusuke Godac133c1f2008-03-11 12:55:12 +09007 */
8
9#ifndef __R7780RP_H
10#define __R7780RP_H
11
Yusuke Godac133c1f2008-03-11 12:55:12 +090012#define CONFIG_CPU_SH7780 1
13#define CONFIG_R7780MP 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020014#define CONFIG_SYS_R7780MP_OLD_FLASH 1
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +090015#define __LITTLE_ENDIAN__ 1
Yusuke Godac133c1f2008-03-11 12:55:12 +090016
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020017#define CONFIG_DISPLAY_BOARDINFO
18
Yusuke Godac133c1f2008-03-11 12:55:12 +090019#define CONFIG_CONS_SCIF0 1
20
Yusuke Godac133c1f2008-03-11 12:55:12 +090021#define CONFIG_ENV_OVERWRITE 1
22
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020023#define CONFIG_SYS_SDRAM_BASE (0x08000000)
24#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
Yusuke Godac133c1f2008-03-11 12:55:12 +090025
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026#define CONFIG_SYS_PBSIZE 256
Yusuke Godac133c1f2008-03-11 12:55:12 +090027
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +090028/* Flash board support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029#define CONFIG_SYS_FLASH_BASE (0xA0000000)
30#ifdef CONFIG_SYS_R7780MP_OLD_FLASH
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +090031/* NOR Flash (S29PL127J60TFI130) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
33# define CONFIG_SYS_MAX_FLASH_BANKS (2)
34# define CONFIG_SYS_MAX_FLASH_SECT 270
35# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
36 CONFIG_SYS_FLASH_BASE + 0x100000,\
37 CONFIG_SYS_FLASH_BASE + 0x400000,\
38 CONFIG_SYS_FLASH_BASE + 0x700000, }
39#else /* CONFIG_SYS_R7780MP_OLD_FLASH */
Nobuhiro Iwamatsuec39d472008-06-17 16:28:01 +090040/* NOR Flash (Spantion S29GL256P) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041# define CONFIG_SYS_MAX_FLASH_BANKS (1)
42# define CONFIG_SYS_MAX_FLASH_SECT 256
43# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
44#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */
Yusuke Godac133c1f2008-03-11 12:55:12 +090045
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
Yusuke Godac133c1f2008-03-11 12:55:12 +090047/* Address of u-boot image in Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
49#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
Yusuke Godac133c1f2008-03-11 12:55:12 +090050/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_MALLOC_LEN (1204 * 1024)
Yusuke Godac133c1f2008-03-11 12:55:12 +090052
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
54#define CONFIG_SYS_RX_ETH_BUFFER (8)
Yusuke Godac133c1f2008-03-11 12:55:12 +090055
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
57#undef CONFIG_SYS_FLASH_QUIET_TEST
Yusuke Godac133c1f2008-03-11 12:55:12 +090058/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_FLASH_EMPTY_INFO
Yusuke Godac133c1f2008-03-11 12:55:12 +090060
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
62#define CONFIG_SYS_FLASH_WRITE_TOUT 500
Yusuke Godac133c1f2008-03-11 12:55:12 +090063
64/* Board Clock */
65#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +090066#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Yusuke Godac133c1f2008-03-11 12:55:12 +090067
68/* PCI Controller */
69#if defined(CONFIG_CMD_PCI)
Yusuke Godac133c1f2008-03-11 12:55:12 +090070#define CONFIG_SH4_PCI
Nobuhiro Iwamatsuab8f4d42008-03-24 02:11:26 +090071#define CONFIG_SH7780_PCI
Yoshihiro Shimoda06b18162009-02-25 14:26:42 +090072#define CONFIG_SH7780_PCI_LSR 0x07f00001
73#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
74#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
Yusuke Godac133c1f2008-03-11 12:55:12 +090075#define CONFIG_PCI_SCAN_SHOW 1
Yusuke Godac133c1f2008-03-11 12:55:12 +090076#define __mem_pci
77
78#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
79#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
80#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
81
82#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
83#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
84#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
Nobuhiro Iwamatsu04366d02009-07-08 11:42:19 +090085#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
86#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
87#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
Yusuke Godac133c1f2008-03-11 12:55:12 +090088#endif /* CONFIG_CMD_PCI */
89
90#if defined(CONFIG_CMD_NET)
Marcel Ziswilerc7c1dbb2009-09-09 21:09:00 +020091/* AX88796L Support(NE2000 base chip) */
Yusuke Godac133c1f2008-03-11 12:55:12 +090092#define CONFIG_DRIVER_AX88796L
93#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
94#endif
95
96/* Compact flash Support */
Simon Glassfc843a02017-05-17 03:25:30 -060097#if defined(CONFIG_IDE)
Yusuke Godac133c1f2008-03-11 12:55:12 +090098#define CONFIG_IDE_RESET 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_PIO_MODE 1
100#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
101#define CONFIG_SYS_IDE_MAXDEVICE 1
102#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
103#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
104#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
105#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
106#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
Albert Aribaudf2a37fc2010-08-08 05:17:05 +0530107#define CONFIG_IDE_SWAP_IO
Simon Glassfc843a02017-05-17 03:25:30 -0600108#endif /* CONFIG_IDE */
Yusuke Godac133c1f2008-03-11 12:55:12 +0900109
110#endif /* __R7780RP_H */