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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 7282d834cd47cabc481a5cbe6e686ef40751436f / . / arch / x86 / cpu / interrupts.c
blob: e733bcb30272fa0da847cac08ca318eac4ee61ee [file] [log] [blame]
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]1/*
Graeme Russdbf71152011-04-13 19:43:26 +1000[diff] [blame]2 * (C) Copyright 2008-2011
3 * Graeme Russ, <graeme.russ@gmail.com>
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]4 *
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]5 * (C) Copyright 2002
Albert ARIBAUDfa82f872011-08-04 18:45:45 +0200[diff] [blame]6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]7 *
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]8 * Portions of this file are derived from the Linux kernel source
9 * Copyright (C) 1991, 1992 Linus Torvalds
10 *
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#include <common.h>
Stefan Reinauer095593c2012-12-02 04:49:50 +0000[diff] [blame]31#include <asm/cache.h>
32#include <asm/control_regs.h>
Graeme Russ9933d602008-12-07 10:29:01 +1100[diff] [blame]33#include <asm/interrupt.h>
Graeme Russca56a4c2011-02-12 15:11:28 +1100[diff] [blame]34#include <asm/io.h>
Graeme Russ0c24c9c2011-02-12 15:11:32 +1100[diff] [blame]35#include <asm/processor-flags.h>
Graeme Russ717979f2011-11-08 02:33:13 +0000[diff] [blame]36#include <linux/compiler.h>
Vadim Bendebury7c710342012-12-03 13:59:20 +0000[diff] [blame]37#include <asm/msr.h>
38#include <asm/u-boot-x86.h>
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]39
Simon Glass7282d832013-04-17 16:13:33 +0000[diff] [blame^]40DECLARE_GLOBAL_DATA_PTR;
41
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]42#define DECLARE_INTERRUPT(x) \
43 ".globl irq_"#x"\n" \
Graeme Russ0fc1b492009-11-24 20:04:19 +1100[diff] [blame]44 ".hidden irq_"#x"\n" \
45 ".type irq_"#x", @function\n" \
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]46 "irq_"#x":\n" \
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]47 "pushl $"#x"\n" \
48 "jmp irq_common_entry\n"
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]49
Graeme Russ7228efa2010-10-07 20:03:23 +1100[diff] [blame]50void dump_regs(struct irq_regs *regs)
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]51{
52 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
53 unsigned long d0, d1, d2, d3, d6, d7;
Graeme Russca56a4c2011-02-12 15:11:28 +1100[diff] [blame]54 unsigned long sp;
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]55
56 printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
57 (u16)regs->xcs, regs->eip, regs->eflags);
58
59 printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
60 regs->eax, regs->ebx, regs->ecx, regs->edx);
61 printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
62 regs->esi, regs->edi, regs->ebp, regs->esp);
63 printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
Graeme Russ717979f2011-11-08 02:33:13 +0000[diff] [blame]64 (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs,
65 (u16)regs->xgs, (u16)regs->xss);
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]66
67 cr0 = read_cr0();
68 cr2 = read_cr2();
69 cr3 = read_cr3();
70 cr4 = read_cr4();
71
72 printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
73 cr0, cr2, cr3, cr4);
74
75 d0 = get_debugreg(0);
76 d1 = get_debugreg(1);
77 d2 = get_debugreg(2);
78 d3 = get_debugreg(3);
79
80 printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
81 d0, d1, d2, d3);
82
83 d6 = get_debugreg(6);
84 d7 = get_debugreg(7);
85 printf("DR6: %08lx DR7: %08lx\n",
86 d6, d7);
Graeme Russca56a4c2011-02-12 15:11:28 +1100[diff] [blame]87
88 printf("Stack:\n");
89 sp = regs->esp;
90
91 sp += 64;
92
93 while (sp > (regs->esp - 16)) {
94 if (sp == regs->esp)
95 printf("--->");
96 else
97 printf(" ");
98 printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
99 sp -= 4;
100 }
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]101}
102
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]103struct idt_entry {
104 u16 base_low;
105 u16 selector;
106 u8 res;
107 u8 access;
108 u16 base_high;
Graeme Russ717979f2011-11-08 02:33:13 +0000[diff] [blame]109} __packed;
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]110
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]111struct desc_ptr {
112 unsigned short size;
113 unsigned long address;
114 unsigned short segment;
Graeme Russ717979f2011-11-08 02:33:13 +0000[diff] [blame]115} __packed;
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]116
Graeme Russ58c7a672011-12-19 14:26:18 +1100[diff] [blame]117struct idt_entry idt[256] __aligned(16);
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]118
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]119struct desc_ptr idt_ptr;
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]120
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]121static inline void load_idt(const struct desc_ptr *dtr)
122{
Graeme Russ717979f2011-11-08 02:33:13 +0000[diff] [blame]123 asm volatile("cs lidt %0" : : "m" (*dtr));
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]124}
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]125
Graeme Russabf0cd32009-02-24 21:13:40 +1100[diff] [blame]126void set_vector(u8 intnum, void *routine)
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]127{
Graeme Russ1c409bc2009-11-24 20:04:21 +1100[diff] [blame]128 idt[intnum].base_high = (u16)((u32)(routine) >> 16);
129 idt[intnum].base_low = (u16)((u32)(routine) & 0xffff);
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]130}
131
Graeme Russ717979f2011-11-08 02:33:13 +0000[diff] [blame]132/*
133 * Ideally these would be defined static to avoid a checkpatch warning, but
134 * the compiler cannot see them in the inline asm and complains that they
135 * aren't defined
136 */
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]137void irq_0(void);
138void irq_1(void);
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]139
Graeme Russabf0cd32009-02-24 21:13:40 +1100[diff] [blame]140int cpu_init_interrupts(void)
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]141{
142 int i;
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]143
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]144 int irq_entry_size = irq_1 - irq_0;
145 void *irq_entry = (void *)irq_0;
146
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]147 /* Just in case... */
148 disable_interrupts();
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]149
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]150 /* Setup the IDT */
Graeme Russ717979f2011-11-08 02:33:13 +0000[diff] [blame]151 for (i = 0; i < 256; i++) {
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]152 idt[i].access = 0x8e;
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]153 idt[i].res = 0;
154 idt[i].selector = 0x10;
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]155 set_vector(i, irq_entry);
156 irq_entry += irq_entry_size;
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]157 }
158
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]159 idt_ptr.size = 256 * 8;
160 idt_ptr.address = (unsigned long) idt;
161 idt_ptr.segment = 0x18;
162
163 load_idt(&idt_ptr);
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]164
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]165 /* It is now safe to enable interrupts */
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]166 enable_interrupts();
167
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]168 return 0;
169}
170
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]171void __do_irq(int irq)
172{
173 printf("Unhandled IRQ : %d\n", irq);
174}
175void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
176
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]177void enable_interrupts(void)
178{
179 asm("sti\n");
180}
181
182int disable_interrupts(void)
183{
184 long flags;
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]185
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]186 asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]187
Graeme Russ717979f2011-11-08 02:33:13 +0000[diff] [blame]188 return flags & X86_EFLAGS_IF;
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]189}
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]190
191/* IRQ Low-Level Service Routine */
Graeme Russ7228efa2010-10-07 20:03:23 +1100[diff] [blame]192void irq_llsr(struct irq_regs *regs)
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]193{
194 /*
195 * For detailed description of each exception, refer to:
Albert ARIBAUDfa82f872011-08-04 18:45:45 +0200[diff] [blame]196 * Intel® 64 and IA-32 Architectures Software Developer's Manual
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]197 * Volume 1: Basic Architecture
198 * Order Number: 253665-029US, November 2008
199 * Table 6-1. Exceptions and Interrupts
200 */
Graeme Russ7228efa2010-10-07 20:03:23 +1100[diff] [blame]201 switch (regs->irq_id) {
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]202 case 0x00:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]203 printf("Divide Error (Division by zero)\n");
204 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000[diff] [blame]205 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]206 break;
207 case 0x01:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]208 printf("Debug Interrupt (Single step)\n");
209 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]210 break;
211 case 0x02:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]212 printf("NMI Interrupt\n");
213 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]214 break;
215 case 0x03:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]216 printf("Breakpoint\n");
217 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]218 break;
219 case 0x04:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]220 printf("Overflow\n");
221 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000[diff] [blame]222 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]223 break;
224 case 0x05:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]225 printf("BOUND Range Exceeded\n");
226 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000[diff] [blame]227 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]228 break;
229 case 0x06:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]230 printf("Invalid Opcode (UnDefined Opcode)\n");
231 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000[diff] [blame]232 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]233 break;
234 case 0x07:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]235 printf("Device Not Available (No Math Coprocessor)\n");
236 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000[diff] [blame]237 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]238 break;
239 case 0x08:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]240 printf("Double fault\n");
241 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000[diff] [blame]242 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]243 break;
244 case 0x09:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]245 printf("Co-processor segment overrun\n");
246 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000[diff] [blame]247 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]248 break;
249 case 0x0a:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]250 printf("Invalid TSS\n");
251 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]252 break;
253 case 0x0b:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]254 printf("Segment Not Present\n");
255 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000[diff] [blame]256 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]257 break;
258 case 0x0c:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]259 printf("Stack Segment Fault\n");
260 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000[diff] [blame]261 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]262 break;
263 case 0x0d:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]264 printf("General Protection\n");
265 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]266 break;
267 case 0x0e:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]268 printf("Page fault\n");
269 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000[diff] [blame]270 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]271 break;
272 case 0x0f:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]273 printf("Floating-Point Error (Math Fault)\n");
274 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]275 break;
276 case 0x10:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]277 printf("Alignment check\n");
278 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]279 break;
280 case 0x11:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]281 printf("Machine Check\n");
282 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]283 break;
284 case 0x12:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]285 printf("SIMD Floating-Point Exception\n");
286 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]287 break;
288 case 0x13:
289 case 0x14:
290 case 0x15:
291 case 0x16:
292 case 0x17:
293 case 0x18:
294 case 0x19:
295 case 0x1a:
296 case 0x1b:
297 case 0x1c:
298 case 0x1d:
299 case 0x1e:
300 case 0x1f:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]301 printf("Reserved Exception\n");
302 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]303 break;
304
305 default:
306 /* Hardware or User IRQ */
Graeme Russ7228efa2010-10-07 20:03:23 +1100[diff] [blame]307 do_irq(regs->irq_id);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]308 }
309}
310
311/*
312 * OK - This looks really horrible, but it serves a purpose - It helps create
313 * fully relocatable code.
314 * - The call to irq_llsr will be a relative jump
315 * - The IRQ entries will be guaranteed to be in order
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]316 * Interrupt entries are now very small (a push and a jump) but they are
317 * now slower (all registers pushed on stack which provides complete
318 * crash dumps in the low level handlers
Graeme Russ7228efa2010-10-07 20:03:23 +1100[diff] [blame]319 *
320 * Interrupt Entry Point:
321 * - Interrupt has caused eflags, CS and EIP to be pushed
322 * - Interrupt Vector Handler has pushed orig_eax
323 * - pt_regs.esp needs to be adjusted by 40 bytes:
324 * 12 bytes pushed by CPU (EFLAGSF, CS, EIP)
325 * 4 bytes pushed by vector handler (irq_id)
326 * 24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX)
327 * NOTE: Only longs are pushed on/popped off the stack!
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]328 */
329asm(".globl irq_common_entry\n" \
Graeme Russ0fc1b492009-11-24 20:04:19 +1100[diff] [blame]330 ".hidden irq_common_entry\n" \
331 ".type irq_common_entry, @function\n" \
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]332 "irq_common_entry:\n" \
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]333 "cld\n" \
Graeme Russ7228efa2010-10-07 20:03:23 +1100[diff] [blame]334 "pushl %ss\n" \
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]335 "pushl %gs\n" \
336 "pushl %fs\n" \
337 "pushl %es\n" \
338 "pushl %ds\n" \
339 "pushl %eax\n" \
Graeme Russ7228efa2010-10-07 20:03:23 +1100[diff] [blame]340 "movl %esp, %eax\n" \
341 "addl $40, %eax\n" \
342 "pushl %eax\n" \
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]343 "pushl %ebp\n" \
344 "pushl %edi\n" \
345 "pushl %esi\n" \
346 "pushl %edx\n" \
347 "pushl %ecx\n" \
348 "pushl %ebx\n" \
349 "mov %esp, %eax\n" \
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]350 "call irq_llsr\n" \
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]351 "popl %ebx\n" \
352 "popl %ecx\n" \
353 "popl %edx\n" \
354 "popl %esi\n" \
355 "popl %edi\n" \
356 "popl %ebp\n" \
357 "popl %eax\n" \
Graeme Russ7228efa2010-10-07 20:03:23 +1100[diff] [blame]358 "popl %eax\n" \
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]359 "popl %ds\n" \
360 "popl %es\n" \
361 "popl %fs\n" \
362 "popl %gs\n" \
Graeme Russ7228efa2010-10-07 20:03:23 +1100[diff] [blame]363 "popl %ss\n" \
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame]364 "add $4, %esp\n" \
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]365 "iret\n" \
366 DECLARE_INTERRUPT(0) \
367 DECLARE_INTERRUPT(1) \
368 DECLARE_INTERRUPT(2) \
369 DECLARE_INTERRUPT(3) \
370 DECLARE_INTERRUPT(4) \
371 DECLARE_INTERRUPT(5) \
372 DECLARE_INTERRUPT(6) \
373 DECLARE_INTERRUPT(7) \
374 DECLARE_INTERRUPT(8) \
375 DECLARE_INTERRUPT(9) \
376 DECLARE_INTERRUPT(10) \
377 DECLARE_INTERRUPT(11) \
378 DECLARE_INTERRUPT(12) \
379 DECLARE_INTERRUPT(13) \
380 DECLARE_INTERRUPT(14) \
381 DECLARE_INTERRUPT(15) \
382 DECLARE_INTERRUPT(16) \
383 DECLARE_INTERRUPT(17) \
384 DECLARE_INTERRUPT(18) \
385 DECLARE_INTERRUPT(19) \
386 DECLARE_INTERRUPT(20) \
387 DECLARE_INTERRUPT(21) \
388 DECLARE_INTERRUPT(22) \
389 DECLARE_INTERRUPT(23) \
390 DECLARE_INTERRUPT(24) \
391 DECLARE_INTERRUPT(25) \
392 DECLARE_INTERRUPT(26) \
393 DECLARE_INTERRUPT(27) \
394 DECLARE_INTERRUPT(28) \
395 DECLARE_INTERRUPT(29) \
396 DECLARE_INTERRUPT(30) \
397 DECLARE_INTERRUPT(31) \
398 DECLARE_INTERRUPT(32) \
399 DECLARE_INTERRUPT(33) \
400 DECLARE_INTERRUPT(34) \
401 DECLARE_INTERRUPT(35) \
402 DECLARE_INTERRUPT(36) \
403 DECLARE_INTERRUPT(37) \
404 DECLARE_INTERRUPT(38) \
405 DECLARE_INTERRUPT(39) \
406 DECLARE_INTERRUPT(40) \
407 DECLARE_INTERRUPT(41) \
408 DECLARE_INTERRUPT(42) \
409 DECLARE_INTERRUPT(43) \
410 DECLARE_INTERRUPT(44) \
411 DECLARE_INTERRUPT(45) \
412 DECLARE_INTERRUPT(46) \
413 DECLARE_INTERRUPT(47) \
414 DECLARE_INTERRUPT(48) \
415 DECLARE_INTERRUPT(49) \
416 DECLARE_INTERRUPT(50) \
417 DECLARE_INTERRUPT(51) \
418 DECLARE_INTERRUPT(52) \
419 DECLARE_INTERRUPT(53) \
420 DECLARE_INTERRUPT(54) \
421 DECLARE_INTERRUPT(55) \
422 DECLARE_INTERRUPT(56) \
423 DECLARE_INTERRUPT(57) \
424 DECLARE_INTERRUPT(58) \
425 DECLARE_INTERRUPT(59) \
426 DECLARE_INTERRUPT(60) \
427 DECLARE_INTERRUPT(61) \
428 DECLARE_INTERRUPT(62) \
429 DECLARE_INTERRUPT(63) \
430 DECLARE_INTERRUPT(64) \
431 DECLARE_INTERRUPT(65) \
432 DECLARE_INTERRUPT(66) \
433 DECLARE_INTERRUPT(67) \
434 DECLARE_INTERRUPT(68) \
435 DECLARE_INTERRUPT(69) \
436 DECLARE_INTERRUPT(70) \
437 DECLARE_INTERRUPT(71) \
438 DECLARE_INTERRUPT(72) \
439 DECLARE_INTERRUPT(73) \
440 DECLARE_INTERRUPT(74) \
441 DECLARE_INTERRUPT(75) \
442 DECLARE_INTERRUPT(76) \
443 DECLARE_INTERRUPT(77) \
444 DECLARE_INTERRUPT(78) \
445 DECLARE_INTERRUPT(79) \
446 DECLARE_INTERRUPT(80) \
447 DECLARE_INTERRUPT(81) \
448 DECLARE_INTERRUPT(82) \
449 DECLARE_INTERRUPT(83) \
450 DECLARE_INTERRUPT(84) \
451 DECLARE_INTERRUPT(85) \
452 DECLARE_INTERRUPT(86) \
453 DECLARE_INTERRUPT(87) \
454 DECLARE_INTERRUPT(88) \
455 DECLARE_INTERRUPT(89) \
456 DECLARE_INTERRUPT(90) \
457 DECLARE_INTERRUPT(91) \
458 DECLARE_INTERRUPT(92) \
459 DECLARE_INTERRUPT(93) \
460 DECLARE_INTERRUPT(94) \
461 DECLARE_INTERRUPT(95) \
462 DECLARE_INTERRUPT(97) \
463 DECLARE_INTERRUPT(96) \
464 DECLARE_INTERRUPT(98) \
465 DECLARE_INTERRUPT(99) \
466 DECLARE_INTERRUPT(100) \
467 DECLARE_INTERRUPT(101) \
468 DECLARE_INTERRUPT(102) \
469 DECLARE_INTERRUPT(103) \
470 DECLARE_INTERRUPT(104) \
471 DECLARE_INTERRUPT(105) \
472 DECLARE_INTERRUPT(106) \
473 DECLARE_INTERRUPT(107) \
474 DECLARE_INTERRUPT(108) \
475 DECLARE_INTERRUPT(109) \
476 DECLARE_INTERRUPT(110) \
477 DECLARE_INTERRUPT(111) \
478 DECLARE_INTERRUPT(112) \
479 DECLARE_INTERRUPT(113) \
480 DECLARE_INTERRUPT(114) \
481 DECLARE_INTERRUPT(115) \
482 DECLARE_INTERRUPT(116) \
483 DECLARE_INTERRUPT(117) \
484 DECLARE_INTERRUPT(118) \
485 DECLARE_INTERRUPT(119) \
486 DECLARE_INTERRUPT(120) \
487 DECLARE_INTERRUPT(121) \
488 DECLARE_INTERRUPT(122) \
489 DECLARE_INTERRUPT(123) \
490 DECLARE_INTERRUPT(124) \
491 DECLARE_INTERRUPT(125) \
492 DECLARE_INTERRUPT(126) \
493 DECLARE_INTERRUPT(127) \
494 DECLARE_INTERRUPT(128) \
495 DECLARE_INTERRUPT(129) \
496 DECLARE_INTERRUPT(130) \
497 DECLARE_INTERRUPT(131) \
498 DECLARE_INTERRUPT(132) \
499 DECLARE_INTERRUPT(133) \
500 DECLARE_INTERRUPT(134) \
501 DECLARE_INTERRUPT(135) \
502 DECLARE_INTERRUPT(136) \
503 DECLARE_INTERRUPT(137) \
504 DECLARE_INTERRUPT(138) \
505 DECLARE_INTERRUPT(139) \
506 DECLARE_INTERRUPT(140) \
507 DECLARE_INTERRUPT(141) \
508 DECLARE_INTERRUPT(142) \
509 DECLARE_INTERRUPT(143) \
510 DECLARE_INTERRUPT(144) \
511 DECLARE_INTERRUPT(145) \
512 DECLARE_INTERRUPT(146) \
513 DECLARE_INTERRUPT(147) \
514 DECLARE_INTERRUPT(148) \
515 DECLARE_INTERRUPT(149) \
516 DECLARE_INTERRUPT(150) \
517 DECLARE_INTERRUPT(151) \
518 DECLARE_INTERRUPT(152) \
519 DECLARE_INTERRUPT(153) \
520 DECLARE_INTERRUPT(154) \
521 DECLARE_INTERRUPT(155) \
522 DECLARE_INTERRUPT(156) \
523 DECLARE_INTERRUPT(157) \
524 DECLARE_INTERRUPT(158) \
525 DECLARE_INTERRUPT(159) \
526 DECLARE_INTERRUPT(160) \
527 DECLARE_INTERRUPT(161) \
528 DECLARE_INTERRUPT(162) \
529 DECLARE_INTERRUPT(163) \
530 DECLARE_INTERRUPT(164) \
531 DECLARE_INTERRUPT(165) \
532 DECLARE_INTERRUPT(166) \
533 DECLARE_INTERRUPT(167) \
534 DECLARE_INTERRUPT(168) \
535 DECLARE_INTERRUPT(169) \
536 DECLARE_INTERRUPT(170) \
537 DECLARE_INTERRUPT(171) \
538 DECLARE_INTERRUPT(172) \
539 DECLARE_INTERRUPT(173) \
540 DECLARE_INTERRUPT(174) \
541 DECLARE_INTERRUPT(175) \
542 DECLARE_INTERRUPT(176) \
543 DECLARE_INTERRUPT(177) \
544 DECLARE_INTERRUPT(178) \
545 DECLARE_INTERRUPT(179) \
546 DECLARE_INTERRUPT(180) \
547 DECLARE_INTERRUPT(181) \
548 DECLARE_INTERRUPT(182) \
549 DECLARE_INTERRUPT(183) \
550 DECLARE_INTERRUPT(184) \
551 DECLARE_INTERRUPT(185) \
552 DECLARE_INTERRUPT(186) \
553 DECLARE_INTERRUPT(187) \
554 DECLARE_INTERRUPT(188) \
555 DECLARE_INTERRUPT(189) \
556 DECLARE_INTERRUPT(190) \
557 DECLARE_INTERRUPT(191) \
558 DECLARE_INTERRUPT(192) \
559 DECLARE_INTERRUPT(193) \
560 DECLARE_INTERRUPT(194) \
561 DECLARE_INTERRUPT(195) \
562 DECLARE_INTERRUPT(196) \
563 DECLARE_INTERRUPT(197) \
564 DECLARE_INTERRUPT(198) \
565 DECLARE_INTERRUPT(199) \
566 DECLARE_INTERRUPT(200) \
567 DECLARE_INTERRUPT(201) \
568 DECLARE_INTERRUPT(202) \
569 DECLARE_INTERRUPT(203) \
570 DECLARE_INTERRUPT(204) \
571 DECLARE_INTERRUPT(205) \
572 DECLARE_INTERRUPT(206) \
573 DECLARE_INTERRUPT(207) \
574 DECLARE_INTERRUPT(208) \
575 DECLARE_INTERRUPT(209) \
576 DECLARE_INTERRUPT(210) \
577 DECLARE_INTERRUPT(211) \
578 DECLARE_INTERRUPT(212) \
579 DECLARE_INTERRUPT(213) \
580 DECLARE_INTERRUPT(214) \
581 DECLARE_INTERRUPT(215) \
582 DECLARE_INTERRUPT(216) \
583 DECLARE_INTERRUPT(217) \
584 DECLARE_INTERRUPT(218) \
585 DECLARE_INTERRUPT(219) \
586 DECLARE_INTERRUPT(220) \
587 DECLARE_INTERRUPT(221) \
588 DECLARE_INTERRUPT(222) \
589 DECLARE_INTERRUPT(223) \
590 DECLARE_INTERRUPT(224) \
591 DECLARE_INTERRUPT(225) \
592 DECLARE_INTERRUPT(226) \
593 DECLARE_INTERRUPT(227) \
594 DECLARE_INTERRUPT(228) \
595 DECLARE_INTERRUPT(229) \
596 DECLARE_INTERRUPT(230) \
597 DECLARE_INTERRUPT(231) \
598 DECLARE_INTERRUPT(232) \
599 DECLARE_INTERRUPT(233) \
600 DECLARE_INTERRUPT(234) \
601 DECLARE_INTERRUPT(235) \
602 DECLARE_INTERRUPT(236) \
603 DECLARE_INTERRUPT(237) \
604 DECLARE_INTERRUPT(238) \
605 DECLARE_INTERRUPT(239) \
606 DECLARE_INTERRUPT(240) \
607 DECLARE_INTERRUPT(241) \
608 DECLARE_INTERRUPT(242) \
609 DECLARE_INTERRUPT(243) \
610 DECLARE_INTERRUPT(244) \
611 DECLARE_INTERRUPT(245) \
612 DECLARE_INTERRUPT(246) \
613 DECLARE_INTERRUPT(247) \
614 DECLARE_INTERRUPT(248) \
615 DECLARE_INTERRUPT(249) \
616 DECLARE_INTERRUPT(250) \
617 DECLARE_INTERRUPT(251) \
618 DECLARE_INTERRUPT(252) \
619 DECLARE_INTERRUPT(253) \
620 DECLARE_INTERRUPT(254) \
621 DECLARE_INTERRUPT(255));
Vadim Bendebury7c710342012-12-03 13:59:20 +0000[diff] [blame]622
623#if defined(CONFIG_INTEL_CORE_ARCH)
624/*
625 * Get the number of CPU time counter ticks since it was read first time after
626 * restart. This yields a free running counter guaranteed to take almost 6
627 * years to wrap around even at 100GHz clock rate.
628 */
629u64 get_ticks(void)
630{
Vadim Bendebury7c710342012-12-03 13:59:20 +0000[diff] [blame]631 u64 now_tick = rdtsc();
632
Simon Glassbc2df1a2013-02-28 19:26:12 +0000[diff] [blame]633 if (!gd->arch.tsc_base)
634 gd->arch.tsc_base = now_tick;
Vadim Bendebury7c710342012-12-03 13:59:20 +0000[diff] [blame]635
Simon Glassbc2df1a2013-02-28 19:26:12 +0000[diff] [blame]636 return now_tick - gd->arch.tsc_base;
Vadim Bendebury7c710342012-12-03 13:59:20 +0000[diff] [blame]637}
638
639#define PLATFORM_INFO_MSR 0xce
640
641unsigned long get_tbclk(void)
642{
643 u32 ratio;
644 u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
645
646 ratio = (platform_info >> 8) & 0xff;
647 return 100 * 1000 * 1000 * ratio; /* 100MHz times Max Non Turbo ratio */
648}
649#endif