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wdenk43d96162003-03-06 00:02:04 +00001/*
2 * (C) Copyright 2000, 2001, 2002
3 * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
4 *
5 * Configuration for the Auerswald Innokom CPU board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * include/configs/innokom.h - configuration options, board specific
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
wdenk43d96162003-03-06 00:02:04 +000033/*
wdenk43d96162003-03-06 00:02:04 +000034 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
38#define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */
39
40#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
41 /* for timer/console/ethernet */
42/*
43 * Hardware drivers
44 */
45
46/*
47 * select serial console configuration
48 */
49#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
50
51/* allow to overwrite serial and ethaddr */
52#define CONFIG_ENV_OVERWRITE
53
54#define CONFIG_BAUDRATE 19200
wdenk06d01db2003-03-14 20:47:52 +000055#define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */
wdenk43d96162003-03-06 00:02:04 +000056
wdenk993cad92003-06-26 22:04:09 +000057#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_I2C|CFG_CMD_DHCP|CFG_CMD_CACHE)
wdenk3e386912003-04-05 00:53:31 +000058/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */
wdenk43d96162003-03-06 00:02:04 +000059/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
60#include <cmd_confdefs.h>
61
62#define CONFIG_BOOTDELAY 3
63/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
64#define CONFIG_BOOTARGS "console=ttyS0,19200"
65#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
66#define CONFIG_NETMASK 255.255.255.0
67#define CONFIG_IPADDR 192.168.1.56
68#define CONFIG_SERVERIP 192.168.1.2
69#define CONFIG_BOOTCOMMAND "bootm 0x40000"
70#define CONFIG_SHOW_BOOT_PROGRESS
71
72#define CONFIG_CMDLINE_TAG 1
73
wdenk43d96162003-03-06 00:02:04 +000074/*
75 * Miscellaneous configurable options
76 */
77
78/*
wdenkf6e20fc2004-02-08 19:38:38 +000079 * Size of malloc() pool
wdenk43d96162003-03-06 00:02:04 +000080 */
wdenk06d01db2003-03-14 20:47:52 +000081#define CFG_MALLOC_LEN (256*1024)
wdenka8c7c702003-12-06 19:49:23 +000082#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenk43d96162003-03-06 00:02:04 +000083
84#define CFG_LONGHELP /* undef to save memory */
85#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
wdenk06d01db2003-03-14 20:47:52 +000086#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenk43d96162003-03-06 00:02:04 +000087#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
88#define CFG_MAXARGS 16 /* max number of command args */
89#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
90
91#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
92#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
93
94#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
95
wdenk06d01db2003-03-14 20:47:52 +000096#define CFG_LOAD_ADDR 0xa3000000 /* load kernel to this address */
wdenk43d96162003-03-06 00:02:04 +000097
98#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
99 /* RS: the oscillator is actually 3680130?? */
100
101#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
102 /* 0101000001 */
103 /* ^^^^^ Memory Speed 99.53 MHz */
104 /* ^^ Run Mode Speed = 2x Mem Speed */
105 /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
106
107#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
108
wdenk8bde7f72003-06-27 21:31:46 +0000109 /* valid baudrates */
wdenk43d96162003-03-06 00:02:04 +0000110#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
111
112/*
113 * I2C bus
114 */
wdenk06d01db2003-03-14 20:47:52 +0000115#define CONFIG_HARD_I2C 1
116#define CFG_I2C_SPEED 50000
117#define CFG_I2C_SLAVE 0xfe
wdenk43d96162003-03-06 00:02:04 +0000118
119#define CFG_ENV_IS_IN_EEPROM 1
120
121#define CFG_ENV_OFFSET 0x00 /* environment starts here */
122#define CFG_ENV_SIZE 1024 /* 1 KiB */
123#define CFG_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */
124#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
wdenk06d01db2003-03-14 20:47:52 +0000125#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */
wdenk43d96162003-03-06 00:02:04 +0000126#define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of address */
127#define CFG_EEPROM_SIZE 4096 /* size in bytes */
wdenk06d01db2003-03-14 20:47:52 +0000128#define CFG_I2C_INIT_BOARD 1 /* board has it's own init */
129
130/*
131 * SMSC91C111 Network Card
132 */
133#define CONFIG_DRIVER_SMC91111 1
134#define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */
135#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
136#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
wdenkf39748a2004-06-09 13:37:52 +0000137#define CONFIG_SMC_AUTONEG_TIMEOUT 10 /* timeout 10 seconds */
wdenk06d01db2003-03-14 20:47:52 +0000138#undef CONFIG_SHOW_ACTIVITY
139#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
wdenk43d96162003-03-06 00:02:04 +0000140
141/*
142 * Stack sizes
143 *
144 * The stack sizes are set up in start.S using the settings below
145 */
146#define CONFIG_STACKSIZE (128*1024) /* regular stack */
147#ifdef CONFIG_USE_IRQ
148#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
149#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
150#endif
151
152/*
153 * Physical Memory Map
154 */
155#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
156#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
157#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
158
159#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
160#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
161
162#define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */
163#define CFG_DRAM_SIZE 0x04000000
164
165#define CFG_FLASH_BASE PHYS_FLASH_1
166
wdenk06d01db2003-03-14 20:47:52 +0000167/*
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200168 * JFFS2 partitions
169 *
wdenk06d01db2003-03-14 20:47:52 +0000170 */
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200171/* development flash */
172#define CONFIG_MTD_INNOKOM_16MB 1
173#undef CONFIG_MTD_INNOKOM_64MB
wdenk06d01db2003-03-14 20:47:52 +0000174
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200175/* production flash */
176/*
177#define CONFIG_MTD_INNOKOM_64MB 1
178#undef CONFIG_MTD_INNOKOM_16MB
179*/
180
181/* No command line, one static partition, whole device */
182#undef CONFIG_JFFS2_CMDLINE
183#define CONFIG_JFFS2_DEV "nor0"
184#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
185#define CONFIG_JFFS2_PART_OFFSET 0x00000000
186
187/* mtdparts command line support */
188/* Note: fake mtd_id used, no linux mtd map file */
189/*
190#define CONFIG_JFFS2_CMDLINE
191#define MTDIDS_DEFAULT "nor0=innokom-0"
192*/
193
194/* development flash */
195/*
196#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)"
197*/
198
199/* production flash */
200/*
201#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)"
202*/
wdenk06d01db2003-03-14 20:47:52 +0000203
204/*
wdenk3e386912003-04-05 00:53:31 +0000205 * GPIO settings
wdenk06d01db2003-03-14 20:47:52 +0000206 *
207 * GP15 == nCS1 is 1
wdenk43d96162003-03-06 00:02:04 +0000208 * GP24 == SFRM is 1
209 * GP25 == TXD is 1
210 * GP33 == nCS5 is 1
211 * GP39 == FFTXD is 1
212 * GP41 == RTS is 1
213 * GP47 == TXD is 1
214 * GP49 == nPWE is 1
215 * GP62 == LED_B is 1
216 * GP63 == TDM_OE is 1
217 * GP78 == nCS2 is 1
218 * GP79 == nCS3 is 1
219 * GP80 == nCS4 is 1
220 */
221#define CFG_GPSR0_VAL 0x03008000
222#define CFG_GPSR1_VAL 0xC0028282
223#define CFG_GPSR2_VAL 0x0001C000
224
225/* GP02 == DON_RST is 0
226 * GP23 == SCLK is 0
227 * GP45 == USB_ACT is 0
228 * GP60 == PLLEN is 0
229 * GP61 == LED_A is 0
230 * GP73 == SWUPD_LED is 0
231 */
232#define CFG_GPCR0_VAL 0x00800004
233#define CFG_GPCR1_VAL 0x30002000
234#define CFG_GPCR2_VAL 0x00000100
235
236/* GP00 == DON_READY is input
237 * GP01 == DON_OK is input
238 * GP02 == DON_RST is output
239 * GP03 == RESET_IND is input
240 * GP07 == RES11 is input
241 * GP09 == RES12 is input
242 * GP11 == SWUPDATE is input
243 * GP14 == nPOWEROK is input
244 * GP15 == nCS1 is output
245 * GP17 == RES22 is input
246 * GP18 == RDY is input
247 * GP23 == SCLK is output
248 * GP24 == SFRM is output
249 * GP25 == TXD is output
250 * GP26 == RXD is input
251 * GP32 == RES21 is input
252 * GP33 == nCS5 is output
253 * GP34 == FFRXD is input
254 * GP35 == CTS is input
255 * GP39 == FFTXD is output
256 * GP41 == RTS is output
257 * GP42 == USB_OK is input
258 * GP45 == USB_ACT is output
259 * GP46 == RXD is input
260 * GP47 == TXD is output
261 * GP49 == nPWE is output
262 * GP58 == nCPUBUSINT is input
263 * GP59 == LANINT is input
264 * GP60 == PLLEN is output
265 * GP61 == LED_A is output
266 * GP62 == LED_B is output
267 * GP63 == TDM_OE is output
268 * GP64 == nDSPINT is input
269 * GP65 == STRAP0 is input
270 * GP67 == STRAP1 is input
271 * GP69 == STRAP2 is input
272 * GP70 == STRAP3 is input
273 * GP71 == STRAP4 is input
274 * GP73 == SWUPD_LED is output
275 * GP78 == nCS2 is output
276 * GP79 == nCS3 is output
277 * GP80 == nCS4 is output
278 */
279#define CFG_GPDR0_VAL 0x03808004
280#define CFG_GPDR1_VAL 0xF002A282
281#define CFG_GPDR2_VAL 0x0001C200
282
283/* GP15 == nCS1 is AF10
284 * GP18 == RDY is AF01
285 * GP23 == SCLK is AF10
286 * GP24 == SFRM is AF10
287 * GP25 == TXD is AF10
288 * GP26 == RXD is AF01
289 * GP33 == nCS5 is AF10
290 * GP34 == FFRXD is AF01
291 * GP35 == CTS is AF01
292 * GP39 == FFTXD is AF10
293 * GP41 == RTS is AF10
294 * GP46 == RXD is AF10
295 * GP47 == TXD is AF01
296 * GP49 == nPWE is AF10
297 * GP78 == nCS2 is AF10
298 * GP79 == nCS3 is AF10
299 * GP80 == nCS4 is AF10
300 */
301#define CFG_GAFR0_L_VAL 0x80000000
302#define CFG_GAFR0_U_VAL 0x001A8010
303#define CFG_GAFR1_L_VAL 0x60088058
304#define CFG_GAFR1_U_VAL 0x00000008
305#define CFG_GAFR2_L_VAL 0xA0000000
306#define CFG_GAFR2_U_VAL 0x00000002
307
wdenk06d01db2003-03-14 20:47:52 +0000308
wdenk43d96162003-03-06 00:02:04 +0000309/* FIXME: set GPIO_RER/FER */
310
311/* RDH = 1
312 * PH = 1
313 * VFS = 1
314 * BFS = 1
315 * SSS = 1
316 */
317#define CFG_PSSR_VAL 0x37
318
319/*
320 * Memory settings
wdenk06d01db2003-03-14 20:47:52 +0000321 *
322 * This is the configuration for nCS0/1 -> flash banks
wdenk43d96162003-03-06 00:02:04 +0000323 * configuration for nCS1:
324 * [31] 0 - Slower Device
325 * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
326 * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
327 * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
328 * [19] 1 - 16 Bit bus width
329 * [18:16] 000 - nonburst RAM or FLASH
330 * configuration for nCS0:
331 * [15] 0 - Slower Device
332 * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
333 * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
334 * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
335 * [03] 1 - 16 Bit bus width
336 * [02:00] 000 - nonburst RAM or FLASH
337 */
338#define CFG_MSC0_VAL 0x25b825b8 /* flash banks */
339
340/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
341 * configuration for nCS3: DSP
342 * [31] 0 - Slower Device
343 * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
344 * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
345 * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
346 * [19] 1 - 16 Bit bus width
347 * [18:16] 100 - variable latency I/O
348 * configuration for nCS2: TDM-Switch
349 * [15] 0 - Slower Device
350 * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
351 * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
352 * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
353 * [03] 1 - 16 Bit bus width
354 * [02:00] 100 - variable latency I/O
355 */
wdenk06d01db2003-03-14 20:47:52 +0000356#define CFG_MSC1_VAL 0x123C593C /* TDM switch, DSP */
wdenk43d96162003-03-06 00:02:04 +0000357
358/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
359 *
360 * configuration for nCS5: LAN Controller
361 * [31] 0 - Slower Device
362 * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
363 * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
364 * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
365 * [19] 1 - 16 Bit bus width
366 * [18:16] 100 - variable latency I/O
367 * configuration for nCS4: ExtBus
368 * [15] 0 - Slower Device
369 * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
370 * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
371 * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
372 * [03] 1 - 16 Bit bus width
373 * [02:00] 100 - variable latency I/O
374 */
wdenk06d01db2003-03-14 20:47:52 +0000375#define CFG_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */
wdenk43d96162003-03-06 00:02:04 +0000376
377/* MDCNFG: SDRAM Configuration Register
378 *
379 * [31:29] 000 - reserved
380 * [28] 0 - no SA1111 compatiblity mode
381 * [27] 0 - latch return data with return clock
382 * [26] 0 - alternate addressing for pair 2/3
383 * [25:24] 00 - timings
384 * [23] 0 - internal banks in lower partition 2/3 (not used)
385 * [22:21] 00 - row address bits for partition 2/3 (not used)
386 * [20:19] 00 - column address bits for partition 2/3 (not used)
387 * [18] 0 - SDRAM partition 2/3 width is 32 bit
388 * [17] 0 - SDRAM partition 3 disabled
389 * [16] 0 - SDRAM partition 2 disabled
390 * [15:13] 000 - reserved
391 * [12] 1 - SA1111 compatiblity mode
392 * [11] 1 - latch return data with return clock
393 * [10] 0 - no alternate addressing for pair 0/1
wdenk06d01db2003-03-14 20:47:52 +0000394 * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
wdenk43d96162003-03-06 00:02:04 +0000395 * [7] 1 - 4 internal banks in lower partition pair
396 * [06:05] 10 - 13 row address bits for partition 0/1
397 * [04:03] 01 - 9 column address bits for partition 0/1
398 * [02] 0 - SDRAM partition 0/1 width is 32 bit
399 * [01] 0 - disable SDRAM partition 1
400 * [00] 1 - enable SDRAM partition 0
wdenk43d96162003-03-06 00:02:04 +0000401 */
wdenk06d01db2003-03-14 20:47:52 +0000402/* use the configuration above but disable partition 0 */
wdenk43d96162003-03-06 00:02:04 +0000403#define CFG_MDCNFG_VAL 0x000019c8
404
405/* MDREFR: SDRAM Refresh Control Register
406 *
407 * [32:26] 0 - reserved
408 * [25] 0 - K2FREE: not free running
409 * [24] 0 - K1FREE: not free running
wdenk3e386912003-04-05 00:53:31 +0000410 * [23] 1 - K0FREE: not free running
wdenk43d96162003-03-06 00:02:04 +0000411 * [22] 0 - SLFRSH: self refresh disabled
412 * [21] 0 - reserved
413 * [20] 0 - APD: no auto power down
414 * [19] 0 - K2DB2: SDCLK2 is MemClk
415 * [18] 0 - K2RUN: disable SDCLK2
416 * [17] 0 - K1DB2: SDCLK1 is MemClk
417 * [16] 1 - K1RUN: enable SDCLK1
418 * [15] 1 - E1PIN: SDRAM clock enable
419 * [14] 1 - K0DB2: SDCLK0 is MemClk
wdenk3e386912003-04-05 00:53:31 +0000420 * [13] 0 - K0RUN: disable SDCLK0
wdenk43d96162003-03-06 00:02:04 +0000421 * [12] 1 - E0PIN: disable SDCKE0
422 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
423 */
wdenk3e386912003-04-05 00:53:31 +0000424#define CFG_MDREFR_VAL 0x0081D018
wdenk43d96162003-03-06 00:02:04 +0000425
426/* MDMRS: Mode Register Set Configuration Register
427 *
428 * [31] 0 - reserved
429 * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
430 * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
431 * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
432 * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
433 * [15] 0 - reserved
434 * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
435 * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
436 * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
437 * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
438 */
439#define CFG_MDMRS_VAL 0x00020022
440
441/*
442 * PCMCIA and CF Interfaces
443 */
444#define CFG_MECR_VAL 0x00000000
445#define CFG_MCMEM0_VAL 0x00000000
446#define CFG_MCMEM1_VAL 0x00000000
447#define CFG_MCATT0_VAL 0x00000000
448#define CFG_MCATT1_VAL 0x00000000
449#define CFG_MCIO0_VAL 0x00000000
450#define CFG_MCIO1_VAL 0x00000000
451
452/*
453#define CSB226_USER_LED0 0x00000008
454#define CSB226_USER_LED1 0x00000010
455#define CSB226_USER_LED2 0x00000020
456*/
457
458/*
459 * FLASH and environment organization
460 */
461#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
462#define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
463
464/* timeout values are in ticks */
465#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
466#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
467
wdenk43d96162003-03-06 00:02:04 +0000468#endif /* __CONFIG_H */