blob: a3ce3b582c7c8ea695d9023e358b58be27cc4142 [file] [log] [blame]
Rodolfo Giometti822af352007-04-03 14:27:18 +02001/*
2 * ISP116x register declarations and HCD data structures
3 *
4 * Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it>
5 * Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it>
6 * Copyright (C) 2005 Olav Kongas <ok@artecdesign.ee>
7 * Portions:
8 * Copyright (C) 2004 Lothar Wassmann
9 * Copyright (C) 2004 Psion Teklogix
10 * Copyright (C) 2004 David Brownell
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifdef DEBUG
29#define DBG(fmt, args...) \
30 printf("isp116x: %s: " fmt "\n" , __FUNCTION__ , ## args)
31#else
32#define DBG(fmt, args...) do {} while (0)
33#endif
34
35#ifdef VERBOSE
36# define VDBG DBG
37#else
38# define VDBG(fmt, args...) do {} while (0)
39#endif
40
41#define ERR(fmt, args...) \
42 printf("isp116x: %s: " fmt "\n" , __FUNCTION__ , ## args)
43#define WARN(fmt, args...) \
44 printf("isp116x: %s: " fmt "\n" , __FUNCTION__ , ## args)
45#define INFO(fmt, args...) \
46 printf("isp116x: " fmt "\n" , ## args)
47
48/* ------------------------------------------------------------------------- */
49
50/* us of 1ms frame */
51#define MAX_LOAD_LIMIT 850
52
53/* Full speed: max # of bytes to transfer for a single urb
54 at a time must be < 1024 && must be multiple of 64.
55 832 allows transfering 4kiB within 5 frames. */
56#define MAX_TRANSFER_SIZE_FULLSPEED 832
57
58/* Low speed: there is no reason to schedule in very big
59 chunks; often the requested long transfers are for
60 string descriptors containing short strings. */
61#define MAX_TRANSFER_SIZE_LOWSPEED 64
62
63/* Bytetime (us), a rough indication of how much time it
64 would take to transfer a byte of useful data over USB */
65#define BYTE_TIME_FULLSPEED 1
66#define BYTE_TIME_LOWSPEED 20
67
68/* Buffer sizes */
69#define ISP116x_BUF_SIZE 4096
70#define ISP116x_ITL_BUFSIZE 0
71#define ISP116x_ATL_BUFSIZE ((ISP116x_BUF_SIZE) - 2*(ISP116x_ITL_BUFSIZE))
72
73#define ISP116x_WRITE_OFFSET 0x80
74
75/* --- ISP116x registers/bits ---------------------------------------------- */
76
77#define HCREVISION 0x00
78#define HCCONTROL 0x01
79#define HCCONTROL_HCFS (3 << 6) /* host controller
80 functional state */
81#define HCCONTROL_USB_RESET (0 << 6)
82#define HCCONTROL_USB_RESUME (1 << 6)
83#define HCCONTROL_USB_OPER (2 << 6)
84#define HCCONTROL_USB_SUSPEND (3 << 6)
85#define HCCONTROL_RWC (1 << 9) /* remote wakeup connected */
86#define HCCONTROL_RWE (1 << 10) /* remote wakeup enable */
87#define HCCMDSTAT 0x02
88#define HCCMDSTAT_HCR (1 << 0) /* host controller reset */
89#define HCCMDSTAT_SOC (3 << 16) /* scheduling overrun count */
90#define HCINTSTAT 0x03
91#define HCINT_SO (1 << 0) /* scheduling overrun */
92#define HCINT_WDH (1 << 1) /* writeback of done_head */
93#define HCINT_SF (1 << 2) /* start frame */
94#define HCINT_RD (1 << 3) /* resume detect */
95#define HCINT_UE (1 << 4) /* unrecoverable error */
96#define HCINT_FNO (1 << 5) /* frame number overflow */
97#define HCINT_RHSC (1 << 6) /* root hub status change */
98#define HCINT_OC (1 << 30) /* ownership change */
99#define HCINT_MIE (1 << 31) /* master interrupt enable */
100#define HCINTENB 0x04
101#define HCINTDIS 0x05
102#define HCFMINTVL 0x0d
103#define HCFMREM 0x0e
104#define HCFMNUM 0x0f
105#define HCLSTHRESH 0x11
106#define HCRHDESCA 0x12
107#define RH_A_NDP (0x3 << 0) /* # downstream ports */
108#define RH_A_PSM (1 << 8) /* power switching mode */
109#define RH_A_NPS (1 << 9) /* no power switching */
110#define RH_A_DT (1 << 10) /* device type (mbz) */
111#define RH_A_OCPM (1 << 11) /* overcurrent protection
112 mode */
113#define RH_A_NOCP (1 << 12) /* no overcurrent protection */
114#define RH_A_POTPGT (0xff << 24) /* power on -> power good
115 time */
116#define HCRHDESCB 0x13
117#define RH_B_DR (0xffff << 0) /* device removable flags */
118#define RH_B_PPCM (0xffff << 16) /* port power control mask */
119#define HCRHSTATUS 0x14
120#define RH_HS_LPS (1 << 0) /* local power status */
121#define RH_HS_OCI (1 << 1) /* over current indicator */
122#define RH_HS_DRWE (1 << 15) /* device remote wakeup
123 enable */
124#define RH_HS_LPSC (1 << 16) /* local power status change */
125#define RH_HS_OCIC (1 << 17) /* over current indicator
126 change */
127#define RH_HS_CRWE (1 << 31) /* clear remote wakeup
128 enable */
129#define HCRHPORT1 0x15
130#define RH_PS_CCS (1 << 0) /* current connect status */
131#define RH_PS_PES (1 << 1) /* port enable status */
132#define RH_PS_PSS (1 << 2) /* port suspend status */
133#define RH_PS_POCI (1 << 3) /* port over current
134 indicator */
135#define RH_PS_PRS (1 << 4) /* port reset status */
136#define RH_PS_PPS (1 << 8) /* port power status */
137#define RH_PS_LSDA (1 << 9) /* low speed device attached */
138#define RH_PS_CSC (1 << 16) /* connect status change */
139#define RH_PS_PESC (1 << 17) /* port enable status change */
140#define RH_PS_PSSC (1 << 18) /* port suspend status
141 change */
142#define RH_PS_OCIC (1 << 19) /* over current indicator
143 change */
144#define RH_PS_PRSC (1 << 20) /* port reset status change */
145#define HCRHPORT_CLRMASK (0x1f << 16)
146#define HCRHPORT2 0x16
147#define HCHWCFG 0x20
148#define HCHWCFG_15KRSEL (1 << 12)
149#define HCHWCFG_CLKNOTSTOP (1 << 11)
150#define HCHWCFG_ANALOG_OC (1 << 10)
151#define HCHWCFG_DACK_MODE (1 << 8)
152#define HCHWCFG_EOT_POL (1 << 7)
153#define HCHWCFG_DACK_POL (1 << 6)
154#define HCHWCFG_DREQ_POL (1 << 5)
155#define HCHWCFG_DBWIDTH_MASK (0x03 << 3)
156#define HCHWCFG_DBWIDTH(n) (((n) << 3) & HCHWCFG_DBWIDTH_MASK)
157#define HCHWCFG_INT_POL (1 << 2)
158#define HCHWCFG_INT_TRIGGER (1 << 1)
159#define HCHWCFG_INT_ENABLE (1 << 0)
160#define HCDMACFG 0x21
161#define HCDMACFG_BURST_LEN_MASK (0x03 << 5)
162#define HCDMACFG_BURST_LEN(n) (((n) << 5) & HCDMACFG_BURST_LEN_MASK)
163#define HCDMACFG_BURST_LEN_1 HCDMACFG_BURST_LEN(0)
164#define HCDMACFG_BURST_LEN_4 HCDMACFG_BURST_LEN(1)
165#define HCDMACFG_BURST_LEN_8 HCDMACFG_BURST_LEN(2)
166#define HCDMACFG_DMA_ENABLE (1 << 4)
167#define HCDMACFG_BUF_TYPE_MASK (0x07 << 1)
168#define HCDMACFG_CTR_SEL (1 << 2)
169#define HCDMACFG_ITLATL_SEL (1 << 1)
170#define HCDMACFG_DMA_RW_SELECT (1 << 0)
171#define HCXFERCTR 0x22
172#define HCuPINT 0x24
173#define HCuPINT_SOF (1 << 0)
174#define HCuPINT_ATL (1 << 1)
175#define HCuPINT_AIIEOT (1 << 2)
176#define HCuPINT_OPR (1 << 4)
177#define HCuPINT_SUSP (1 << 5)
178#define HCuPINT_CLKRDY (1 << 6)
179#define HCuPINTENB 0x25
180#define HCCHIPID 0x27
181#define HCCHIPID_MASK 0xff00
182#define HCCHIPID_MAGIC 0x6100
183#define HCSCRATCH 0x28
184#define HCSWRES 0x29
185#define HCSWRES_MAGIC 0x00f6
186#define HCITLBUFLEN 0x2a
187#define HCATLBUFLEN 0x2b
188#define HCBUFSTAT 0x2c
189#define HCBUFSTAT_ITL0_FULL (1 << 0)
190#define HCBUFSTAT_ITL1_FULL (1 << 1)
191#define HCBUFSTAT_ATL_FULL (1 << 2)
192#define HCBUFSTAT_ITL0_DONE (1 << 3)
193#define HCBUFSTAT_ITL1_DONE (1 << 4)
194#define HCBUFSTAT_ATL_DONE (1 << 5)
195#define HCRDITL0LEN 0x2d
196#define HCRDITL1LEN 0x2e
197#define HCITLPORT 0x40
198#define HCATLPORT 0x41
199
200/* PTD accessor macros. */
201#define PTD_GET_COUNT(p) (((p)->count & PTD_COUNT_MSK) >> 0)
202#define PTD_COUNT(v) (((v) << 0) & PTD_COUNT_MSK)
203#define PTD_GET_TOGGLE(p) (((p)->count & PTD_TOGGLE_MSK) >> 10)
204#define PTD_TOGGLE(v) (((v) << 10) & PTD_TOGGLE_MSK)
205#define PTD_GET_ACTIVE(p) (((p)->count & PTD_ACTIVE_MSK) >> 11)
206#define PTD_ACTIVE(v) (((v) << 11) & PTD_ACTIVE_MSK)
207#define PTD_GET_CC(p) (((p)->count & PTD_CC_MSK) >> 12)
208#define PTD_CC(v) (((v) << 12) & PTD_CC_MSK)
209#define PTD_GET_MPS(p) (((p)->mps & PTD_MPS_MSK) >> 0)
210#define PTD_MPS(v) (((v) << 0) & PTD_MPS_MSK)
211#define PTD_GET_SPD(p) (((p)->mps & PTD_SPD_MSK) >> 10)
212#define PTD_SPD(v) (((v) << 10) & PTD_SPD_MSK)
213#define PTD_GET_LAST(p) (((p)->mps & PTD_LAST_MSK) >> 11)
214#define PTD_LAST(v) (((v) << 11) & PTD_LAST_MSK)
215#define PTD_GET_EP(p) (((p)->mps & PTD_EP_MSK) >> 12)
216#define PTD_EP(v) (((v) << 12) & PTD_EP_MSK)
217#define PTD_GET_LEN(p) (((p)->len & PTD_LEN_MSK) >> 0)
218#define PTD_LEN(v) (((v) << 0) & PTD_LEN_MSK)
219#define PTD_GET_DIR(p) (((p)->len & PTD_DIR_MSK) >> 10)
220#define PTD_DIR(v) (((v) << 10) & PTD_DIR_MSK)
221#define PTD_GET_B5_5(p) (((p)->len & PTD_B5_5_MSK) >> 13)
222#define PTD_B5_5(v) (((v) << 13) & PTD_B5_5_MSK)
223#define PTD_GET_FA(p) (((p)->faddr & PTD_FA_MSK) >> 0)
224#define PTD_FA(v) (((v) << 0) & PTD_FA_MSK)
225#define PTD_GET_FMT(p) (((p)->faddr & PTD_FMT_MSK) >> 7)
226#define PTD_FMT(v) (((v) << 7) & PTD_FMT_MSK)
227
228/* Hardware transfer status codes -- CC from ptd->count */
229#define TD_CC_NOERROR 0x00
230#define TD_CC_CRC 0x01
231#define TD_CC_BITSTUFFING 0x02
232#define TD_CC_DATATOGGLEM 0x03
233#define TD_CC_STALL 0x04
234#define TD_DEVNOTRESP 0x05
235#define TD_PIDCHECKFAIL 0x06
236#define TD_UNEXPECTEDPID 0x07
237#define TD_DATAOVERRUN 0x08
238#define TD_DATAUNDERRUN 0x09
239 /* 0x0A, 0x0B reserved for hardware */
240#define TD_BUFFEROVERRUN 0x0C
241#define TD_BUFFERUNDERRUN 0x0D
242 /* 0x0E, 0x0F reserved for HCD */
243#define TD_NOTACCESSED 0x0F
244
245/* ------------------------------------------------------------------------- */
246
247#define LOG2_PERIODIC_SIZE 5 /* arbitrary; this matches OHCI */
248#define PERIODIC_SIZE (1 << LOG2_PERIODIC_SIZE)
249
250/* Philips transfer descriptor */
251struct ptd {
252 u16 count;
253#define PTD_COUNT_MSK (0x3ff << 0)
254#define PTD_TOGGLE_MSK (1 << 10)
255#define PTD_ACTIVE_MSK (1 << 11)
256#define PTD_CC_MSK (0xf << 12)
257 u16 mps;
258#define PTD_MPS_MSK (0x3ff << 0)
259#define PTD_SPD_MSK (1 << 10)
260#define PTD_LAST_MSK (1 << 11)
261#define PTD_EP_MSK (0xf << 12)
262 u16 len;
263#define PTD_LEN_MSK (0x3ff << 0)
264#define PTD_DIR_MSK (3 << 10)
265#define PTD_DIR_SETUP (0)
266#define PTD_DIR_OUT (1)
267#define PTD_DIR_IN (2)
268#define PTD_B5_5_MSK (1 << 13)
269 u16 faddr;
270#define PTD_FA_MSK (0x7f << 0)
271#define PTD_FMT_MSK (1 << 7)
272} __attribute__ ((packed, aligned(2)));
273
274struct isp116x_ep {
275 struct usb_device *udev;
276 struct ptd ptd;
277
278 u8 maxpacket;
279 u8 epnum;
280 u8 nextpid;
281
282 u16 length; /* of current packet */
283 unsigned char *data; /* to databuf */
284
285 u16 error_count;
286};
287
288/* URB struct */
289#define N_URB_TD 48
290#define URB_DEL 1
291typedef struct {
292 struct isp116x_ep *ed;
293 void *transfer_buffer; /* (in) associated data buffer */
294 int actual_length; /* (return) actual transfer length */
295 unsigned long pipe; /* (in) pipe information */
296#if 0
297 int state;
298#endif
299} urb_priv_t;
300
301struct isp116x_platform_data {
302 /* Enable internal resistors on downstream ports */
303 unsigned sel15Kres:1;
304 /* On-chip overcurrent detection */
305 unsigned oc_enable:1;
306 /* Enable wakeup by devices on usb bus (e.g. wakeup
307 by attachment/detachment or by device activity
308 such as moving a mouse). When chosen, this option
309 prevents stopping internal clock, increasing
310 thereby power consumption in suspended state. */
311 unsigned remote_wakeup_enable:1;
312};
313
314struct isp116x {
315 u16 *addr_reg;
316 u16 *data_reg;
317
318 struct isp116x_platform_data *board;
319
320 struct dentry *dentry;
321 unsigned long stat1, stat2, stat4, stat8, stat16;
322
323 /* Status flags */
324 unsigned disabled:1;
325 unsigned sleeping:1;
326
327 /* Root hub registers */
328 u32 rhdesca;
329 u32 rhdescb;
330 u32 rhstatus;
331 u32 rhport[2];
332
333 /* Schedule for the current frame */
334 struct isp116x_ep *atl_active;
335 int atl_buflen;
336 int atl_bufshrt;
337 int atl_last_dir;
338 int atl_finishing;
339};
340
341/* ------------------------------------------------- */
342
343/* Inter-io delay (ns). The chip is picky about access timings; it
344 * expects at least:
345 * 150ns delay between consecutive accesses to DATA_REG,
346 * 300ns delay between access to ADDR_REG and DATA_REG
347 * OE, WE MUST NOT be changed during these intervals
348 */
349#if defined(UDELAY)
350#define isp116x_delay(h,d) udelay(d)
351#else
352#define isp116x_delay(h,d) do {} while (0)
353#endif
354
355static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg)
356{
357 writew(reg & 0xff, isp116x->addr_reg);
358 isp116x_delay(isp116x, UDELAY);
359}
360
361static inline void isp116x_write_data16(struct isp116x *isp116x, u16 val)
362{
363 writew(val, isp116x->data_reg);
364 isp116x_delay(isp116x, UDELAY);
365}
366
367static inline void isp116x_raw_write_data16(struct isp116x *isp116x, u16 val)
368{
369 __raw_writew(val, isp116x->data_reg);
370 isp116x_delay(isp116x, UDELAY);
371}
372
373static inline u16 isp116x_read_data16(struct isp116x *isp116x)
374{
375 u16 val;
376
377 val = readw(isp116x->data_reg);
378 isp116x_delay(isp116x, UDELAY);
379 return val;
380}
381
382static inline u16 isp116x_raw_read_data16(struct isp116x *isp116x)
383{
384 u16 val;
385
386 val = __raw_readw(isp116x->data_reg);
387 isp116x_delay(isp116x, UDELAY);
388 return val;
389}
390
391static inline void isp116x_write_data32(struct isp116x *isp116x, u32 val)
392{
393 writew(val & 0xffff, isp116x->data_reg);
394 isp116x_delay(isp116x, UDELAY);
395 writew(val >> 16, isp116x->data_reg);
396 isp116x_delay(isp116x, UDELAY);
397}
398
399static inline u32 isp116x_read_data32(struct isp116x *isp116x)
400{
401 u32 val;
402
403 val = (u32) readw(isp116x->data_reg);
404 isp116x_delay(isp116x, UDELAY);
405 val |= ((u32) readw(isp116x->data_reg)) << 16;
406 isp116x_delay(isp116x, UDELAY);
407 return val;
408}
409
410/* Let's keep register access functions out of line. Hint:
411 we wait at least 150 ns at every access.
412*/
413static u16 isp116x_read_reg16(struct isp116x *isp116x, unsigned reg)
414{
415 isp116x_write_addr(isp116x, reg);
416 return isp116x_read_data16(isp116x);
417}
418
419static u32 isp116x_read_reg32(struct isp116x *isp116x, unsigned reg)
420{
421 isp116x_write_addr(isp116x, reg);
422 return isp116x_read_data32(isp116x);
423}
424
425static void isp116x_write_reg16(struct isp116x *isp116x, unsigned reg,
426 unsigned val)
427{
428 isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
429 isp116x_write_data16(isp116x, (u16) (val & 0xffff));
430}
431
432static void isp116x_write_reg32(struct isp116x *isp116x, unsigned reg,
433 unsigned val)
434{
435 isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
436 isp116x_write_data32(isp116x, (u32) val);
437}
438
439/* --- USB HUB constants (not OHCI-specific; see hub.h) -------------------- */
440
441/* destination of request */
442#define RH_INTERFACE 0x01
443#define RH_ENDPOINT 0x02
444#define RH_OTHER 0x03
445
446#define RH_CLASS 0x20
447#define RH_VENDOR 0x40
448
449/* Requests: bRequest << 8 | bmRequestType */
450#define RH_GET_STATUS 0x0080
451#define RH_CLEAR_FEATURE 0x0100
452#define RH_SET_FEATURE 0x0300
453#define RH_SET_ADDRESS 0x0500
454#define RH_GET_DESCRIPTOR 0x0680
455#define RH_SET_DESCRIPTOR 0x0700
456#define RH_GET_CONFIGURATION 0x0880
457#define RH_SET_CONFIGURATION 0x0900
458#define RH_GET_STATE 0x0280
459#define RH_GET_INTERFACE 0x0A80
460#define RH_SET_INTERFACE 0x0B00
461#define RH_SYNC_FRAME 0x0C80
462/* Our Vendor Specific Request */
463#define RH_SET_EP 0x2000
464
465/* Hub port features */
466#define RH_PORT_CONNECTION 0x00
467#define RH_PORT_ENABLE 0x01
468#define RH_PORT_SUSPEND 0x02
469#define RH_PORT_OVER_CURRENT 0x03
470#define RH_PORT_RESET 0x04
471#define RH_PORT_POWER 0x08
472#define RH_PORT_LOW_SPEED 0x09
473
474#define RH_C_PORT_CONNECTION 0x10
475#define RH_C_PORT_ENABLE 0x11
476#define RH_C_PORT_SUSPEND 0x12
477#define RH_C_PORT_OVER_CURRENT 0x13
478#define RH_C_PORT_RESET 0x14
479
480/* Hub features */
481#define RH_C_HUB_LOCAL_POWER 0x00
482#define RH_C_HUB_OVER_CURRENT 0x01
483
484#define RH_DEVICE_REMOTE_WAKEUP 0x00
485#define RH_ENDPOINT_STALL 0x01
486
487#define RH_ACK 0x01
488#define RH_REQ_ERR -1
489#define RH_NACK 0x00