blob: bd3107ab23c3cdf715af824181e3be77d23975e6 [file] [log] [blame]
roy zangc6411c02006-11-02 18:55:04 +08001/*
2 * Copyright (c) 2005 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2006
5 * Alex Bounine , Tundra Semiconductor Corp.
roy zang4efe20c2006-12-04 14:46:23 +08006 * Roy Zang , <tie-fei.zang@freescale.com> Freescale Corp.
roy zangc6411c02006-11-02 18:55:04 +08007 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
roy zangee311212006-12-01 11:47:36 +080027/*
roy zangc6411c02006-11-02 18:55:04 +080028 * board specific configuration options for Freescale
29 * MPC7448HPC2 (High-Performance Computing II) (Taiga) board
30 *
roy zangee311212006-12-01 11:47:36 +080031 */
roy zangc6411c02006-11-02 18:55:04 +080032
33#ifndef __CONFIG_H
34#define __CONFIG_H
35
36#undef DEBUG
37
38/* Board Configuration Definitions */
39/* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */
40
41#define CONFIG_MPC7448HPC2
42
43#define CONFIG_74xx
44#define CONFIG_750FX /* this option to enable init of extended BATs */
45#define CONFIG_ALTIVEC /* undef to disable */
46
roy zangee311212006-12-01 11:47:36 +080047#define CFG_BOARD_NAME "MPC7448 HPC II"
48#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II"
roy zangc6411c02006-11-02 18:55:04 +080049
roy zangee311212006-12-01 11:47:36 +080050#define CFG_OCN_CLK 133000000 /* 133 MHz */
51#define CFG_CONFIG_BUS_CLK 133000000
roy zangc6411c02006-11-02 18:55:04 +080052
53#define CFG_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */
54
55#undef CONFIG_ECC /* disable ECC support */
56
57/* Board-specific Initialization Functions to be called */
58#define CFG_BOARD_ASM_INIT
59#define CONFIG_BOARD_EARLY_INIT_F
60#define CONFIG_BOARD_EARLY_INIT_R
61#define CONFIG_MISC_INIT_R
62
roy zangc6411c02006-11-02 18:55:04 +080063#define CONFIG_HAS_ETH1
roy zangc6411c02006-11-02 18:55:04 +080064
65#define CONFIG_ENV_OVERWRITE
66
67/*
68 * High Level Configuration Options
69 * (easy to change)
70 */
71
roy zangee311212006-12-01 11:47:36 +080072#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
roy zangc6411c02006-11-02 18:55:04 +080073
74/*#define CFG_HUSH_PARSER */
75#undef CFG_HUSH_PARSER
76
roy zangee311212006-12-01 11:47:36 +080077#define CFG_PROMPT_HUSH_PS2 "> "
roy zangc6411c02006-11-02 18:55:04 +080078
79/* Pass open firmware flat tree */
80#define CONFIG_OF_FLAT_TREE 1
81#define CONFIG_OF_BOARD_SETUP 1
82
roy zangc6411c02006-11-02 18:55:04 +080083#define OF_CPU "PowerPC,7448@0"
84#define OF_TSI "tsi108@c0000000"
85#define OF_TBCLK (bd->bi_busfreq / 8)
86#define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808"
87
88/*
89 * The following defines let you select what serial you want to use
90 * for your console driver.
91 *
92 * what to do:
roy zangee311212006-12-01 11:47:36 +080093 * If you have hacked a serial cable onto the second DUART channel,
94 * change the CFG_DUART port from 1 to 0 below.
roy zangc6411c02006-11-02 18:55:04 +080095 *
96 */
97
roy zangee311212006-12-01 11:47:36 +080098#define CONFIG_CONS_INDEX 1
roy zangc6411c02006-11-02 18:55:04 +080099#define CFG_NS16550
100#define CFG_NS16550_SERIAL
roy zangee311212006-12-01 11:47:36 +0800101#define CFG_NS16550_REG_SIZE 1
roy zangc6411c02006-11-02 18:55:04 +0800102#define CFG_NS16550_CLK CFG_OCN_CLK * 8
103
roy zangee311212006-12-01 11:47:36 +0800104#define CFG_NS16550_COM1 (CFG_TSI108_CSR_RST_BASE+0x7808)
105#define CFG_NS16550_COM2 (CFG_TSI108_CSR_RST_BASE+0x7C08)
roy zangc6411c02006-11-02 18:55:04 +0800106#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
107
roy zangee311212006-12-01 11:47:36 +0800108#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
roy zangc6411c02006-11-02 18:55:04 +0800109#define CONFIG_ZERO_BOOTDELAY_CHECK
110
111#undef CONFIG_BOOTARGS
roy zangee311212006-12-01 11:47:36 +0800112/* #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\"
113 * to mount root filesystem over NFS;echo" */
roy zangc6411c02006-11-02 18:55:04 +0800114
115#if (CONFIG_BOOTDELAY >= 0)
roy zangee311212006-12-01 11:47:36 +0800116#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\
roy zangc6411c02006-11-02 18:55:04 +0800117 setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
118 ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
119
120#define CONFIG_BOOTARGS "console=ttyS0,115200"
121#endif
122
123#undef CONFIG_EXTRA_ENV_SETTINGS
124
roy zangee311212006-12-01 11:47:36 +0800125#define CONFIG_SERIAL "No. 1"
roy zangc6411c02006-11-02 18:55:04 +0800126
127/* Networking Configuration */
128
roy zangee311212006-12-01 11:47:36 +0800129#define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */
roy zangc6411c02006-11-02 18:55:04 +0800130
131#define CONFIG_TSI108_ETH
roy zangee311212006-12-01 11:47:36 +0800132#define CONFIG_TSI108_ETH_NUM_PORTS 2
roy zangc6411c02006-11-02 18:55:04 +0800133
134#define CONFIG_NET_MULTI
135
roy zangee311212006-12-01 11:47:36 +0800136#define CONFIG_BOOTFILE zImage.initrd.elf
137#define CONFIG_LOADADDR 0x400000
roy zangc6411c02006-11-02 18:55:04 +0800138
roy zangc6411c02006-11-02 18:55:04 +0800139/*-------------------------------------------------------------------------- */
140
roy zangee311212006-12-01 11:47:36 +0800141#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
roy zangc6411c02006-11-02 18:55:04 +0800142#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
143
144#undef CONFIG_WATCHDOG /* watchdog disabled */
145
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500146/*
147 * BOOTP options
148 */
149#define CONFIG_BOOTP_SUBNETMASK
150#define CONFIG_BOOTP_GATEWAY
151#define CONFIG_BOOTP_HOSTNAME
152#define CONFIG_BOOTP_BOOTPATH
153#define CONFIG_BOOTP_BOOTFILESIZE
roy zangc6411c02006-11-02 18:55:04 +0800154
roy zangc6411c02006-11-02 18:55:04 +0800155
Jon Loeliger5dc11a52007-07-04 22:33:01 -0500156/*
157 * Command line configuration.
158 */
159#include <config_cmd_default.h>
160
161#define CONFIG_CMD_ASKENV
162#define CONFIG_CMD_CACHE
163#define CONFIG_CMD_PCI
164#define CONFIG_CMD_I2C
165#define CONFIG_CMD_SDRAM
166#define CONFIG_CMD_EEPROM
167#define CONFIG_CMD_FLASH
168#define CONFIG_CMD_ENV
169#define CONFIG_CMD_BSP
170#define CONFIG_CMD_DHCP
171#define CONFIG_CMD_PING
172#define CONFIG_CMD_DATE
173
roy zangc6411c02006-11-02 18:55:04 +0800174
175/*set date in u-boot*/
176#define CONFIG_RTC_M48T35A
roy zangee311212006-12-01 11:47:36 +0800177#define CFG_NVRAM_BASE_ADDR 0xfc000000
178#define CFG_NVRAM_SIZE 0x8000
roy zangc6411c02006-11-02 18:55:04 +0800179/*
180 * Miscellaneous configurable options
181 */
roy zangee311212006-12-01 11:47:36 +0800182#define CONFIG_VERSION_VARIABLE 1
roy zangc6411c02006-11-02 18:55:04 +0800183#define CONFIG_TSI108_I2C
184
roy zangee311212006-12-01 11:47:36 +0800185#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */
186#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
roy zangc6411c02006-11-02 18:55:04 +0800187
188#define CFG_LONGHELP /* undef to save memory */
189#define CFG_PROMPT "=> " /* Monitor Command Prompt */
190
Jon Loeliger5dc11a52007-07-04 22:33:01 -0500191#if defined(CONFIG_CMD_KGDB)
roy zangee311212006-12-01 11:47:36 +0800192#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
193#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
roy zangc6411c02006-11-02 18:55:04 +0800194#else
roy zangee311212006-12-01 11:47:36 +0800195#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
roy zangc6411c02006-11-02 18:55:04 +0800196#endif
197
roy zangee311212006-12-01 11:47:36 +0800198#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)/* Print Buffer Size */
199#define CFG_MAXARGS 16 /* max number of command args */
200#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
roy zangc6411c02006-11-02 18:55:04 +0800201
roy zangee311212006-12-01 11:47:36 +0800202#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
203#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
roy zangc6411c02006-11-02 18:55:04 +0800204
roy zangee311212006-12-01 11:47:36 +0800205#define CFG_LOAD_ADDR 0x00400000 /* default load address */
roy zangc6411c02006-11-02 18:55:04 +0800206
roy zangee311212006-12-01 11:47:36 +0800207#define CFG_HZ 1000 /* decr freq: 1ms ticks */
roy zangc6411c02006-11-02 18:55:04 +0800208
209/*
210 * Low Level Configuration Settings
211 * (address mappings, register initial values, etc.)
212 * You should know what you are doing if you make changes here.
213 */
214
215/*-----------------------------------------------------------------------
216 * Definitions for initial stack pointer and data area
217 */
218
219/*
220 * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
221 * To an unused memory region. The stack will remain in cache until RAM
222 * is initialized
roy zangee311212006-12-01 11:47:36 +0800223 */
roy zangc6411c02006-11-02 18:55:04 +0800224#undef CFG_INIT_RAM_LOCK
roy zangee311212006-12-01 11:47:36 +0800225#define CFG_INIT_RAM_ADDR 0x07d00000 /* unused memory region */
226#define CFG_INIT_RAM_END 0x4000/* larger space - we have SDRAM initialized */
roy zangc6411c02006-11-02 18:55:04 +0800227
roy zangee311212006-12-01 11:47:36 +0800228#define CFG_GBL_DATA_SIZE 128/* size in bytes reserved for init data */
roy zangc6411c02006-11-02 18:55:04 +0800229#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
230
231/*-----------------------------------------------------------------------
232 * Start addresses for the final memory configuration
233 * (Set up by the startup code)
234 * Please note that CFG_SDRAM_BASE _must_ start at 0
235 */
236
roy zangee311212006-12-01 11:47:36 +0800237#define CFG_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */
238#define CFG_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */
roy zangc6411c02006-11-02 18:55:04 +0800239
roy zangee311212006-12-01 11:47:36 +0800240#define CFG_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */
241#define CFG_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */
roy zangc6411c02006-11-02 18:55:04 +0800242
roy zangee311212006-12-01 11:47:36 +0800243#define CFG_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */
roy zangc6411c02006-11-02 18:55:04 +0800244
roy zangee311212006-12-01 11:47:36 +0800245#define CFG_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */
roy zangc6411c02006-11-02 18:55:04 +0800246
roy zangee311212006-12-01 11:47:36 +0800247#define CFG_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */
roy zangc6411c02006-11-02 18:55:04 +0800248
roy zangee311212006-12-01 11:47:36 +0800249#define CFG_FLASH_BASE 0xff000000 /* Base Address of Flash device */
250#define CFG_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */
roy zangc6411c02006-11-02 18:55:04 +0800251
252#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */
253
roy zangee311212006-12-01 11:47:36 +0800254#define PCI0_IO_BASE_BOOTM 0xfd000000
roy zangc6411c02006-11-02 18:55:04 +0800255
roy zangee311212006-12-01 11:47:36 +0800256#define CFG_RESET_ADDRESS 0x3fffff00
257#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
258#define CFG_MONITOR_BASE TEXT_BASE /* u-boot code base */
259#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
roy zangc6411c02006-11-02 18:55:04 +0800260
261/* Peripheral Device section */
262
roy zangee311212006-12-01 11:47:36 +0800263/*
roy zangc6411c02006-11-02 18:55:04 +0800264 * Resources on the Tsi108
roy zangee311212006-12-01 11:47:36 +0800265 */
roy zangc6411c02006-11-02 18:55:04 +0800266
roy zangee311212006-12-01 11:47:36 +0800267#define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */
268#define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */
roy zangc6411c02006-11-02 18:55:04 +0800269
270#define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */
271
272#undef DISABLE_PBM
273
roy zangee311212006-12-01 11:47:36 +0800274/*
roy zangc6411c02006-11-02 18:55:04 +0800275 * PCI stuff
roy zangee311212006-12-01 11:47:36 +0800276 *
roy zangc6411c02006-11-02 18:55:04 +0800277 */
278
279#define CONFIG_PCI /* include pci support */
280#define CONFIG_TSI108_PCI /* include tsi108 pci support */
281
roy zangee311212006-12-01 11:47:36 +0800282#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
283#define PCI_HOST_FORCE 1 /* configure as pci host */
284#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
roy zangc6411c02006-11-02 18:55:04 +0800285
286#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
287#define CONFIG_PCI_PNP /* do pci plug-and-play */
288
289/* PCI MEMORY MAP section */
290
291/* PCI view of System Memory */
roy zangee311212006-12-01 11:47:36 +0800292#define CFG_PCI_MEMORY_BUS 0x00000000
293#define CFG_PCI_MEMORY_PHYS 0x00000000
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100294#define CFG_PCI_MEMORY_SIZE 0x80000000
roy zangc6411c02006-11-02 18:55:04 +0800295
296/* PCI Memory Space */
roy zangee311212006-12-01 11:47:36 +0800297#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS)
298#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) /* 0xE0000000 */
299#define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */
roy zangc6411c02006-11-02 18:55:04 +0800300
301/* PCI I/O Space */
roy zangee311212006-12-01 11:47:36 +0800302#define CFG_PCI_IO_BUS 0x00000000
303#define CFG_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */
roy zangc6411c02006-11-02 18:55:04 +0800304
roy zangee311212006-12-01 11:47:36 +0800305#define CFG_PCI_IO_SIZE 0x01000000 /* 16MB */
roy zangc6411c02006-11-02 18:55:04 +0800306
307#define _IO_BASE 0x00000000 /* points to PCI I/O space */
308
309/* PCI Config Space mapping */
310#define CFG_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */
311#define CFG_PCI_CFG_SIZE 0x01000000 /* 16MB */
312
roy zangee311212006-12-01 11:47:36 +0800313#define CFG_IBAT0U 0xFE0003FF
314#define CFG_IBAT0L 0xFE000002
roy zangc6411c02006-11-02 18:55:04 +0800315
roy zangee311212006-12-01 11:47:36 +0800316#define CFG_IBAT1U 0x00007FFF
317#define CFG_IBAT1L 0x00000012
roy zangc6411c02006-11-02 18:55:04 +0800318
roy zangee311212006-12-01 11:47:36 +0800319#define CFG_IBAT2U 0x80007FFF
320#define CFG_IBAT2L 0x80000022
roy zangc6411c02006-11-02 18:55:04 +0800321
roy zangee311212006-12-01 11:47:36 +0800322#define CFG_IBAT3U 0x00000000
323#define CFG_IBAT3L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800324
roy zangee311212006-12-01 11:47:36 +0800325#define CFG_IBAT4U 0x00000000
326#define CFG_IBAT4L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800327
roy zangee311212006-12-01 11:47:36 +0800328#define CFG_IBAT5U 0x00000000
329#define CFG_IBAT5L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800330
roy zangee311212006-12-01 11:47:36 +0800331#define CFG_IBAT6U 0x00000000
332#define CFG_IBAT6L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800333
roy zangee311212006-12-01 11:47:36 +0800334#define CFG_IBAT7U 0x00000000
335#define CFG_IBAT7L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800336
roy zangee311212006-12-01 11:47:36 +0800337#define CFG_DBAT0U 0xE0003FFF
338#define CFG_DBAT0L 0xE000002A
roy zangc6411c02006-11-02 18:55:04 +0800339
roy zangee311212006-12-01 11:47:36 +0800340#define CFG_DBAT1U 0x00007FFF
341#define CFG_DBAT1L 0x00000012
roy zangc6411c02006-11-02 18:55:04 +0800342
roy zangee311212006-12-01 11:47:36 +0800343#define CFG_DBAT2U 0x00000000
344#define CFG_DBAT2L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800345
roy zangee311212006-12-01 11:47:36 +0800346#define CFG_DBAT3U 0xC0000003
347#define CFG_DBAT3L 0xC000002A
roy zangc6411c02006-11-02 18:55:04 +0800348
roy zangee311212006-12-01 11:47:36 +0800349#define CFG_DBAT4U 0x00000000
350#define CFG_DBAT4L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800351
roy zangee311212006-12-01 11:47:36 +0800352#define CFG_DBAT5U 0x00000000
353#define CFG_DBAT5L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800354
roy zangee311212006-12-01 11:47:36 +0800355#define CFG_DBAT6U 0x00000000
356#define CFG_DBAT6L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800357
roy zangee311212006-12-01 11:47:36 +0800358#define CFG_DBAT7U 0x00000000
359#define CFG_DBAT7L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800360
361/* I2C addresses for the two DIMM SPD chips */
roy zangee311212006-12-01 11:47:36 +0800362#define DIMM0_I2C_ADDR 0x51
363#define DIMM1_I2C_ADDR 0x52
roy zangc6411c02006-11-02 18:55:04 +0800364
365/*
366 * For booting Linux, the board info and command line data
367 * have to be in the first 8 MB of memory, since this is
368 * the maximum mapped by the Linux kernel during initialization.
369 */
roy zangee311212006-12-01 11:47:36 +0800370#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
roy zangc6411c02006-11-02 18:55:04 +0800371
372/*-----------------------------------------------------------------------
373 * FLASH organization
374 */
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200375#define CFG_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */
roy zangee311212006-12-01 11:47:36 +0800376#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200377#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, /* CFG_FLASH_BASE2 */ }
roy zangc6411c02006-11-02 18:55:04 +0800378
379#define CFG_FLASH_CFI_DRIVER
380#define CFG_FLASH_CFI
roy zangfdef3882007-01-22 13:19:21 +0800381#define CFG_WRITE_SWAPPED_DATA
roy zangc6411c02006-11-02 18:55:04 +0800382
roy zangee311212006-12-01 11:47:36 +0800383#define PHYS_FLASH_SIZE 0x01000000
384#define CFG_MAX_FLASH_SECT (128)
roy zangc6411c02006-11-02 18:55:04 +0800385
386#define CFG_ENV_IS_IN_NVRAM
roy zangee311212006-12-01 11:47:36 +0800387#define CFG_ENV_ADDR 0xFC000000
roy zangc6411c02006-11-02 18:55:04 +0800388
roy zangee311212006-12-01 11:47:36 +0800389#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */
390#define CFG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */
roy zangc6411c02006-11-02 18:55:04 +0800391
392/*-----------------------------------------------------------------------
393 * Cache Configuration
394 */
roy zangee311212006-12-01 11:47:36 +0800395#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
Jon Loeliger5dc11a52007-07-04 22:33:01 -0500396#if defined(CONFIG_CMD_KGDB)
roy zangee311212006-12-01 11:47:36 +0800397#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
roy zangc6411c02006-11-02 18:55:04 +0800398#endif
399
400/*-----------------------------------------------------------------------
401 * L2CR setup -- make sure this is right for your board!
402 * look in include/mpc74xx.h for the defines used here
403 */
404#undef CFG_L2
405
roy zangee311212006-12-01 11:47:36 +0800406#define L2_INIT 0
407#define L2_ENABLE (L2_INIT | L2CR_L2E)
roy zangc6411c02006-11-02 18:55:04 +0800408
409/*
410 * Internal Definitions
411 *
412 * Boot Flags
413 */
roy zangee311212006-12-01 11:47:36 +0800414#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
415#define BOOTFLAG_WARM 0x02 /* Software reboot */
roy zangc6411c02006-11-02 18:55:04 +0800416#define CFG_SERIAL_HANG_IN_EXCEPTION
roy zangee311212006-12-01 11:47:36 +0800417#endif /* __CONFIG_H */