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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Wang Huan550e3dc2014-09-05 13:52:44 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Wang Huan550e3dc2014-09-05 13:52:44 +08004 */
5
6#ifndef __CONFIG_H
7#define __CONFIG_H
8
Hongbo Zhangaeb901f2016-07-21 18:09:38 +08009#define CONFIG_ARMV7_PSCI_1_0
Wang Dongsheng340848b2015-06-04 12:01:09 +080010
Hongbo Zhang32886282016-07-21 18:09:39 +080011#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
12
Gong Qianyu18fb0e32015-10-26 19:47:42 +080013#define CONFIG_SYS_FSL_CLK
Wang Huan550e3dc2014-09-05 13:52:44 +080014
Wang Huan550e3dc2014-09-05 13:52:44 +080015#define CONFIG_SKIP_LOWLEVEL_INIT
Wang Huan550e3dc2014-09-05 13:52:44 +080016
tang yuantian41ba57d2014-12-17 12:58:05 +080017#define CONFIG_DEEP_SLEEP
tang yuantian41ba57d2014-12-17 12:58:05 +080018
Wang Huan550e3dc2014-09-05 13:52:44 +080019/*
20 * Size of malloc() pool
21 */
22#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
23
24#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
25#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
26
Wang Huan550e3dc2014-09-05 13:52:44 +080027#ifndef __ASSEMBLY__
28unsigned long get_board_sys_clk(void);
29unsigned long get_board_ddr_clk(void);
30#endif
31
Alison Wang70097022016-02-02 15:16:23 +080032#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Alison Wangd612f0a2014-12-09 17:38:02 +080033#define CONFIG_SYS_CLK_FREQ 100000000
34#define CONFIG_DDR_CLK_FREQ 100000000
35#define CONFIG_QIXIS_I2C_ACCESS
36#else
Wang Huan550e3dc2014-09-05 13:52:44 +080037#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
38#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
Alison Wangd612f0a2014-12-09 17:38:02 +080039#endif
Wang Huan550e3dc2014-09-05 13:52:44 +080040
Alison Wang86949c22014-12-03 15:00:47 +080041#ifdef CONFIG_RAMBOOT_PBL
42#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
43#endif
44
45#ifdef CONFIG_SD_BOOT
Alison Wang70097022016-02-02 15:16:23 +080046#ifdef CONFIG_SD_BOOT_QSPI
47#define CONFIG_SYS_FSL_PBL_RCW \
48 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
49#else
50#define CONFIG_SYS_FSL_PBL_RCW \
51 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
52#endif
Alison Wang86949c22014-12-03 15:00:47 +080053
54#define CONFIG_SPL_TEXT_BASE 0x10000000
55#define CONFIG_SPL_MAX_SIZE 0x1a000
56#define CONFIG_SPL_STACK 0x1001d000
57#define CONFIG_SPL_PAD_TO 0x1c000
Alison Wang86949c22014-12-03 15:00:47 +080058
tang yuantian41ba57d2014-12-17 12:58:05 +080059#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
60 CONFIG_SYS_MONITOR_LEN)
Alison Wang86949c22014-12-03 15:00:47 +080061#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
62#define CONFIG_SPL_BSS_START_ADDR 0x80100000
63#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
Alison Wang7ee52af2015-10-30 22:45:38 +080064#define CONFIG_SYS_MONITOR_LEN 0xc0000
Alison Wang86949c22014-12-03 15:00:47 +080065#endif
66
Alison Wang8ab967b2014-12-09 17:38:14 +080067#ifdef CONFIG_NAND_BOOT
68#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
Alison Wang8ab967b2014-12-09 17:38:14 +080069
70#define CONFIG_SPL_TEXT_BASE 0x10000000
71#define CONFIG_SPL_MAX_SIZE 0x1a000
72#define CONFIG_SPL_STACK 0x1001d000
73#define CONFIG_SPL_PAD_TO 0x1c000
Alison Wang8ab967b2014-12-09 17:38:14 +080074
75#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
76#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
77#define CONFIG_SYS_NAND_PAGE_SIZE 2048
78#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
79#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
80
81#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
82#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
83#define CONFIG_SPL_BSS_START_ADDR 0x80100000
84#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
85#define CONFIG_SYS_MONITOR_LEN 0x80000
86#endif
87
Wang Huan550e3dc2014-09-05 13:52:44 +080088#define CONFIG_NR_DRAM_BANKS 1
89
90#define CONFIG_DDR_SPD
91#define SPD_EEPROM_ADDRESS 0x51
92#define CONFIG_SYS_SPD_BUS_NUM 0
Wang Huan550e3dc2014-09-05 13:52:44 +080093
94#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
York Sunc7eae7f2014-09-11 13:32:07 -070095#ifndef CONFIG_SYS_FSL_DDR4
York Sunc7eae7f2014-09-11 13:32:07 -070096#define CONFIG_SYS_DDR_RAW_TIMING
97#endif
Wang Huan550e3dc2014-09-05 13:52:44 +080098#define CONFIG_DIMM_SLOTS_PER_CTLR 1
99#define CONFIG_CHIP_SELECTS_PER_CTRL 4
100
101#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
102#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
103
104#define CONFIG_DDR_ECC
105#ifdef CONFIG_DDR_ECC
106#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
107#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
108#endif
109
Alison Wang4c59ab92014-12-09 17:37:49 +0800110#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
111 !defined(CONFIG_QSPI_BOOT)
Zhao Qiang63e75fd2014-09-26 16:25:32 +0800112#define CONFIG_U_QE
Zhao Qiang5aa03dd2017-05-25 09:47:40 +0800113#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiang63e75fd2014-09-26 16:25:32 +0800114#endif
115
Wang Huan550e3dc2014-09-05 13:52:44 +0800116/*
117 * IFC Definitions
118 */
Alison Wang70097022016-02-02 15:16:23 +0800119#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Wang Huan550e3dc2014-09-05 13:52:44 +0800120#define CONFIG_FSL_IFC
121#define CONFIG_SYS_FLASH_BASE 0x60000000
122#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
123
124#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
125#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
126 CSPR_PORT_SIZE_16 | \
127 CSPR_MSEL_NOR | \
128 CSPR_V)
129#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
130#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
131 + 0x8000000) | \
132 CSPR_PORT_SIZE_16 | \
133 CSPR_MSEL_NOR | \
134 CSPR_V)
135#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
136
137#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
138 CSOR_NOR_TRHZ_80)
139#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
140 FTIM0_NOR_TEADC(0x5) | \
141 FTIM0_NOR_TEAHC(0x5))
142#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
143 FTIM1_NOR_TRAD_NOR(0x1a) | \
144 FTIM1_NOR_TSEQRAD_NOR(0x13))
145#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
146 FTIM2_NOR_TCH(0x4) | \
147 FTIM2_NOR_TWPH(0xe) | \
148 FTIM2_NOR_TWP(0x1c))
149#define CONFIG_SYS_NOR_FTIM3 0
150
151#define CONFIG_FLASH_CFI_DRIVER
152#define CONFIG_SYS_FLASH_CFI
153#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
154#define CONFIG_SYS_FLASH_QUIET_TEST
155#define CONFIG_FLASH_SHOW_PROGRESS 45
156#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
Yuan Yao272c5262014-10-17 15:26:34 +0800157#define CONFIG_SYS_WRITE_SWAPPED_DATA
Wang Huan550e3dc2014-09-05 13:52:44 +0800158
159#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
160#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
161#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
162#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
163
164#define CONFIG_SYS_FLASH_EMPTY_INFO
165#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
166 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
167
168/*
169 * NAND Flash Definitions
170 */
171#define CONFIG_NAND_FSL_IFC
172
173#define CONFIG_SYS_NAND_BASE 0x7e800000
174#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
175
176#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
177
178#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
179 | CSPR_PORT_SIZE_8 \
180 | CSPR_MSEL_NAND \
181 | CSPR_V)
182#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
183#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
184 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
185 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
186 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
187 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
188 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
189 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
190
191#define CONFIG_SYS_NAND_ONFI_DETECTION
192
193#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
194 FTIM0_NAND_TWP(0x18) | \
195 FTIM0_NAND_TWCHT(0x7) | \
196 FTIM0_NAND_TWH(0xa))
197#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
198 FTIM1_NAND_TWBE(0x39) | \
199 FTIM1_NAND_TRR(0xe) | \
200 FTIM1_NAND_TRP(0x18))
201#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
202 FTIM2_NAND_TREH(0xa) | \
203 FTIM2_NAND_TWHRE(0x1e))
204#define CONFIG_SYS_NAND_FTIM3 0x0
205
206#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
207#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wang Huan550e3dc2014-09-05 13:52:44 +0800208
209#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Alison Wangd612f0a2014-12-09 17:38:02 +0800210#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800211
212/*
213 * QIXIS Definitions
214 */
215#define CONFIG_FSL_QIXIS
216
217#ifdef CONFIG_FSL_QIXIS
218#define QIXIS_BASE 0x7fb00000
219#define QIXIS_BASE_PHYS QIXIS_BASE
220#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
221#define QIXIS_LBMAP_SWITCH 6
222#define QIXIS_LBMAP_MASK 0x0f
223#define QIXIS_LBMAP_SHIFT 0
224#define QIXIS_LBMAP_DFLTBANK 0x00
225#define QIXIS_LBMAP_ALTBANK 0x04
Hongbo Zhangaeb901f2016-07-21 18:09:38 +0800226#define QIXIS_PWR_CTL 0x21
227#define QIXIS_PWR_CTL_POWEROFF 0x80
Wang Huan550e3dc2014-09-05 13:52:44 +0800228#define QIXIS_RST_CTL_RESET 0x44
229#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
230#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
231#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
Hongbo Zhang349cfc92016-08-19 17:20:31 +0800232#define QIXIS_CTL_SYS 0x5
233#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
234#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
235#define QIXIS_RST_FORCE_3 0x45
236#define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
237#define QIXIS_PWR_CTL2 0x21
238#define QIXIS_PWR_CTL2_PCTL 0x2
Wang Huan550e3dc2014-09-05 13:52:44 +0800239
240#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
241#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
242 CSPR_PORT_SIZE_8 | \
243 CSPR_MSEL_GPCM | \
244 CSPR_V)
245#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
246#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
247 CSOR_NOR_NOR_MODE_AVD_NOR | \
248 CSOR_NOR_TRHZ_80)
249
250/*
251 * QIXIS Timing parameters for IFC GPCM
252 */
253#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
254 FTIM0_GPCM_TEADC(0xe) | \
255 FTIM0_GPCM_TEAHC(0xe))
256#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
257 FTIM1_GPCM_TRAD(0x1f))
258#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
259 FTIM2_GPCM_TCH(0xe) | \
260 FTIM2_GPCM_TWP(0xf0))
261#define CONFIG_SYS_FPGA_FTIM3 0x0
262#endif
263
Alison Wang8ab967b2014-12-09 17:38:14 +0800264#if defined(CONFIG_NAND_BOOT)
265#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
266#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
267#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
268#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
269#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
270#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
271#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
272#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
273#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
274#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
275#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
276#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
277#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
278#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
279#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
280#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
281#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
282#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
283#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
284#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
285#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
286#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
287#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
288#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
289#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
290#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
291#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
292#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
293#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
294#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
295#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
296#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
297#else
Wang Huan550e3dc2014-09-05 13:52:44 +0800298#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
299#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
300#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
301#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
302#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
303#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
304#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
305#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
306#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
307#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
308#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
309#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
310#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
311#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
312#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
313#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
314#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
315#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
316#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
317#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
318#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
319#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
320#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
321#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
322#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
323#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
324#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
325#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
326#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
327#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
328#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
329#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
Alison Wang8ab967b2014-12-09 17:38:14 +0800330#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800331
332/*
333 * Serial Port
334 */
Alison Wang8fc21212015-01-04 15:30:58 +0800335#ifdef CONFIG_LPUART
Alison Wang8fc21212015-01-04 15:30:58 +0800336#define CONFIG_LPUART_32B_REG
337#else
Wang Huan550e3dc2014-09-05 13:52:44 +0800338#define CONFIG_SYS_NS16550_SERIAL
York Sund83b47b2016-02-08 13:04:17 -0800339#ifndef CONFIG_DM_SERIAL
Wang Huan550e3dc2014-09-05 13:52:44 +0800340#define CONFIG_SYS_NS16550_REG_SIZE 1
York Sund83b47b2016-02-08 13:04:17 -0800341#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800342#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Alison Wang8fc21212015-01-04 15:30:58 +0800343#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800344
Wang Huan550e3dc2014-09-05 13:52:44 +0800345/*
346 * I2C
347 */
Wang Huan550e3dc2014-09-05 13:52:44 +0800348#define CONFIG_SYS_I2C
349#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +0200350#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
351#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf8cb1012015-03-20 10:20:40 -0700352#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Wang Huan550e3dc2014-09-05 13:52:44 +0800353
Jagdish Gediya73dc91f2018-05-10 04:04:29 +0530354/* EEPROM */
355#define CONFIG_ID_EEPROM
356#define CONFIG_SYS_I2C_EEPROM_NXID
357#define CONFIG_SYS_EEPROM_BUS_NUM 0
358#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
359#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
360#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
361#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
362
Wang Huan550e3dc2014-09-05 13:52:44 +0800363/*
364 * I2C bus multiplexer
365 */
366#define I2C_MUX_PCA_ADDR_PRI 0x77
367#define I2C_MUX_CH_DEFAULT 0x8
Xiubo Lidd048322014-12-16 14:50:33 +0800368#define I2C_MUX_CH_CH7301 0xC
Wang Huan550e3dc2014-09-05 13:52:44 +0800369
370/*
371 * MMC
372 */
Wang Huan550e3dc2014-09-05 13:52:44 +0800373
Haikun Wange5493d42015-06-29 13:08:46 +0530374/* SPI */
Alison Wang70097022016-02-02 15:16:23 +0800375#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Haikun Wange5493d42015-06-29 13:08:46 +0530376/* QSPI */
Alison Wangd612f0a2014-12-09 17:38:02 +0800377#define QSPI0_AMBA_BASE 0x40000000
378#define FSL_QSPI_FLASH_SIZE (1 << 24)
379#define FSL_QSPI_FLASH_NUM 2
Haikun Wange5493d42015-06-29 13:08:46 +0530380
381/* DSPI */
Haikun Wange5493d42015-06-29 13:08:46 +0530382
383/* DM SPI */
384#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
Haikun Wange5493d42015-06-29 13:08:46 +0530385#define CONFIG_DM_SPI_FLASH
Jagan Teki68124842015-06-27 22:04:55 +0530386#define CONFIG_SPI_FLASH_DATAFLASH
Haikun Wange5493d42015-06-29 13:08:46 +0530387#endif
Alison Wangd612f0a2014-12-09 17:38:02 +0800388#endif
389
Wang Huan550e3dc2014-09-05 13:52:44 +0800390/*
Xiubo Lidd048322014-12-16 14:50:33 +0800391 * Video
392 */
Sanchayan Maityb215fb32017-04-11 11:12:09 +0530393#ifdef CONFIG_VIDEO_FSL_DCU_FB
Xiubo Lidd048322014-12-16 14:50:33 +0800394#define CONFIG_VIDEO_LOGO
395#define CONFIG_VIDEO_BMP_LOGO
396
397#define CONFIG_FSL_DIU_CH7301
398#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
399#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
400#define CONFIG_SYS_I2C_DVI_ADDR 0x75
401#endif
402
403/*
Wang Huan550e3dc2014-09-05 13:52:44 +0800404 * eTSEC
405 */
Wang Huan550e3dc2014-09-05 13:52:44 +0800406
407#ifdef CONFIG_TSEC_ENET
408#define CONFIG_MII
409#define CONFIG_MII_DEFAULT_TSEC 3
410#define CONFIG_TSEC1 1
411#define CONFIG_TSEC1_NAME "eTSEC1"
412#define CONFIG_TSEC2 1
413#define CONFIG_TSEC2_NAME "eTSEC2"
414#define CONFIG_TSEC3 1
415#define CONFIG_TSEC3_NAME "eTSEC3"
416
417#define TSEC1_PHY_ADDR 1
418#define TSEC2_PHY_ADDR 2
419#define TSEC3_PHY_ADDR 3
420
421#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
422#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
423#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
424
425#define TSEC1_PHYIDX 0
426#define TSEC2_PHYIDX 0
427#define TSEC3_PHYIDX 0
428
429#define CONFIG_ETHPRIME "eTSEC1"
430
Wang Huan550e3dc2014-09-05 13:52:44 +0800431#define CONFIG_PHY_REALTEK
432
433#define CONFIG_HAS_ETH0
434#define CONFIG_HAS_ETH1
435#define CONFIG_HAS_ETH2
436
437#define CONFIG_FSL_SGMII_RISER 1
438#define SGMII_RISER_PHY_OFFSET 0x1b
439
440#ifdef CONFIG_FSL_SGMII_RISER
441#define CONFIG_SYS_TBIPA_VALUE 8
442#endif
443
444#endif
Minghuan Lianda419022014-10-31 13:43:44 +0800445
446/* PCIe */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -0400447#define CONFIG_PCIE1 /* PCIE controller 1 */
448#define CONFIG_PCIE2 /* PCIE controller 2 */
Minghuan Lianda419022014-10-31 13:43:44 +0800449
Minghuan Lian180b8682015-01-21 17:29:19 +0800450#ifdef CONFIG_PCI
Minghuan Lian180b8682015-01-21 17:29:19 +0800451#define CONFIG_PCI_SCAN_SHOW
Minghuan Lian180b8682015-01-21 17:29:19 +0800452#endif
453
Wang Huan550e3dc2014-09-05 13:52:44 +0800454#define CONFIG_CMDLINE_TAG
Alison Wang86949c22014-12-03 15:00:47 +0800455
Xiubo Li1a2826f2014-11-21 17:40:57 +0800456#define CONFIG_PEN_ADDR_BIG_ENDIAN
Mingkai Hu435acd82015-10-26 19:47:41 +0800457#define CONFIG_LAYERSCAPE_NS_ACCESS
Xiubo Li1a2826f2014-11-21 17:40:57 +0800458#define CONFIG_SMP_PEN_ADDR 0x01ee0200
Andre Przywarae4916e82017-02-16 01:20:19 +0000459#define COUNTER_FREQUENCY 12500000
Xiubo Li1a2826f2014-11-21 17:40:57 +0800460
Wang Huan550e3dc2014-09-05 13:52:44 +0800461#define CONFIG_HWCONFIG
Zhuoyu Zhang03c22442015-08-17 18:55:12 +0800462#define HWCONFIG_BUFFER_SIZE 256
463
464#define CONFIG_FSL_DEVICE_DISABLE
Wang Huan550e3dc2014-09-05 13:52:44 +0800465
Wang Huan550e3dc2014-09-05 13:52:44 +0800466
Alison Wang615bfce2017-05-16 10:45:57 +0800467#define CONFIG_SYS_QE_FW_ADDR 0x60940000
Zhao Qiang63e75fd2014-09-26 16:25:32 +0800468
Alison Wang8fc21212015-01-04 15:30:58 +0800469#ifdef CONFIG_LPUART
470#define CONFIG_EXTRA_ENV_SETTINGS \
471 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
Alison Wang99fe4542015-11-05 11:16:26 +0800472 "fdt_high=0xffffffff\0" \
473 "initrd_high=0xffffffff\0" \
Alison Wang8fc21212015-01-04 15:30:58 +0800474 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
475#else
Wang Huan550e3dc2014-09-05 13:52:44 +0800476#define CONFIG_EXTRA_ENV_SETTINGS \
477 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
Alison Wang99fe4542015-11-05 11:16:26 +0800478 "fdt_high=0xffffffff\0" \
479 "initrd_high=0xffffffff\0" \
Wang Huan550e3dc2014-09-05 13:52:44 +0800480 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
Alison Wang8fc21212015-01-04 15:30:58 +0800481#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800482
483/*
484 * Miscellaneous configurable options
485 */
Wang Huan550e3dc2014-09-05 13:52:44 +0800486
Wang Huan550e3dc2014-09-05 13:52:44 +0800487#define CONFIG_SYS_MEMTEST_START 0x80000000
488#define CONFIG_SYS_MEMTEST_END 0x9fffffff
489
490#define CONFIG_SYS_LOAD_ADDR 0x82000000
Wang Huan550e3dc2014-09-05 13:52:44 +0800491
Xiubo Li660673a2014-11-21 17:40:59 +0800492#define CONFIG_LS102XA_STREAM_ID
493
Wang Huan550e3dc2014-09-05 13:52:44 +0800494#define CONFIG_SYS_INIT_SP_OFFSET \
495 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
496#define CONFIG_SYS_INIT_SP_ADDR \
497 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
498
Alison Wang86949c22014-12-03 15:00:47 +0800499#ifdef CONFIG_SPL_BUILD
500#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
501#else
Wang Huan550e3dc2014-09-05 13:52:44 +0800502#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Alison Wang86949c22014-12-03 15:00:47 +0800503#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800504
505/*
506 * Environment
507 */
508#define CONFIG_ENV_OVERWRITE
509
Alison Wang86949c22014-12-03 15:00:47 +0800510#if defined(CONFIG_SD_BOOT)
Alison Wang615bfce2017-05-16 10:45:57 +0800511#define CONFIG_ENV_OFFSET 0x300000
Alison Wang86949c22014-12-03 15:00:47 +0800512#define CONFIG_SYS_MMC_ENV_DEV 0
513#define CONFIG_ENV_SIZE 0x2000
Alison Wangd612f0a2014-12-09 17:38:02 +0800514#elif defined(CONFIG_QSPI_BOOT)
Alison Wangd612f0a2014-12-09 17:38:02 +0800515#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
Alison Wang615bfce2017-05-16 10:45:57 +0800516#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
Alison Wangd612f0a2014-12-09 17:38:02 +0800517#define CONFIG_ENV_SECT_SIZE 0x10000
Alison Wang8ab967b2014-12-09 17:38:14 +0800518#elif defined(CONFIG_NAND_BOOT)
Alison Wang8ab967b2014-12-09 17:38:14 +0800519#define CONFIG_ENV_SIZE 0x2000
520#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
Alison Wang86949c22014-12-03 15:00:47 +0800521#else
Alison Wang615bfce2017-05-16 10:45:57 +0800522#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
Wang Huan550e3dc2014-09-05 13:52:44 +0800523#define CONFIG_ENV_SIZE 0x2000
524#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
Alison Wang86949c22014-12-03 15:00:47 +0800525#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800526
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530527#define CONFIG_MISC_INIT_R
528
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530529#include <asm/fsl_secure_boot.h>
Alison Wangcc7b8b92016-01-15 15:29:32 +0800530#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530531
Wang Huan550e3dc2014-09-05 13:52:44 +0800532#endif