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Magnus Lilja8449f282009-07-01 01:07:55 +02001/*
2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
3 *
4 * (C) Copyright 2004
5 * Texas Instruments.
6 * Richard Woodruff <r-woodruff2@ti.com>
7 * Kshitij Gupta <kshitij@ti.com>
8 *
9 * Configuration settings for the Freescale i.MX31 PDK board.
10 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
Magnus Lilja8449f282009-07-01 01:07:55 +020012 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
Stefano Babic86271112011-03-14 15:43:56 +010017#include <asm/arch/imx-regs.h>
Magnus Lilja38a8b3e2010-01-17 17:46:11 +010018
Magnus Lilja8449f282009-07-01 01:07:55 +020019/* High Level Configuration Options */
Fabio Estevame89f1f92011-04-26 11:04:37 +000020#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
21#define CONFIG_MX31 /* in a mx31 */
Magnus Lilja8449f282009-07-01 01:07:55 +020022
23#define CONFIG_DISPLAY_CPUINFO
24#define CONFIG_DISPLAY_BOARDINFO
25
Fabio Estevame89f1f92011-04-26 11:04:37 +000026#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
27#define CONFIG_SETUP_MEMORY_TAGS
28#define CONFIG_INITRD_TAG
Magnus Lilja8449f282009-07-01 01:07:55 +020029
Fabio Estevam9aa3c6a2011-09-22 08:07:14 +000030#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
31
Benoît Thébaudeauda962b72013-04-11 09:35:51 +000032#define CONFIG_SPL
33#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
34#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
35#define CONFIG_SPL_MAX_SIZE 2048
36#define CONFIG_SPL_NAND_SUPPORT
Andreas Bießmannb1573152013-04-18 22:48:48 +000037#define CONFIG_SPL_LIBGENERIC_SUPPORT
Benoît Thébaudeauda962b72013-04-11 09:35:51 +000038
39#define CONFIG_SPL_TEXT_BASE 0x87dc0000
40#define CONFIG_SYS_TEXT_BASE 0x87e00000
41
42#ifndef CONFIG_SPL_BUILD
Magnus Lilja8449f282009-07-01 01:07:55 +020043#define CONFIG_SKIP_LOWLEVEL_INIT
Magnus Liljad08e5ca2009-07-04 10:31:24 +020044#endif
Magnus Lilja8449f282009-07-01 01:07:55 +020045
46/*
47 * Size of malloc() pool
48 */
Magnus Lilja38a8b3e2010-01-17 17:46:11 +010049#define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
Magnus Lilja8449f282009-07-01 01:07:55 +020050
51/*
52 * Hardware drivers
53 */
54
Fabio Estevame89f1f92011-04-26 11:04:37 +000055#define CONFIG_MXC_UART
Stefano Babic40f6fff2011-11-22 15:22:39 +010056#define CONFIG_MXC_UART_BASE UART1_BASE
Stefano Babic6f2a4be2011-09-07 10:51:43 +000057#define CONFIG_MXC_GPIO
Magnus Lilja8449f282009-07-01 01:07:55 +020058
Fabio Estevame89f1f92011-04-26 11:04:37 +000059#define CONFIG_HARD_SPI
60#define CONFIG_MXC_SPI
Magnus Lilja8449f282009-07-01 01:07:55 +020061#define CONFIG_DEFAULT_SPI_BUS 1
Stefano Babic9f481e92010-08-23 20:41:19 +020062#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
Magnus Lilja8449f282009-07-01 01:07:55 +020063
Stefano Babic877a4382011-10-08 11:04:22 +020064/* PMIC Controller */
Łukasz Majewskibe3b51a2012-11-13 03:22:14 +000065#define CONFIG_POWER
66#define CONFIG_POWER_SPI
67#define CONFIG_POWER_FSL
Stefano Babicdfe5e142010-04-16 17:11:19 +020068#define CONFIG_FSL_PMIC_BUS 1
69#define CONFIG_FSL_PMIC_CS 2
70#define CONFIG_FSL_PMIC_CLK 1000000
Stefano Babic9f481e92010-08-23 20:41:19 +020071#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
Stefano Babic877a4382011-10-08 11:04:22 +020072#define CONFIG_FSL_PMIC_BITLEN 32
Fabio Estevam4e8b7542011-10-24 06:44:15 +000073#define CONFIG_RTC_MC13XXX
Magnus Lilja8449f282009-07-01 01:07:55 +020074
Magnus Lilja8449f282009-07-01 01:07:55 +020075/* allow to overwrite serial and ethaddr */
76#define CONFIG_ENV_OVERWRITE
77#define CONFIG_CONS_INDEX 1
78#define CONFIG_BAUDRATE 115200
Magnus Lilja8449f282009-07-01 01:07:55 +020079
80/***********************************************************
81 * Command definition
82 ***********************************************************/
83
84#include <config_cmd_default.h>
85
86#define CONFIG_CMD_MII
87#define CONFIG_CMD_PING
Fabio Estevamfc971022011-06-15 03:36:23 +000088#define CONFIG_CMD_DHCP
Magnus Lilja8449f282009-07-01 01:07:55 +020089#define CONFIG_CMD_SPI
90#define CONFIG_CMD_DATE
Magnus Lilja38a8b3e2010-01-17 17:46:11 +010091#define CONFIG_CMD_NAND
Fabio Estevam0c23d842012-04-23 06:31:18 +000092#define CONFIG_CMD_BOOTZ
Magnus Lilja8449f282009-07-01 01:07:55 +020093
94/*
95 * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
96 * that CFG_NO_FLASH is undefined).
97 */
98#undef CONFIG_CMD_IMLS
99
Helmut Raiger9660e442011-10-20 04:19:47 +0000100#define CONFIG_BOARD_LATE_INIT
Fabio Estevamb73850f2011-04-10 08:17:50 +0000101
Fabio Estevam562e6c62012-11-16 05:09:09 +0000102#define CONFIG_BOOTDELAY 1
Magnus Lilja8449f282009-07-01 01:07:55 +0200103
104#define CONFIG_EXTRA_ENV_SETTINGS \
105 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
106 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
107 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
108 "bootcmd=run bootcmd_net\0" \
109 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
Magnus Lilja38a8b3e2010-01-17 17:46:11 +0100110 "tftpboot 0x81000000 uImage-mx31; bootm\0" \
Benoît Thébaudeauda962b72013-04-11 09:35:51 +0000111 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
Magnus Lilja38a8b3e2010-01-17 17:46:11 +0100112 "nand erase 0x0 0x40000; " \
113 "nand write 0x81000000 0x0 0x40000\0"
Magnus Lilja8449f282009-07-01 01:07:55 +0200114
Fabio Estevame89f1f92011-04-26 11:04:37 +0000115#define CONFIG_SMC911X
Ben Warren736fead2009-07-20 22:01:11 -0700116#define CONFIG_SMC911X_BASE 0xB6000000
Fabio Estevame89f1f92011-04-26 11:04:37 +0000117#define CONFIG_SMC911X_32_BIT
Magnus Lilja8449f282009-07-01 01:07:55 +0200118
119/*
120 * Miscellaneous configurable options
121 */
122#define CONFIG_SYS_LONGHELP /* undef to save memory */
Magnus Lilja8449f282009-07-01 01:07:55 +0200123#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
124/* Print Buffer Size */
125#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
126 sizeof(CONFIG_SYS_PROMPT)+16)
127/* max number of command args */
128#define CONFIG_SYS_MAXARGS 16
129/* Boot Argument Buffer Size */
130#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
131
132/* memtest works on */
133#define CONFIG_SYS_MEMTEST_START 0x80000000
Fabio Estevam304e49e2012-02-09 14:25:07 +0000134#define CONFIG_SYS_MEMTEST_END 0x80010000
Magnus Lilja8449f282009-07-01 01:07:55 +0200135
136/* default load address */
137#define CONFIG_SYS_LOAD_ADDR 0x81000000
138
Fabio Estevame89f1f92011-04-26 11:04:37 +0000139#define CONFIG_CMDLINE_EDITING
Magnus Lilja8449f282009-07-01 01:07:55 +0200140
141/*-----------------------------------------------------------------------
Magnus Lilja8449f282009-07-01 01:07:55 +0200142 * Physical Memory Map
143 */
144#define CONFIG_NR_DRAM_BANKS 1
145#define PHYS_SDRAM_1 CSD0_BASE
146#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
Fabio Estevame89f1f92011-04-26 11:04:37 +0000147#define CONFIG_BOARD_EARLY_INIT_F
Magnus Lilja8449f282009-07-01 01:07:55 +0200148
Fabio Estevamed3df722011-02-09 01:17:55 +0000149#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
150#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
151#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
Fabio Estevam026ca652011-07-04 09:29:46 +0000152#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
153 GENERATED_GBL_DATA_SIZE)
154#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
Benoît Thébaudeauda962b72013-04-11 09:35:51 +0000155 CONFIG_SYS_INIT_RAM_SIZE)
Fabio Estevamed3df722011-02-09 01:17:55 +0000156
Magnus Lilja8449f282009-07-01 01:07:55 +0200157/*-----------------------------------------------------------------------
158 * FLASH and environment organization
159 */
160/* No NOR flash present */
Fabio Estevame89f1f92011-04-26 11:04:37 +0000161#define CONFIG_SYS_NO_FLASH
Magnus Lilja8449f282009-07-01 01:07:55 +0200162
Fabio Estevame89f1f92011-04-26 11:04:37 +0000163#define CONFIG_ENV_IS_IN_NAND
Magnus Lilja38a8b3e2010-01-17 17:46:11 +0100164#define CONFIG_ENV_OFFSET 0x40000
165#define CONFIG_ENV_OFFSET_REDUND 0x60000
166#define CONFIG_ENV_SIZE (128 * 1024)
Magnus Lilja8449f282009-07-01 01:07:55 +0200167
Magnus Lilja38a8b3e2010-01-17 17:46:11 +0100168/*
169 * NAND driver
170 */
171#define CONFIG_NAND_MXC
172#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
173#define CONFIG_SYS_MAX_NAND_DEVICE 1
174#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
175#define CONFIG_MXC_NAND_HWECC
176#define CONFIG_SYS_NAND_LARGEPAGE
Magnus Lilja8449f282009-07-01 01:07:55 +0200177
Magnus Liljad08e5ca2009-07-04 10:31:24 +0200178/* NAND configuration for the NAND_SPL */
179
180/* Start copying real U-boot from the second page */
Benoît Thébaudeauda962b72013-04-11 09:35:51 +0000181#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
182#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800
Magnus Liljad08e5ca2009-07-04 10:31:24 +0200183/* Load U-Boot to this address */
Benoît Thébaudeauda962b72013-04-11 09:35:51 +0000184#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
Magnus Liljad08e5ca2009-07-04 10:31:24 +0200185#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
186
187#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
188#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
189#define CONFIG_SYS_NAND_PAGE_COUNT 64
190#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
191#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
192
193
194/* Configuration of lowlevel_init.S (clocks and SDRAM) */
195#define CCM_CCMR_SETUP 0x074B0BF5
Benoît Thébaudeau9e0081d2012-08-14 08:43:07 +0000196#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
197 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \
198 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \
199 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
200#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
Magnus Liljad08e5ca2009-07-04 10:31:24 +0200201 PLL_MFN(12))
202
203#define ESDMISC_MDDR_SETUP 0x00000004
204#define ESDMISC_MDDR_RESET_DL 0x0000000c
205#define ESDCFG0_MDDR_SETUP 0x006ac73a
206
207#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
208#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
209 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
210#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
211#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
212#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
213#define ESDCTL_RW ESDCTL_SETTINGS
214
Magnus Lilja8449f282009-07-01 01:07:55 +0200215#endif /* __CONFIG_H */