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wdenkc7de8292002-11-19 11:04:11 +00001/*
2 * (C) Copyright 2002
3 * Adam Kowalczyk, ACK Software Controls Inc. akowalczyk@cogeco.ca
4 *
5 * Some portions taken from 3c59x.c Written 1996-1999 by Donald Becker.
6 *
7 * Outline of the program based on eepro100.c which is
8 *
9 * (C) Copyright 2002
10 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <malloc.h>
30#include <net.h>
31#include <asm/io.h>
32#include <pci.h>
33
34#include "articiaS.h"
35#include "memio.h"
36
37/* 3Com Ethernet PCI definitions*/
38
wdenk8bde7f72003-06-27 21:31:46 +000039/* #define PCI_VENDOR_ID_3COM 0x10B7 */
wdenkc7de8292002-11-19 11:04:11 +000040#define PCI_DEVICE_ID_3COM_3C905C 0x9200
41
42/* 3Com Commands, top 5 bits are command and bottom 11 bits are parameters */
43
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010044#define TotalReset (0<<11)
45#define SelectWindow (1<<11)
46#define StartCoax (2<<11)
47#define RxDisable (3<<11)
48#define RxEnable (4<<11)
49#define RxReset (5<<11)
50#define UpStall (6<<11)
51#define UpUnstall (6<<11)+1
52#define DownStall (6<<11)+2
53#define DownUnstall (6<<11)+3
54#define RxDiscard (8<<11)
55#define TxEnable (9<<11)
56#define TxDisable (10<<11)
57#define TxReset (11<<11)
58#define FakeIntr (12<<11)
59#define AckIntr (13<<11)
60#define SetIntrEnb (14<<11)
61#define SetStatusEnb (15<<11)
62#define SetRxFilter (16<<11)
63#define SetRxThreshold (17<<11)
64#define SetTxThreshold (18<<11)
65#define SetTxStart (19<<11)
66#define StartDMAUp (20<<11)
67#define StartDMADown (20<<11)+1
wdenkc7de8292002-11-19 11:04:11 +000068#define StatsEnable (21<<11)
wdenk8bde7f72003-06-27 21:31:46 +000069#define StatsDisable (22<<11)
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010070#define StopCoax (23<<11)
71#define SetFilterBit (25<<11)
wdenkc7de8292002-11-19 11:04:11 +000072
73/* The SetRxFilter command accepts the following classes */
74
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010075#define RxStation 1
wdenk8bde7f72003-06-27 21:31:46 +000076#define RxMulticast 2
77#define RxBroadcast 4
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010078#define RxProm 8
wdenkc7de8292002-11-19 11:04:11 +000079
80/* 3Com status word defnitions */
81
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010082#define IntLatch 0x0001
83#define HostError 0x0002
84#define TxComplete 0x0004
85#define TxAvailable 0x0008
86#define RxComplete 0x0010
87#define RxEarly 0x0020
88#define IntReq 0x0040
89#define StatsFull 0x0080
90#define DMADone (1<<8)
91#define DownComplete (1<<9)
92#define UpComplete (1<<10)
93#define DMAInProgress (1<<11) /* DMA controller is still busy.*/
94#define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/
wdenkc7de8292002-11-19 11:04:11 +000095
96/* Polling Registers */
97
98#define DnPoll 0x2d
99#define UpPoll 0x3d
100
101/* Register window 0 offets */
102
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100103#define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */
104#define Wn0EepromData 12 /* Window 0: EEPROM results register. */
wdenkc7de8292002-11-19 11:04:11 +0000105#define IntrStatus 0x0E /* Valid in all windows. */
106
107/* Register window 0 EEPROM bits */
108
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100109#define EEPROM_Read 0x80
110#define EEPROM_WRITE 0x40
111#define EEPROM_ERASE 0xC0
112#define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */
113#define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */
wdenkc7de8292002-11-19 11:04:11 +0000114
115/* EEPROM locations. */
116
wdenk8bde7f72003-06-27 21:31:46 +0000117#define PhysAddr01 0
wdenkc7de8292002-11-19 11:04:11 +0000118#define PhysAddr23 1
wdenk8bde7f72003-06-27 21:31:46 +0000119#define PhysAddr45 2
wdenkc7de8292002-11-19 11:04:11 +0000120#define ModelID 3
wdenk8bde7f72003-06-27 21:31:46 +0000121#define EtherLink3ID 7
122#define IFXcvrIO 8
wdenkc7de8292002-11-19 11:04:11 +0000123#define IRQLine 9
wdenk8bde7f72003-06-27 21:31:46 +0000124#define NodeAddr01 10
125#define NodeAddr23 11
wdenkc7de8292002-11-19 11:04:11 +0000126#define NodeAddr45 12
wdenk8bde7f72003-06-27 21:31:46 +0000127#define DriverTune 13
wdenkc7de8292002-11-19 11:04:11 +0000128#define Checksum 15
129
130/* Register window 1 offsets, the window used in normal operation */
131
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100132#define TX_FIFO 0x10
133#define RX_FIFOa 0x10
134#define RxErrors 0x14
135#define RxStatus 0x18
wdenk8bde7f72003-06-27 21:31:46 +0000136#define Timer 0x1A
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100137#define TxStatus 0x1B
138#define TxFree 0x1C /* Remaining free bytes in Tx buffer. */
wdenkc7de8292002-11-19 11:04:11 +0000139
140/* Register Window 2 */
wdenk8bde7f72003-06-27 21:31:46 +0000141
wdenkc7de8292002-11-19 11:04:11 +0000142#define Wn2_ResetOptions 12
143
144/* Register Window 3: MAC/config bits */
145
146#define Wn3_Config 0 /* Internal Configuration */
147#define Wn3_MAC_Ctrl 6
148#define Wn3_Options 8
149
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100150#define BFEXT(value, offset, bitcount) \
wdenk8bde7f72003-06-27 21:31:46 +0000151 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
wdenkc7de8292002-11-19 11:04:11 +0000152
153#define BFINS(lhs, rhs, offset, bitcount) \
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100154 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
wdenk8bde7f72003-06-27 21:31:46 +0000155 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
wdenkc7de8292002-11-19 11:04:11 +0000156
157#define RAM_SIZE(v) BFEXT(v, 0, 3)
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100158#define RAM_WIDTH(v) BFEXT(v, 3, 1)
159#define RAM_SPEED(v) BFEXT(v, 4, 2)
wdenkc7de8292002-11-19 11:04:11 +0000160#define ROM_SIZE(v) BFEXT(v, 6, 2)
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100161#define RAM_SPLIT(v) BFEXT(v, 16, 2)
wdenkc7de8292002-11-19 11:04:11 +0000162#define XCVR(v) BFEXT(v, 20, 4)
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100163#define AUTOSELECT(v) BFEXT(v, 24, 1)
wdenkc7de8292002-11-19 11:04:11 +0000164
165/* Register Window 4: Xcvr/media bits */
wdenk8bde7f72003-06-27 21:31:46 +0000166
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100167#define Wn4_FIFODiag 4
168#define Wn4_NetDiag 6
wdenkc7de8292002-11-19 11:04:11 +0000169#define Wn4_PhysicalMgmt 8
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100170#define Wn4_Media 10
wdenkc7de8292002-11-19 11:04:11 +0000171
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100172#define Media_SQE 0x0008 /* Enable SQE error counting for AUI. */
173#define Media_10TP 0x00C0 /* Enable link beat and jabber for 10baseT. */
174#define Media_Lnk 0x0080 /* Enable just link beat for 100TX/100FX. */
175#define Media_LnkBeat 0x0800
wdenkc7de8292002-11-19 11:04:11 +0000176
177/* Register Window 7: Bus Master control */
178
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100179#define Wn7_MasterAddr 0
180#define Wn7_MasterLen 6
181#define Wn7_MasterStatus 12
wdenkc7de8292002-11-19 11:04:11 +0000182
183/* Boomerang bus master control registers. */
184
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100185#define PktStatus 0x20
wdenkc7de8292002-11-19 11:04:11 +0000186#define DownListPtr 0x24
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100187#define FragAddr 0x28
188#define FragLen 0x2c
wdenkc7de8292002-11-19 11:04:11 +0000189#define TxFreeThreshold 0x2f
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100190#define UpPktStatus 0x30
wdenkc7de8292002-11-19 11:04:11 +0000191#define UpListPtr 0x38
192
193/* The Rx and Tx descriptor lists. */
194
195#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
196#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
197
198struct rx_desc_3com {
wdenk8bde7f72003-06-27 21:31:46 +0000199 u32 next; /* Last entry points to 0 */
200 u32 status; /* FSH -> Frame Start Header */
201 u32 addr; /* Up to 63 addr/len pairs possible */
202 u32 length; /* Set LAST_FRAG to indicate last pair */
wdenkc7de8292002-11-19 11:04:11 +0000203};
204
205/* Values for the Rx status entry. */
206
207#define RxDComplete 0x00008000
208#define RxDError 0x4000
wdenk8bde7f72003-06-27 21:31:46 +0000209#define IPChksumErr (1<<25)
210#define TCPChksumErr (1<<26)
wdenkc7de8292002-11-19 11:04:11 +0000211#define UDPChksumErr (1<<27)
wdenk8bde7f72003-06-27 21:31:46 +0000212#define IPChksumValid (1<<29)
wdenkc7de8292002-11-19 11:04:11 +0000213#define TCPChksumValid (1<<30)
214#define UDPChksumValid (1<<31)
215
216struct tx_desc_3com {
wdenk8bde7f72003-06-27 21:31:46 +0000217 u32 next; /* Last entry points to 0 */
218 u32 status; /* bits 0:12 length, others see below */
219 u32 addr;
220 u32 length;
wdenkc7de8292002-11-19 11:04:11 +0000221};
222
223/* Values for the Tx status entry. */
224
225#define CRCDisable 0x2000
226#define TxDComplete 0x8000
227#define AddIPChksum 0x02000000
228#define AddTCPChksum 0x04000000
229#define AddUDPChksum 0x08000000
230#define TxIntrUploaded 0x80000000 /* IRQ when in FIFO, but maybe not sent. */
231
232/* XCVR Types */
233
234#define XCVR_10baseT 0
wdenk8bde7f72003-06-27 21:31:46 +0000235#define XCVR_AUI 1
wdenkc7de8292002-11-19 11:04:11 +0000236#define XCVR_10baseTOnly 2
wdenk8bde7f72003-06-27 21:31:46 +0000237#define XCVR_10base2 3
wdenkc7de8292002-11-19 11:04:11 +0000238#define XCVR_100baseTx 4
239#define XCVR_100baseFx 5
240#define XCVR_MII 6
241#define XCVR_NWAY 8
242#define XCVR_ExtMII 9
243#define XCVR_Default 10 /* I don't think this is correct -> should have been 0x10 if Auto Negotiate */
244
245struct descriptor { /* A generic descriptor. */
wdenk8bde7f72003-06-27 21:31:46 +0000246 u32 next; /* Last entry points to 0 */
247 u32 status; /* FSH -> Frame Start Header */
248 u32 addr; /* Up to 63 addr/len pairs possible */
249 u32 length; /* Set LAST_FRAG to indicate last pair */
wdenkc7de8292002-11-19 11:04:11 +0000250};
251
252/* Misc. definitions */
253
254#define NUM_RX_DESC PKTBUFSRX * 10
255#define NUM_TX_DESC 1 /* Number of TX descriptors */
256
257#define TOUT_LOOP 1000000
258
259#define ETH_ALEN 6
260
261#define EL3WINDOW(dev, win_num) ETH_OUTW(dev, SelectWindow + (win_num), EL3_CMD)
262#define EL3_CMD 0x0e
263#define EL3_STATUS 0x0e
264
265
266#undef ETH_DEBUG
267
268#ifdef ETH_DEBUG
269#define PRINTF(fmt,args...) printf (fmt ,##args)
270#else
271#define PRINTF(fmt,args...)
272#endif
273
274
275static struct rx_desc_3com *rx_ring; /* RX descriptor ring */
276static struct tx_desc_3com *tx_ring; /* TX descriptor ring */
277static u8 rx_buffer[NUM_RX_DESC][PKTSIZE_ALIGN]; /* storage for the incoming messages */
278static int rx_next = 0; /* RX descriptor ring pointer */
279static int tx_next = 0; /* TX descriptor ring pointer */
280static int tx_threshold;
281
282static void init_rx_ring(struct eth_device* dev);
283static void purge_tx_ring(struct eth_device* dev);
284
285static void read_hw_addr(struct eth_device* dev, bd_t * bis);
286
287static int eth_3com_init(struct eth_device* dev, bd_t *bis);
288static int eth_3com_send(struct eth_device* dev, volatile void *packet, int length);
289static int eth_3com_recv(struct eth_device* dev);
290static void eth_3com_halt(struct eth_device* dev);
291
292#define io_to_phys(a) pci_io_to_phys((pci_dev_t)dev->priv, a)
293#define phys_to_io(a) pci_phys_to_io((pci_dev_t)dev->priv, a)
294#define mem_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
295#define phys_to_mem(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
296
297static inline int ETH_INL(struct eth_device* dev, u_long addr)
298{
299 __asm volatile ("eieio");
300 return le32_to_cpu(*(volatile u32 *)io_to_phys(addr + dev->iobase));
301}
302
303static inline int ETH_INW(struct eth_device* dev, u_long addr)
304{
305 __asm volatile ("eieio");
306 return le16_to_cpu(*(volatile u16 *)io_to_phys(addr + dev->iobase));
307}
308
309static inline int ETH_INB(struct eth_device* dev, u_long addr)
310{
311 __asm volatile ("eieio");
312 return *(volatile u8 *)io_to_phys(addr + dev->iobase);
313}
314
315static inline void ETH_OUTB(struct eth_device* dev, int command, u_long addr)
316{
317 *(volatile u8 *)io_to_phys(addr + dev->iobase) = command;
318 __asm volatile ("eieio");
319}
320
321static inline void ETH_OUTW(struct eth_device* dev, int command, u_long addr)
322{
323 *(volatile u16 *)io_to_phys(addr + dev->iobase) = cpu_to_le16(command);
324 __asm volatile ("eieio");
325}
326
327static inline void ETH_OUTL(struct eth_device* dev, int command, u_long addr)
328{
329 *(volatile u32 *)io_to_phys(addr + dev->iobase) = cpu_to_le32(command);
330 __asm volatile ("eieio");
331}
332
333static inline int ETH_STATUS(struct eth_device* dev)
334{
335 __asm volatile ("eieio");
336 return le16_to_cpu(*(volatile u16 *)io_to_phys(EL3_STATUS + dev->iobase));
337}
338
339static inline void ETH_CMD(struct eth_device* dev, int command)
340{
wdenk8bde7f72003-06-27 21:31:46 +0000341 *(volatile u16 *)io_to_phys(EL3_CMD + dev->iobase) = cpu_to_le16(command);
wdenkc7de8292002-11-19 11:04:11 +0000342 __asm volatile ("eieio");
343}
344
345/* Command register is always in the same spot in all the register windows */
346/* This function issues a command and waits for it so complete by checking the CmdInProgress bit */
347
348static int issue_and_wait(struct eth_device* dev, int command)
349{
350
wdenk8bde7f72003-06-27 21:31:46 +0000351 int i, status;
wdenkc7de8292002-11-19 11:04:11 +0000352
353 ETH_CMD(dev, command);
wdenk8bde7f72003-06-27 21:31:46 +0000354 for (i = 0; i < 2000; i++) {
355 status = ETH_STATUS(dev);
356 /*printf ("Issue: status 0x%4x.\n", status); */
wdenkc7de8292002-11-19 11:04:11 +0000357 if (!(status & CmdInProgress))
wdenk8bde7f72003-06-27 21:31:46 +0000358 return 1;
359 }
wdenkc7de8292002-11-19 11:04:11 +0000360
wdenk8bde7f72003-06-27 21:31:46 +0000361 /* OK, that didn't work. Do it the slow way. One second */
362 for (i = 0; i < 100000; i++) {
363 status = ETH_STATUS(dev);
364 /*printf ("Issue: status 0x%4x.\n", status); */
365 return 1;
366 udelay(10);
367 }
368 PRINTF("Ethernet command: 0x%4x did not complete! Status: 0x%4x\n", command, ETH_STATUS(dev) );
wdenkc7de8292002-11-19 11:04:11 +0000369 return 0;
370}
371
372/* Determine network media type and set up 3com accordingly */
373/* I think I'm going to start with something known first like 10baseT */
374
375static int auto_negotiate(struct eth_device* dev)
376{
377 int i;
378
379 EL3WINDOW(dev, 1);
380
wdenk8bde7f72003-06-27 21:31:46 +0000381 /* Wait for Auto negotiation to complete */
wdenkc7de8292002-11-19 11:04:11 +0000382 for (i = 0; i <= 1000; i++)
383 {
384 if (ETH_INW(dev, 2) & 0x04)
385 break;
386 udelay(100);
387
388 if (i == 1000)
389 {
390 PRINTF("Error: Auto negotiation failed\n");
391 return 0;
392 }
393 }
wdenkc7de8292002-11-19 11:04:11 +0000394
395
396 return 1;
397}
398
399void eth_interrupt(struct eth_device *dev)
400{
401 u16 status = ETH_STATUS(dev);
402
403 printf("eth0: status = 0x%04x\n", status);
404
405 if (!(status & IntLatch))
406 return;
407
408 if (status & (1<<6))
409 {
410 ETH_CMD(dev, AckIntr | (1<<6));
411 printf("Acknowledged Interrupt command\n");
412 }
413
414 if (status & DownComplete)
415 {
416 ETH_CMD(dev, AckIntr | DownComplete);
417 printf("Acknowledged DownComplete\n");
418 }
419
420 if (status & UpComplete)
421 {
422 ETH_CMD(dev, AckIntr | UpComplete);
423 printf("Acknowledged UpComplete\n");
424 }
425
426 ETH_CMD(dev, AckIntr | IntLatch);
427 printf("Acknowledged IntLatch\n");
428}
429
430int eth_3com_initialize(bd_t *bis)
431{
wdenk8bde7f72003-06-27 21:31:46 +0000432 u32 eth_iobase = 0, status;
433 int card_number = 0, ret;
434 struct eth_device* dev;
435 pci_dev_t devno;
wdenkc7de8292002-11-19 11:04:11 +0000436 char *s;
437
438 s = getenv("3com_base");
439
440 /* Find ethernet controller on the PCI bus */
441
442 if ((devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0)) < 0)
443 {
444 PRINTF("Error: Cannot find the ethernet device on the PCI bus\n");
445 goto Done;
446 }
447
448 if (s)
449 {
450 unsigned long base = atoi(s);
451 pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, base | 0x01);
452 }
453
454 ret = pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &eth_iobase);
wdenk8bde7f72003-06-27 21:31:46 +0000455 eth_iobase &= ~0xf;
wdenkc7de8292002-11-19 11:04:11 +0000456
457 PRINTF("eth: 3Com Found at Address: 0x%x\n", eth_iobase);
wdenk8bde7f72003-06-27 21:31:46 +0000458
wdenkc7de8292002-11-19 11:04:11 +0000459 pci_write_config_dword(devno, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
460
461 /* Check if I/O accesses and Bus Mastering are enabled */
462
463 ret = pci_read_config_dword(devno, PCI_COMMAND, &status);
464
465 if (!(status & PCI_COMMAND_IO))
466 {
467 printf("Error: Cannot enable IO access.\n");
468 goto Done;
469 }
470
471 if (!(status & PCI_COMMAND_MEMORY))
472 {
473 printf("Error: Cannot enable MEMORY access.\n");
474 goto Done;
475 }
476
477 if (!(status & PCI_COMMAND_MASTER))
478 {
479 printf("Error: Cannot enable Bus Mastering.\n");
480 goto Done;
481 }
482
wdenk8bde7f72003-06-27 21:31:46 +0000483 dev = (struct eth_device*) malloc(sizeof(*dev)); /*struct eth_device)); */
wdenkc7de8292002-11-19 11:04:11 +0000484
wdenk8bde7f72003-06-27 21:31:46 +0000485 sprintf(dev->name, "3Com 3c920c#%d", card_number);
486 dev->iobase = eth_iobase;
487 dev->priv = (void*) devno;
488 dev->init = eth_3com_init;
489 dev->halt = eth_3com_halt;
490 dev->send = eth_3com_send;
491 dev->recv = eth_3com_recv;
wdenkc7de8292002-11-19 11:04:11 +0000492
wdenk8bde7f72003-06-27 21:31:46 +0000493 eth_register(dev);
wdenkc7de8292002-11-19 11:04:11 +0000494
495/* { */
496/* char interrupt; */
497/* devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */
498/* pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */
wdenk8bde7f72003-06-27 21:31:46 +0000499
wdenkc7de8292002-11-19 11:04:11 +0000500/* printf("Installing eth0 interrupt handler to %d\n", interrupt); */
501/* irq_install_handler(interrupt, eth_interrupt, dev); */
502/* } */
503
wdenk8bde7f72003-06-27 21:31:46 +0000504 card_number++;
wdenkc7de8292002-11-19 11:04:11 +0000505
506 /* Set the latency timer for value */
507 s = getenv("3com_latency");
508 if (s)
509 {
510 ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, (unsigned char)atoi(s));
511 }
512 else ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x0a);
513
514 read_hw_addr(dev, bis); /* get the MAC address from Window 2*/
515
516 /* Reset the ethernet controller */
517
518 PRINTF ("Issuing reset command....\n");
519 if (!issue_and_wait(dev, TotalReset))
520 {
521 printf("Error: Cannot reset ethernet controller.\n");
522 goto Done;
523 }
524 else
525 PRINTF ("Ethernet controller reset.\n");
526
527 /* allocate memory for rx and tx rings */
528
529 if(!(rx_ring = memalign(sizeof(struct rx_desc_3com) * NUM_RX_DESC, 16)))
530 {
531 PRINTF ("Cannot allocate memory for RX_RING.....\n");
532 goto Done;
533 }
wdenk8bde7f72003-06-27 21:31:46 +0000534
wdenkc7de8292002-11-19 11:04:11 +0000535 if (!(tx_ring = memalign(sizeof(struct tx_desc_3com) * NUM_TX_DESC, 16)))
536 {
537 PRINTF ("Cannot allocate memory for TX_RING.....\n");
538 goto Done;
539 }
wdenk8bde7f72003-06-27 21:31:46 +0000540
wdenkc7de8292002-11-19 11:04:11 +0000541Done:
542 return status;
543}
544
545
546static int eth_3com_init(struct eth_device* dev, bd_t *bis)
547{
548 int i, status = 0;
549 int tx_cur, loop;
550 u16 status_enable, intr_enable;
551 struct descriptor *ias_cmd;
552
553 /* Determine what type of network the machine is connected to */
wdenk8bde7f72003-06-27 21:31:46 +0000554 /* presently drops the connect to 10Mbps */
wdenkc7de8292002-11-19 11:04:11 +0000555
556 if (!auto_negotiate(dev))
557 {
558 printf("Error: Cannot determine network media.\n");
559 goto Done;
560 }
561
wdenk8bde7f72003-06-27 21:31:46 +0000562 issue_and_wait(dev, TxReset);
563 issue_and_wait(dev, RxReset|0x04);
wdenkc7de8292002-11-19 11:04:11 +0000564
wdenk8bde7f72003-06-27 21:31:46 +0000565 /* Switch to register set 7 for normal use. */
566 EL3WINDOW(dev, 7);
wdenkc7de8292002-11-19 11:04:11 +0000567
568 /* Initialize Rx and Tx rings */
569
570 init_rx_ring(dev);
571 purge_tx_ring(dev);
572
wdenk8bde7f72003-06-27 21:31:46 +0000573 ETH_CMD(dev, SetRxFilter | RxStation | RxBroadcast | RxProm);
wdenkc7de8292002-11-19 11:04:11 +0000574
wdenk8bde7f72003-06-27 21:31:46 +0000575 issue_and_wait(dev,SetTxStart|0x07ff);
wdenkc7de8292002-11-19 11:04:11 +0000576
wdenk8bde7f72003-06-27 21:31:46 +0000577 /* Below sets which indication bits to be seen. */
wdenkc7de8292002-11-19 11:04:11 +0000578
wdenk8bde7f72003-06-27 21:31:46 +0000579 status_enable = SetStatusEnb | HostError | DownComplete | UpComplete | (1<<6);
580 ETH_CMD(dev, status_enable);
wdenkc7de8292002-11-19 11:04:11 +0000581
582 /* Below sets no bits are to cause an interrupt since this is just polling */
583
wdenk8bde7f72003-06-27 21:31:46 +0000584 intr_enable = SetIntrEnb;
585/* intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6); */
586 ETH_CMD(dev, intr_enable);
wdenkc7de8292002-11-19 11:04:11 +0000587 ETH_OUTB(dev, 127, UpPoll);
588
wdenk8bde7f72003-06-27 21:31:46 +0000589 /* Ack all pending events, and set active indicator mask */
wdenkc7de8292002-11-19 11:04:11 +0000590
wdenk8bde7f72003-06-27 21:31:46 +0000591 ETH_CMD(dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq);
592 ETH_CMD(dev, intr_enable);
wdenkc7de8292002-11-19 11:04:11 +0000593
594 /* Tell the adapter where the RX ring is located */
595
596 issue_and_wait(dev,UpStall); /* Stall and set the UplistPtr */
597 ETH_OUTL(dev, (u32)&rx_ring[rx_next], UpListPtr);
wdenk8bde7f72003-06-27 21:31:46 +0000598 ETH_CMD(dev, RxEnable); /* Enable the receiver. */
wdenkc7de8292002-11-19 11:04:11 +0000599 issue_and_wait(dev,UpUnstall);
600
601 /* Send the Individual Address Setup frame */
602
603 tx_cur = tx_next;
604 tx_next = ((tx_next+1) % NUM_TX_DESC);
605
606 ias_cmd = (struct descriptor *)&tx_ring[tx_cur];
607 ias_cmd->status = cpu_to_le32(1<<31); /* set DnIndicate bit. */
608 ias_cmd->next = 0;
609 ias_cmd->addr = cpu_to_le32((u32)&bis->bi_enetaddr[0]);
610 ias_cmd->length = cpu_to_le32(6 | LAST_FRAG);
611
612 /* Tell the adapter where the TX ring is located */
613
wdenk8bde7f72003-06-27 21:31:46 +0000614 ETH_CMD(dev, TxEnable); /* Enable transmitter. */
wdenkc7de8292002-11-19 11:04:11 +0000615 issue_and_wait(dev, DownStall); /* Stall and set the DownListPtr. */
616 ETH_OUTL(dev, (u32)&tx_ring[tx_cur], DownListPtr);
617 issue_and_wait(dev, DownUnstall);
618 for (i=0; !(ETH_STATUS(dev) & DownComplete); i++)
619 {
620 if (i >= TOUT_LOOP)
621 {
622 PRINTF("TX Ring status (Init): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status));
623 PRINTF("ETH_STATUS: 0x%x\n", ETH_STATUS(dev));
624 goto Done;
625 }
626 }
627 if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */
628 {
wdenk8bde7f72003-06-27 21:31:46 +0000629 ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */
630 issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */
wdenkc7de8292002-11-19 11:04:11 +0000631 ETH_OUTL(dev, 0, DownListPtr);
632 issue_and_wait(dev, DownUnstall);
633 }
634 status = 1;
wdenk8bde7f72003-06-27 21:31:46 +0000635
wdenkc7de8292002-11-19 11:04:11 +0000636Done:
637 return status;
638}
639
640int eth_3com_send(struct eth_device* dev, volatile void *packet, int length)
641{
642 int i, status = 0;
643 int tx_cur;
644
645 if (length <= 0)
646 {
647 PRINTF("eth: bad packet size: %d\n", length);
648 goto Done;
649 }
650
651 tx_cur = tx_next;
652 tx_next = (tx_next+1) % NUM_TX_DESC;
653
654 tx_ring[tx_cur].status = cpu_to_le32(1<<31); /* set DnIndicate bit */
655 tx_ring[tx_cur].next = 0;
656 tx_ring[tx_cur].addr = cpu_to_le32(((u32) packet));
657 tx_ring[tx_cur].length = cpu_to_le32(length | LAST_FRAG);
658
659 /* Send the packet */
660
661 issue_and_wait(dev, DownStall); /* stall and set the DownListPtr */
662 ETH_OUTL(dev, (u32) &tx_ring[tx_cur], DownListPtr);
663 issue_and_wait(dev, DownUnstall);
664
665 for (i=0; !(ETH_STATUS(dev) & DownComplete); i++)
666 {
667 if (i >= TOUT_LOOP)
668 {
669 PRINTF("TX Ring status (send): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status));
670 goto Done;
671 }
672 }
673 if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */
674 {
wdenk8bde7f72003-06-27 21:31:46 +0000675 ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */
676 issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */
wdenkc7de8292002-11-19 11:04:11 +0000677 ETH_OUTL(dev, 0, DownListPtr);
678 issue_and_wait(dev, DownUnstall);
679 }
680 status=1;
681 Done:
682 return status;
683}
684
685void PrintPacket (uchar *packet, int length)
686{
687int loop;
688uchar *ptr;
689
690 printf ("Printing packet of length %x.\n\n", length);
691 ptr = packet;
692 for (loop = 1; loop <= length; loop++)
693 {
694 printf ("%2x ", *ptr++);
695 if ((loop % 40)== 0)
696 printf ("\n");
697 }
698}
699
700int eth_3com_recv(struct eth_device* dev)
701{
702 u16 stat = 0;
703 u32 status;
704 int rx_prev, length = 0;
705
706 while (!(ETH_STATUS(dev) & UpComplete)) /* wait on receipt of packet */
707 ;
708
709 status = le32_to_cpu(rx_ring[rx_next].status); /* packet status */
710
711 while (status & (1<<15))
wdenk8bde7f72003-06-27 21:31:46 +0000712 {
wdenkc7de8292002-11-19 11:04:11 +0000713 /* A packet has been received */
714
wdenk8bde7f72003-06-27 21:31:46 +0000715 if (status & (1<<15))
wdenkc7de8292002-11-19 11:04:11 +0000716 {
717 /* A valid frame received */
wdenk8bde7f72003-06-27 21:31:46 +0000718
wdenkc7de8292002-11-19 11:04:11 +0000719 length = le32_to_cpu(rx_ring[rx_next].status) & 0x1fff; /* length is in bits 0 - 12 */
wdenk8bde7f72003-06-27 21:31:46 +0000720
wdenkc7de8292002-11-19 11:04:11 +0000721 /* Pass the packet up to the protocol layers */
722
723 NetReceive((uchar *)le32_to_cpu(rx_ring[rx_next].addr), length);
724 rx_ring[rx_next].status = 0; /* clear the status word */
725 ETH_CMD(dev, AckIntr | UpComplete);
726 issue_and_wait(dev, UpUnstall);
727 }
728 else
729 if (stat & HostError)
730 {
731 /* There was an error */
732
733 printf("Rx error status: 0x%4x\n", stat);
734 init_rx_ring(dev);
735 goto Done;
736 }
737
738 rx_prev = rx_next;
739 rx_next = (rx_next + 1) % NUM_RX_DESC;
740 stat = ETH_STATUS(dev); /* register status */
741 status = le32_to_cpu(rx_ring[rx_next].status); /* packet status */
742 }
743
744Done:
745 return length;
746}
747
748void eth_3com_halt(struct eth_device* dev)
749{
wdenk8bde7f72003-06-27 21:31:46 +0000750 if (!(dev->iobase))
wdenkc7de8292002-11-19 11:04:11 +0000751 {
752 goto Done;
753 }
754
755 issue_and_wait(dev, DownStall); /* shut down transmit and receive */
756 issue_and_wait(dev, UpStall);
757 issue_and_wait(dev, RxDisable);
758 issue_and_wait(dev, TxDisable);
759
wdenk8bde7f72003-06-27 21:31:46 +0000760/* free(tx_ring); /###* release memory allocated to the DPD and UPD rings */
761/* free(rx_ring); */
wdenkc7de8292002-11-19 11:04:11 +0000762
763Done:
764 return;
765}
766
wdenk8bde7f72003-06-27 21:31:46 +0000767static void init_rx_ring(struct eth_device* dev)
wdenkc7de8292002-11-19 11:04:11 +0000768{
769 int i;
770
771 PRINTF("Initializing rx_ring. rx_buffer = %p\n", rx_buffer);
772 issue_and_wait(dev, UpStall);
773
774 for (i = 0; i < NUM_RX_DESC; i++)
775 {
776 rx_ring[i].next = cpu_to_le32(((u32) &rx_ring[(i+1) % NUM_RX_DESC]));
777 rx_ring[i].status = 0;
778 rx_ring[i].addr = cpu_to_le32(((u32) &rx_buffer[i][0]));
779 rx_ring[i].length = cpu_to_le32(PKTSIZE_ALIGN | LAST_FRAG);
780 }
781 rx_next = 0;
782}
783
wdenk8bde7f72003-06-27 21:31:46 +0000784static void purge_tx_ring(struct eth_device* dev)
wdenkc7de8292002-11-19 11:04:11 +0000785{
786 int i;
787
788 PRINTF("Purging tx_ring.\n");
789
790 tx_next = 0;
791
792 for (i = 0; i < NUM_TX_DESC; i++)
793 {
794 tx_ring[i].next = 0;
795 tx_ring[i].status = 0;
796 tx_ring[i].addr = 0;
797 tx_ring[i].length = 0;
798 }
799}
800
wdenk8bde7f72003-06-27 21:31:46 +0000801static void read_hw_addr(struct eth_device* dev, bd_t *bis)
wdenkc7de8292002-11-19 11:04:11 +0000802{
803 u8 hw_addr[ETH_ALEN];
804 unsigned int eeprom[0x40];
805 unsigned int checksum = 0;
806 int i, j, timer;
807
wdenk8bde7f72003-06-27 21:31:46 +0000808 /* Read the station address from the EEPROM. */
wdenkc7de8292002-11-19 11:04:11 +0000809
wdenk8bde7f72003-06-27 21:31:46 +0000810 EL3WINDOW(dev, 0);
wdenkc7de8292002-11-19 11:04:11 +0000811 for (i = 0; i < 0x40; i++)
812 {
wdenk8bde7f72003-06-27 21:31:46 +0000813 ETH_OUTW(dev, EEPROM_Read + i, Wn0EepromCmd);
814 /* Pause for at least 162 us. for the read to take place. */
815 for (timer = 10; timer >= 0; timer--)
wdenkc7de8292002-11-19 11:04:11 +0000816 {
wdenk8bde7f72003-06-27 21:31:46 +0000817 udelay(162);
818 if ((ETH_INW(dev, Wn0EepromCmd) & 0x8000) == 0)
819 break;
820 }
821 eeprom[i] = ETH_INW(dev, Wn0EepromData);
822 }
wdenkc7de8292002-11-19 11:04:11 +0000823
824 /* Checksum calculation. I'm not sure about this part and there seems to be a bug on the 3com side of things */
825
wdenk8bde7f72003-06-27 21:31:46 +0000826 for (i = 0; i < 0x21; i++)
827 checksum ^= eeprom[i];
828 checksum = (checksum ^ (checksum >> 8)) & 0xff;
wdenkc7de8292002-11-19 11:04:11 +0000829
wdenk8bde7f72003-06-27 21:31:46 +0000830 if (checksum != 0xbb)
831 printf(" *** INVALID EEPROM CHECKSUM %4.4x *** \n", checksum);
wdenkc7de8292002-11-19 11:04:11 +0000832
wdenk8bde7f72003-06-27 21:31:46 +0000833 for (i = 0, j = 0; i < 3; i++)
wdenkc7de8292002-11-19 11:04:11 +0000834 {
835 hw_addr[j++] = (u8)((eeprom[i+10] >> 8) & 0xff);
836 hw_addr[j++] = (u8)(eeprom[i+10] & 0xff);
837 }
838
839 /* MAC Address is in window 2, write value from EEPROM to window 2 */
840
wdenk8bde7f72003-06-27 21:31:46 +0000841 EL3WINDOW(dev, 2);
842 for (i = 0; i < 6; i++)
843 ETH_OUTB(dev, hw_addr[i], i);
wdenkc7de8292002-11-19 11:04:11 +0000844
845 for (j = 0; j < ETH_ALEN; j+=2)
846 {
847 hw_addr[j] = (u8)(ETH_INW(dev, j) & 0xff);
848 hw_addr[j+1] = (u8)((ETH_INW(dev, j) >> 8) & 0xff);
849 }
850
wdenk8bde7f72003-06-27 21:31:46 +0000851 for (i=0;i<ETH_ALEN;i++)
wdenkc7de8292002-11-19 11:04:11 +0000852 {
wdenk8bde7f72003-06-27 21:31:46 +0000853 if (hw_addr[i] != bis->bi_enetaddr[i])
wdenkc7de8292002-11-19 11:04:11 +0000854 {
855/* printf("Warning: HW address don't match:\n"); */
856/* printf("Address in 3Com Window 2 is " */
857/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */
858/* hw_addr[0], hw_addr[1], hw_addr[2], */
859/* hw_addr[3], hw_addr[4], hw_addr[5]); */
860/* printf("Address used by U-Boot is " */
861/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */
862/* bis->bi_enetaddr[0], bis->bi_enetaddr[1], */
863/* bis->bi_enetaddr[2], bis->bi_enetaddr[3], */
864/* bis->bi_enetaddr[4], bis->bi_enetaddr[5]); */
865/* goto Done; */
866 char buffer[256];
867 if (bis->bi_enetaddr[0] == 0 && bis->bi_enetaddr[1] == 0 &&
868 bis->bi_enetaddr[2] == 0 && bis->bi_enetaddr[3] == 0 &&
869 bis->bi_enetaddr[4] == 0 && bis->bi_enetaddr[5] == 0)
870 {
871
wdenk8bde7f72003-06-27 21:31:46 +0000872 sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X",
873 hw_addr[0], hw_addr[1], hw_addr[2],
874 hw_addr[3], hw_addr[4], hw_addr[5]);
wdenkc7de8292002-11-19 11:04:11 +0000875 setenv("ethaddr", buffer);
876 }
877 }
878 }
879
880 for(i=0; i<ETH_ALEN; i++) dev->enetaddr[i] = hw_addr[i];
881
882Done:
883 return;
884}