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Tom Warren3f82b1d2011-01-27 10:58:05 +00001/*
2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <ns16550.h>
26#include <asm/io.h>
27#include <asm/arch/tegra2.h>
28#include <asm/arch/sys_proto.h>
29
30#include <asm/arch/clk_rst.h>
Simon Glassb4ba2be2011-08-30 06:23:13 +000031#include <asm/arch/clock.h>
Tom Warren3f82b1d2011-01-27 10:58:05 +000032#include <asm/arch/pinmux.h>
33#include <asm/arch/uart.h>
Tom Warren74652cf2011-04-14 12:18:06 +000034#include "board.h"
Tom Warren3f82b1d2011-01-27 10:58:05 +000035
Tom Warren21ef6a12011-05-31 10:30:37 +000036#ifdef CONFIG_TEGRA2_MMC
37#include <mmc.h>
38#endif
39
Tom Warren3f82b1d2011-01-27 10:58:05 +000040DECLARE_GLOBAL_DATA_PTR;
41
42const struct tegra2_sysinfo sysinfo = {
43 CONFIG_TEGRA2_BOARD_STRING
44};
45
46/*
47 * Routine: timer_init
48 * Description: init the timestamp and lastinc value
49 */
50int timer_init(void)
51{
Tom Warren3f82b1d2011-01-27 10:58:05 +000052 return 0;
53}
54
Simon Glass4ed59e72011-09-21 12:40:04 +000055static void enable_uart(enum periph_id pid)
56{
57 /* Assert UART reset and enable clock */
58 reset_set_enable(pid, 1);
59 clock_enable(pid);
60 clock_ll_set_source(pid, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
61
62 /* wait for 2us */
63 udelay(2);
64
65 /* De-assert reset to UART */
66 reset_set_enable(pid, 0);
67}
68
Tom Warren3f82b1d2011-01-27 10:58:05 +000069/*
70 * Routine: clock_init_uart
71 * Description: init the PLL and clock for the UART(s)
72 */
73static void clock_init_uart(void)
74{
Tom Warren3f82b1d2011-01-27 10:58:05 +000075#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
Simon Glass4ed59e72011-09-21 12:40:04 +000076 enable_uart(PERIPH_ID_UART1);
Tom Warren3f82b1d2011-01-27 10:58:05 +000077#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
78#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
Simon Glass4ed59e72011-09-21 12:40:04 +000079 enable_uart(PERIPH_ID_UART4);
Tom Warren3f82b1d2011-01-27 10:58:05 +000080#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
81}
82
83/*
84 * Routine: pin_mux_uart
85 * Description: setup the pin muxes/tristate values for the UART(s)
86 */
87static void pin_mux_uart(void)
88{
Tom Warren3f82b1d2011-01-27 10:58:05 +000089#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
Simon Glass20e18e02011-09-21 12:40:06 +000090 pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
91 pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
Tom Warren3f82b1d2011-01-27 10:58:05 +000092
Simon Glassc3cf49d2011-09-21 12:40:05 +000093 pinmux_tristate_disable(PINGRP_IRRX);
94 pinmux_tristate_disable(PINGRP_IRTX);
Tom Warren3f82b1d2011-01-27 10:58:05 +000095#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
96#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
Simon Glass20e18e02011-09-21 12:40:06 +000097 pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
Tom Warren3f82b1d2011-01-27 10:58:05 +000098
Simon Glassc3cf49d2011-09-21 12:40:05 +000099 pinmux_tristate_disable(PINGRP_GMC);
Tom Warren3f82b1d2011-01-27 10:58:05 +0000100#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
101}
102
Simon Glass3e00dbd2011-09-21 12:40:03 +0000103#ifdef CONFIG_TEGRA2_MMC
Tom Warren3f82b1d2011-01-27 10:58:05 +0000104/*
Tom Warren21ef6a12011-05-31 10:30:37 +0000105 * Routine: pin_mux_mmc
106 * Description: setup the pin muxes/tristate values for the SDMMC(s)
107 */
108static void pin_mux_mmc(void)
109{
Simon Glass20e18e02011-09-21 12:40:06 +0000110 /* SDMMC4: config 3, x8 on 2nd set of pins */
111 pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
112 pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
113 pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
Tom Warren21ef6a12011-05-31 10:30:37 +0000114
Simon Glassc3cf49d2011-09-21 12:40:05 +0000115 pinmux_tristate_disable(PINGRP_ATB);
116 pinmux_tristate_disable(PINGRP_GMA);
117 pinmux_tristate_disable(PINGRP_GME);
Tom Warren21ef6a12011-05-31 10:30:37 +0000118
Simon Glass20e18e02011-09-21 12:40:06 +0000119 /* SDMMC3: SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
120 pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
121 pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3);
122 pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3);
Tom Warren21ef6a12011-05-31 10:30:37 +0000123
Simon Glassc3cf49d2011-09-21 12:40:05 +0000124 pinmux_tristate_disable(PINGRP_SDC);
125 pinmux_tristate_disable(PINGRP_SDD);
126 pinmux_tristate_disable(PINGRP_SDB);
Tom Warren21ef6a12011-05-31 10:30:37 +0000127}
Simon Glass3e00dbd2011-09-21 12:40:03 +0000128#endif
Tom Warrenf4ef6662011-04-14 12:09:41 +0000129
130/*
Tom Warren3f82b1d2011-01-27 10:58:05 +0000131 * Routine: board_init
132 * Description: Early hardware init.
133 */
134int board_init(void)
135{
Simon Glass4ed59e72011-09-21 12:40:04 +0000136 clock_init();
137 clock_verify();
138
Tom Warren3f82b1d2011-01-27 10:58:05 +0000139 /* boot param addr */
140 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
Tom Warren3f82b1d2011-01-27 10:58:05 +0000141
Tom Warren3f82b1d2011-01-27 10:58:05 +0000142 return 0;
143}
Tom Warren21ef6a12011-05-31 10:30:37 +0000144
145#ifdef CONFIG_TEGRA2_MMC
146/* this is a weak define that we are overriding */
147int board_mmc_init(bd_t *bd)
148{
149 debug("board_mmc_init called\n");
Stephen Warrende71fbe2011-10-31 06:51:34 +0000150 /* Enable muxes, etc. for SDMMC controllers */
Tom Warren21ef6a12011-05-31 10:30:37 +0000151 pin_mux_mmc();
Tom Warrenccf79882011-09-21 12:40:07 +0000152 gpio_config_mmc();
Tom Warren21ef6a12011-05-31 10:30:37 +0000153
154 debug("board_mmc_init: init eMMC\n");
155 /* init dev 0, eMMC chip, with 4-bit bus */
156 tegra2_mmc_init(0, 4);
157
158 debug("board_mmc_init: init SD slot\n");
159 /* init dev 1, SD slot, with 4-bit bus */
160 tegra2_mmc_init(1, 4);
161
162 return 0;
163}
Tom Warren21ef6a12011-05-31 10:30:37 +0000164#endif
Simon Glass3e00dbd2011-09-21 12:40:03 +0000165
166#ifdef CONFIG_BOARD_EARLY_INIT_F
167int board_early_init_f(void)
168{
Simon Glass4ed59e72011-09-21 12:40:04 +0000169 /* Initialize essential common plls */
170 clock_early_init();
171
Simon Glass3e00dbd2011-09-21 12:40:03 +0000172 /* Initialize UART clocks */
173 clock_init_uart();
174
175 /* Initialize periph pinmuxes */
176 pin_mux_uart();
177
178 /* Initialize periph GPIOs */
179 gpio_config_uart();
180
181 /* Init UART, scratch regs, and start CPU */
182 tegra2_start();
183 return 0;
184}
185#endif /* EARLY_INIT */