| Andy Yan | f1a2252 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * (C) Copyright 2017 Rockchip Electronics Co., Ltd |
| 4 | */ |
| 5 | |
| 6 | #ifndef __CONFIG_RK3308_COMMON_H |
| 7 | #define __CONFIG_RK3308_COMMON_H |
| 8 | |
| 9 | #include "rockchip-common.h" |
| 10 | |
| Tom Rini | 7b5f75c | 2022-12-04 10:04:13 -0500 | [diff] [blame] | 11 | #define CFG_IRAM_BASE 0xfff80000 |
| Andy Yan | f1a2252 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 12 | |
| Tom Rini | aa6e94d | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 13 | #define CFG_SYS_SDRAM_BASE 0 |
| Andy Yan | f1a2252 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 14 | #define SDRAM_MAX_SIZE 0xff000000 |
| Andy Yan | f1a2252 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 15 | |
| Andy Yan | f1a2252 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 16 | #define ENV_MEM_LAYOUT_SETTINGS \ |
| 17 | "scriptaddr=0x00500000\0" \ |
| 18 | "pxefile_addr_r=0x00600000\0" \ |
| Andy Yan | 0abe0af | 2019-12-26 15:20:04 +0800 | [diff] [blame] | 19 | "fdt_addr_r=0x02800000\0" \ |
| Andy Yan | f1a2252 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 20 | "kernel_addr_r=0x00680000\0" \ |
| 21 | "ramdisk_addr_r=0x04000000\0" |
| 22 | |
| Tom Rini | 0613c36 | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 23 | #define CFG_EXTRA_ENV_SETTINGS \ |
| Andy Yan | f1a2252 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 24 | ENV_MEM_LAYOUT_SETTINGS \ |
| 25 | "partitions=" PARTS_DEFAULT \ |
| 26 | ROCKCHIP_DEVICE_SETTINGS \ |
| Simon Glass | 7755dc5 | 2023-04-24 13:49:51 +1200 | [diff] [blame^] | 27 | "boot_targets=" BOOT_TARGETS "\0" |
| Andy Yan | f1a2252 | 2019-11-14 11:21:12 +0800 | [diff] [blame] | 28 | |
| 29 | #endif |