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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +05302/*
3 * Copyright 2016 Freescale Semiconductor
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +05304 */
5
6#ifndef __LS1012A_COMMON_H
7#define __LS1012A_COMMON_H
8
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +05309#define CONFIG_GICV2
10
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053011#include <asm/arch/config.h>
Bharat Bhushan9f076db2017-03-22 12:06:29 +053012#include <asm/arch/stream_id_lsch2.h>
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053013
Hou Zhiqiang904110c2017-01-10 16:44:15 +080014#define CONFIG_SYS_CLK_FREQ 125000000
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053015
16#define CONFIG_SKIP_LOWLEVEL_INIT
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053017
Rajesh Bhagat1f6180d2018-11-05 18:02:53 +000018#ifdef CONFIG_TFABOOT
19#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
20#else
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053021#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
Rajesh Bhagat1f6180d2018-11-05 18:02:53 +000022#endif
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053023#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
24
25#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
26#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
27#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Prabhakar Kushwaha7d559602017-01-30 17:05:22 +053028#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053029
30/* Generic Timer Definitions */
Yuantian Tangb5845102017-10-12 14:29:26 +080031#define COUNTER_FREQUENCY 25000000 /* 25MHz */
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053032
33/* CSU */
34#define CONFIG_LAYERSCAPE_NS_ACCESS
35
36/* Size of malloc() pool */
37#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
38
39/*SPI device */
Rajesh Bhagat1f6180d2018-11-05 18:02:53 +000040#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_TFABOOT)
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053041#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053042#define CONFIG_SPI_FLASH_SPANSION
43#define CONFIG_FSL_SPI_INTERFACE
44#define CONFIG_SF_DATAFLASH
45
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053046#define QSPI0_AMBA_BASE 0x40000000
47#define CONFIG_SPI_FLASH_SPANSION
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053048
Suresh Gupta5e3f7632017-04-25 14:51:38 +053049#define FSL_QSPI_FLASH_SIZE SZ_64M
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053050#define FSL_QSPI_FLASH_NUM 2
51
52/*
53 * Environment
54 */
55#define CONFIG_ENV_OVERWRITE
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053056#endif
57
Yuantian Tangae02cf02018-01-03 15:53:10 +080058/* SATA */
59#define CONFIG_SCSI_AHCI_PLAT
60
61#define CONFIG_SYS_SATA AHCI_BASE_ADDR
62
63#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
64#define CONFIG_SYS_SCSI_MAX_LUN 1
65#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
66 CONFIG_SYS_SCSI_MAX_LUN)
67
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053068/* I2C */
Biwen Lia0affb32019-12-31 15:33:41 +080069#ifndef CONFIG_DM_I2C
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053070#define CONFIG_SYS_I2C
Biwen Lia0affb32019-12-31 15:33:41 +080071#else
72#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
73#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
74#endif
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053075
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053076#define CONFIG_SYS_NS16550_SERIAL
77#define CONFIG_SYS_NS16550_REG_SIZE 1
Hou Zhiqiang904110c2017-01-10 16:44:15 +080078#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053079
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053080#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
81
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053082#define CONFIG_SYS_HZ 1000
83
84#define CONFIG_HWCONFIG
85#define HWCONFIG_BUFFER_SIZE 128
86
Rajesh Bhagata81357a2017-11-30 16:44:38 +053087#ifndef CONFIG_SPL_BUILD
88#define BOOT_TARGET_DEVICES(func) \
89 func(MMC, mmc, 0) \
Yunfeng Dingd2c49aa2019-02-19 14:44:04 +080090 func(USB, usb, 0) \
91 func(SCSI, scsi, 0) \
92 func(DHCP, dhcp, na)
Rajesh Bhagata81357a2017-11-30 16:44:38 +053093#include <config_distro_bootcmd.h>
94#endif
95
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053096/* Initial environment variables */
97#define CONFIG_EXTRA_ENV_SETTINGS \
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053098 "verify=no\0" \
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053099 "loadaddr=0x80100000\0" \
100 "kernel_addr=0x100000\0" \
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530101 "fdt_high=0xffffffffffffffff\0" \
102 "initrd_high=0xffffffffffffffff\0" \
Bhaskar Upadhaya4def3782017-11-14 05:05:10 +0530103 "kernel_start=0x1000000\0" \
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530104 "kernel_load=0xa0000000\0" \
105 "kernel_size=0x2800000\0" \
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530106
Rajesh Bhagata81357a2017-11-30 16:44:38 +0530107#undef CONFIG_BOOTCOMMAND
Rajesh Bhagat1f6180d2018-11-05 18:02:53 +0000108#ifdef CONFIG_TFABOOT
109#define QSPI_NOR_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\
110 "$kernel_start $kernel_size && "\
111 "bootm $kernel_load"
112#else
Calvin Johnsona802d1e2018-03-08 15:30:35 +0530113#define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\
114 "$kernel_start $kernel_size && "\
115 "bootm $kernel_load"
Rajesh Bhagat1f6180d2018-11-05 18:02:53 +0000116#endif
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530117
118/* Monitor Command Prompt */
119#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530120#define CONFIG_SYS_MAXARGS 64 /* max command args */
121
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530122#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
123
Simon Glass457e51c2017-05-17 08:23:10 -0600124#include <asm/arch/soc.h>
125
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530126#endif /* __LS1012A_COMMON_H */