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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mingkai Hudd029362016-09-07 18:47:28 +08002/*
3 * Copyright 2016 Freescale Semiconductor
Mingkai Hudd029362016-09-07 18:47:28 +08004 */
5
6#ifndef __LS1046A_COMMON_H
7#define __LS1046A_COMMON_H
8
Sumit Garga52ff332017-03-30 09:53:13 +05309/* SPL build */
10#ifdef CONFIG_SPL_BUILD
11#define SPL_NO_QBMAN
12#define SPL_NO_FMAN
13#define SPL_NO_ENV
14#define SPL_NO_MISC
15#define SPL_NO_QSPI
16#define SPL_NO_USB
17#define SPL_NO_SATA
18#endif
19#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
20#define SPL_NO_MMC
21#endif
22#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
23#define SPL_NO_IFC
24#endif
25
Mingkai Hudd029362016-09-07 18:47:28 +080026#define CONFIG_REMAKE_ELF
27#define CONFIG_FSL_LAYERSCAPE
Mingkai Hudd029362016-09-07 18:47:28 +080028#define CONFIG_GICV2
29
30#include <asm/arch/config.h>
Bharat Bhushanb52a0502017-03-22 12:06:28 +053031#include <asm/arch/stream_id_lsch2.h>
Mingkai Hudd029362016-09-07 18:47:28 +080032
33/* Link Definitions */
34#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
35
Mingkai Hudd029362016-09-07 18:47:28 +080036#define CONFIG_SKIP_LOWLEVEL_INIT
Mingkai Hudd029362016-09-07 18:47:28 +080037
38#define CONFIG_VERY_BIG_RAM
39#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
40#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
41#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
42#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
43
44#define CPU_RELEASE_ADDR secondary_boot_func
45
46/* Generic Timer Definitions */
47#define COUNTER_FREQUENCY 25000000 /* 25MHz */
48
49/* Size of malloc() pool */
50#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
51
52/* Serial Port */
Mingkai Hudd029362016-09-07 18:47:28 +080053#define CONFIG_SYS_NS16550_SERIAL
54#define CONFIG_SYS_NS16550_REG_SIZE 1
Hou Zhiqiang904110c2017-01-10 16:44:15 +080055#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
Mingkai Hudd029362016-09-07 18:47:28 +080056
Mingkai Hudd029362016-09-07 18:47:28 +080057#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
58
59/* SD boot SPL */
60#ifdef CONFIG_SD_BOOT
Mingkai Hudd029362016-09-07 18:47:28 +080061#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
62#define CONFIG_SPL_LIBCOMMON_SUPPORT
63#define CONFIG_SPL_LIBGENERIC_SUPPORT
64#define CONFIG_SPL_ENV_SUPPORT
65#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
66#define CONFIG_SPL_WATCHDOG_SUPPORT
67#define CONFIG_SPL_I2C_SUPPORT
Mingkai Hudd029362016-09-07 18:47:28 +080068#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
69
70#define CONFIG_SPL_MMC_SUPPORT
Mingkai Hudd029362016-09-07 18:47:28 +080071#define CONFIG_SPL_TEXT_BASE 0x10000000
72#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
73#define CONFIG_SPL_STACK 0x10020000
74#define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
75#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
76#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
77#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
78 CONFIG_SPL_BSS_MAX_SIZE)
79#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
Ruchika Gupta511fc862017-04-17 18:07:19 +053080
81#ifdef CONFIG_SECURE_BOOT
82#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
83/*
84 * HDR would be appended at end of image and copied to DDR along
85 * with U-Boot image. Here u-boot max. size is 512K. So if binary
86 * size increases then increase this size in case of secure boot as
87 * it uses raw u-boot image instead of fit image.
88 */
89#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
90#else
91#define CONFIG_SYS_MONITOR_LEN 0x100000
92#endif /* ifdef CONFIG_SECURE_BOOT */
Mingkai Hudd029362016-09-07 18:47:28 +080093#endif
94
Shaohui Xie126fe702016-09-07 17:56:14 +080095/* NAND SPL */
96#ifdef CONFIG_NAND_BOOT
97#define CONFIG_SPL_PBL_PAD
Shaohui Xie126fe702016-09-07 17:56:14 +080098#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
99#define CONFIG_SPL_LIBCOMMON_SUPPORT
100#define CONFIG_SPL_LIBGENERIC_SUPPORT
101#define CONFIG_SPL_ENV_SUPPORT
102#define CONFIG_SPL_WATCHDOG_SUPPORT
103#define CONFIG_SPL_I2C_SUPPORT
Shaohui Xie126fe702016-09-07 17:56:14 +0800104#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
105
106#define CONFIG_SPL_NAND_SUPPORT
107#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
108#define CONFIG_SPL_TEXT_BASE 0x10000000
Ruchika Gupta511fc862017-04-17 18:07:19 +0530109#define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
Shaohui Xie126fe702016-09-07 17:56:14 +0800110#define CONFIG_SPL_STACK 0x1001f000
111#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
112#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
113
114#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
115#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
116#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
117 CONFIG_SPL_BSS_MAX_SIZE)
118#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
119#define CONFIG_SYS_MONITOR_LEN 0xa0000
120#endif
121
Mingkai Hudd029362016-09-07 18:47:28 +0800122/* I2C */
123#define CONFIG_SYS_I2C
Mingkai Hudd029362016-09-07 18:47:28 +0800124
Hou Zhiqiang3098e532017-04-14 16:49:01 +0800125/* PCIe */
126#define CONFIG_PCIE1 /* PCIE controller 1 */
127#define CONFIG_PCIE2 /* PCIE controller 2 */
128#define CONFIG_PCIE3 /* PCIE controller 3 */
129
130#ifdef CONFIG_PCI
131#define CONFIG_PCI_SCAN_SHOW
Hou Zhiqiang3098e532017-04-14 16:49:01 +0800132#endif
133
Yuantian Tangf216ef22018-01-03 15:53:09 +0800134/* SATA */
135#ifndef SPL_NO_SATA
136#define CONFIG_SCSI_AHCI_PLAT
137
138#define CONFIG_SYS_SATA AHCI_BASE_ADDR
139
140#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
141#define CONFIG_SYS_SCSI_MAX_LUN 1
142#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
143 CONFIG_SYS_SCSI_MAX_LUN)
144#endif
145
Mingkai Hudd029362016-09-07 18:47:28 +0800146/* Command line configuration */
Mingkai Hudd029362016-09-07 18:47:28 +0800147
148/* MMC */
Sumit Garga52ff332017-03-30 09:53:13 +0530149#ifndef SPL_NO_MMC
Mingkai Hudd029362016-09-07 18:47:28 +0800150#ifdef CONFIG_MMC
Mingkai Hudd029362016-09-07 18:47:28 +0800151#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Mingkai Hudd029362016-09-07 18:47:28 +0800152#endif
Sumit Garga52ff332017-03-30 09:53:13 +0530153#endif
Mingkai Hudd029362016-09-07 18:47:28 +0800154
Mingkai Hudd029362016-09-07 18:47:28 +0800155/* FMan ucode */
Sumit Garga52ff332017-03-30 09:53:13 +0530156#ifndef SPL_NO_FMAN
Mingkai Hudd029362016-09-07 18:47:28 +0800157#define CONFIG_SYS_DPAA_FMAN
158#ifdef CONFIG_SYS_DPAA_FMAN
159#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
Sumit Garga52ff332017-03-30 09:53:13 +0530160#endif
Mingkai Hudd029362016-09-07 18:47:28 +0800161
162#ifdef CONFIG_SD_BOOT
163/*
164 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
165 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
Alison Wang8104deb2017-05-16 10:45:59 +0800166 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
Mingkai Hudd029362016-09-07 18:47:28 +0800167 */
168#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Alison Wang8104deb2017-05-16 10:45:59 +0800169#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
Shaohui Xie126fe702016-09-07 17:56:14 +0800170#elif defined(CONFIG_QSPI_BOOT)
Mingkai Hudd029362016-09-07 18:47:28 +0800171#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Alison Wang8104deb2017-05-16 10:45:59 +0800172#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
Mingkai Hudd029362016-09-07 18:47:28 +0800173#define CONFIG_ENV_SPI_BUS 0
174#define CONFIG_ENV_SPI_CS 0
175#define CONFIG_ENV_SPI_MAX_HZ 1000000
176#define CONFIG_ENV_SPI_MODE 0x03
Shaohui Xie126fe702016-09-07 17:56:14 +0800177#elif defined(CONFIG_NAND_BOOT)
178#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Gong Qianyu752513d2017-09-18 16:59:28 +0800179#define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shaohui Xie126fe702016-09-07 17:56:14 +0800180#else
181#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Alison Wang8104deb2017-05-16 10:45:59 +0800182#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
Mingkai Hudd029362016-09-07 18:47:28 +0800183#endif
184#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
185#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
186#endif
187
188/* Miscellaneous configurable options */
189#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
Mingkai Hudd029362016-09-07 18:47:28 +0800190
191#define CONFIG_HWCONFIG
192#define HWCONFIG_BUFFER_SIZE 128
193
Qianyu Gong8de227e2017-06-15 11:10:09 +0800194#ifndef CONFIG_SPL_BUILD
195#define BOOT_TARGET_DEVICES(func) \
Yuantian Tangf216ef22018-01-03 15:53:09 +0800196 func(SCSI, scsi, 0) \
Qianyu Gong8de227e2017-06-15 11:10:09 +0800197 func(MMC, mmc, 0) \
198 func(USB, usb, 0)
199#include <config_distro_bootcmd.h>
200#endif
201
Sumit Garga52ff332017-03-30 09:53:13 +0530202#ifndef SPL_NO_MISC
Mingkai Hudd029362016-09-07 18:47:28 +0800203/* Initial environment variables */
204#define CONFIG_EXTRA_ENV_SETTINGS \
205 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
Mingkai Hudd029362016-09-07 18:47:28 +0800206 "ramdisk_addr=0x800000\0" \
207 "ramdisk_size=0x2000000\0" \
208 "fdt_high=0xffffffffffffffff\0" \
209 "initrd_high=0xffffffffffffffff\0" \
Qianyu Gong8de227e2017-06-15 11:10:09 +0800210 "fdt_addr=0x64f00000\0" \
211 "kernel_addr=0x65000000\0" \
212 "scriptaddr=0x80000000\0" \
Sumit Gargf7b75f82017-06-06 20:50:29 +0530213 "scripthdraddr=0x80080000\0" \
Qianyu Gong8de227e2017-06-15 11:10:09 +0800214 "fdtheader_addr_r=0x80100000\0" \
215 "kernelheader_addr_r=0x80200000\0" \
216 "load_addr=0xa0000000\0" \
Sumit Gargf7b75f82017-06-06 20:50:29 +0530217 "kernel_addr_r=0x81000000\0" \
Qianyu Gong8de227e2017-06-15 11:10:09 +0800218 "fdt_addr_r=0x90000000\0" \
219 "ramdisk_addr_r=0xa0000000\0" \
Mingkai Hudd029362016-09-07 18:47:28 +0800220 "kernel_start=0x1000000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530221 "kernelheader_start=0x800000\0" \
Mingkai Hudd029362016-09-07 18:47:28 +0800222 "kernel_load=0xa0000000\0" \
223 "kernel_size=0x2800000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530224 "kernelheader_size=0x40000\0" \
Shengzhou Liuaab2ef92017-11-09 17:57:56 +0800225 "kernel_addr_sd=0x8000\0" \
226 "kernel_size_sd=0x14000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530227 "kernelhdr_addr_sd=0x4000\0" \
228 "kernelhdr_size_sd=0x10\0" \
Mingkai Hudd029362016-09-07 18:47:28 +0800229 "console=ttyS0,115200\0" \
Tom Rini43ede0b2017-10-22 17:55:07 -0400230 CONFIG_MTDPARTS_DEFAULT "\0" \
Qianyu Gong8de227e2017-06-15 11:10:09 +0800231 BOOTENV \
232 "boot_scripts=ls1046ardb_boot.scr\0" \
Sumit Gargf7b75f82017-06-06 20:50:29 +0530233 "boot_script_hdr=hdr_ls1046ardb_bs.out\0" \
Qianyu Gong8de227e2017-06-15 11:10:09 +0800234 "scan_dev_for_boot_part=" \
235 "part list ${devtype} ${devnum} devplist; " \
236 "env exists devplist || setenv devplist 1; " \
237 "for distro_bootpart in ${devplist}; do " \
238 "if fstype ${devtype} " \
239 "${devnum}:${distro_bootpart} " \
240 "bootfstype; then " \
241 "run scan_dev_for_boot; " \
242 "fi; " \
243 "done\0" \
Sumit Gargf7b75f82017-06-06 20:50:29 +0530244 "scan_dev_for_boot=" \
245 "echo Scanning ${devtype} " \
246 "${devnum}:${distro_bootpart}...; " \
247 "for prefix in ${boot_prefixes}; do " \
248 "run scan_dev_for_scripts; " \
249 "done;" \
250 "\0" \
251 "boot_a_script=" \
252 "load ${devtype} ${devnum}:${distro_bootpart} " \
253 "${scriptaddr} ${prefix}${script}; " \
254 "env exists secureboot && load ${devtype} " \
255 "${devnum}:${distro_bootpart} " \
256 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
257 "&& esbc_validate ${scripthdraddr};" \
258 "source ${scriptaddr}\0" \
Qianyu Gong8de227e2017-06-15 11:10:09 +0800259 "qspi_bootcmd=echo Trying load from qspi..;" \
260 "sf probe && sf read $load_addr " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530261 "$kernel_start $kernel_size; env exists secureboot " \
262 "&& sf read $kernelheader_addr_r $kernelheader_start " \
263 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
264 "bootm $load_addr#$board\0" \
Shengzhou Liuaab2ef92017-11-09 17:57:56 +0800265 "sd_bootcmd=echo Trying load from SD ..;" \
266 "mmcinfo; mmc read $load_addr " \
267 "$kernel_addr_sd $kernel_size_sd && " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530268 "env exists secureboot && mmc read $kernelheader_addr_r " \
269 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
270 " && esbc_validate ${kernelheader_addr_r};" \
Shengzhou Liuaab2ef92017-11-09 17:57:56 +0800271 "bootm $load_addr#$board\0"
Qianyu Gong8de227e2017-06-15 11:10:09 +0800272
Sumit Garga52ff332017-03-30 09:53:13 +0530273#endif
274
Mingkai Hudd029362016-09-07 18:47:28 +0800275/* Monitor Command Prompt */
276#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
Sumit Garga52ff332017-03-30 09:53:13 +0530277
Mingkai Hudd029362016-09-07 18:47:28 +0800278#define CONFIG_SYS_MAXARGS 64 /* max command args */
279
280#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
281
Simon Glass457e51c2017-05-17 08:23:10 -0600282#include <asm/arch/soc.h>
283
Mingkai Hudd029362016-09-07 18:47:28 +0800284#endif /* __LS1046A_COMMON_H */