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Masahiro Yamada0b11dbf2015-07-26 02:46:26 +09001#
2# Multifunction miscellaneous devices
3#
4
5menu "Multifunction device drivers"
6
Thomas Chou4395e062015-10-07 20:20:51 +08007config MISC
8 bool "Enable Driver Model for Misc drivers"
9 depends on DM
10 help
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
14 access the device.
15
Simon Glassaaba7032018-11-18 08:14:27 -070016config SPL_MISC
17 bool "Enable Driver Model for Misc drivers in SPL"
18 depends on SPL_DM
19 help
20 Enable driver model for miscellaneous devices. This class is
21 used only for those do not fit other more general classes. A
22 set of generic read, write and ioctl methods may be used to
23 access the device.
24
25config TPL_MISC
26 bool "Enable Driver Model for Misc drivers in TPL"
27 depends on TPL_DM
28 help
29 Enable driver model for miscellaneous devices. This class is
30 used only for those do not fit other more general classes. A
31 set of generic read, write and ioctl methods may be used to
32 access the device.
33
Thomas Chouca844dd2015-10-14 08:43:31 +080034config ALTERA_SYSID
35 bool "Altera Sysid support"
36 depends on MISC
37 help
38 Select this to enable a sysid for Altera devices. Please find
39 details on the "Embedded Peripherals IP User Guide" of Altera.
40
Marek BehĂșnaa5eb9a2017-06-09 19:28:44 +020041config ATSHA204A
42 bool "Support for Atmel ATSHA204A module"
43 depends on MISC
44 help
45 Enable support for I2C connected Atmel's ATSHA204A
46 CryptoAuthentication module found for example on the Turris Omnia
47 board.
48
Philipp Tomsich49cd8e82017-05-05 19:21:38 +020049config ROCKCHIP_EFUSE
50 bool "Rockchip e-fuse support"
51 depends on MISC
52 help
53 Enable (read-only) access for the e-fuse block found in Rockchip
54 SoCs: accesses can either be made using byte addressing and a length
55 or through child-nodes that are generated based on the e-fuse map
56 retrieved from the DTS.
57
58 This driver currently supports the RK3399 only, but can easily be
59 extended (by porting the read function from the Linux kernel sources)
60 to support other recent Rockchip devices.
61
Liviu Dudau0fabfeb2018-09-28 13:43:31 +010062config VEXPRESS_CONFIG
63 bool "Enable support for Arm Versatile Express config bus"
64 depends on MISC
65 help
66 If you say Y here, you will get support for accessing the
67 configuration bus on the Arm Versatile Express boards via
68 a sysreg driver.
69
Simon Glass6fb9ac12015-02-13 12:20:47 -070070config CMD_CROS_EC
71 bool "Enable crosec command"
72 depends on CROS_EC
73 help
74 Enable command-line access to the Chrome OS EC (Embedded
75 Controller). This provides the 'crosec' command which has
76 a number of sub-commands for performing EC tasks such as
77 updating its flash, accessing a small saved context area
78 and talking to the I2C bus behind the EC (if there is one).
79
80config CROS_EC
81 bool "Enable Chrome OS EC"
82 help
83 Enable access to the Chrome OS EC. This is a separate
84 microcontroller typically available on a SPI bus on Chromebooks. It
85 provides access to the keyboard, some internal storage and may
86 control access to the battery and main PMIC depending on the
87 device. You can use the 'crosec' command to access it.
88
Simon Glassaaba7032018-11-18 08:14:27 -070089config SPL_CROS_EC
90 bool "Enable Chrome OS EC in SPL"
91 help
92 Enable access to the Chrome OS EC in SPL. This is a separate
93 microcontroller typically available on a SPI bus on Chromebooks. It
94 provides access to the keyboard, some internal storage and may
95 control access to the battery and main PMIC depending on the
96 device. You can use the 'crosec' command to access it.
97
98config TPL_CROS_EC
99 bool "Enable Chrome OS EC in TPL"
100 help
101 Enable access to the Chrome OS EC in TPL. This is a separate
102 microcontroller typically available on a SPI bus on Chromebooks. It
103 provides access to the keyboard, some internal storage and may
104 control access to the battery and main PMIC depending on the
105 device. You can use the 'crosec' command to access it.
106
Simon Glass6fb9ac12015-02-13 12:20:47 -0700107config CROS_EC_I2C
108 bool "Enable Chrome OS EC I2C driver"
109 depends on CROS_EC
110 help
111 Enable I2C access to the Chrome OS EC. This is used on older
112 ARM Chromebooks such as snow and spring before the standard bus
113 changed to SPI. The EC will accept commands across the I2C using
114 a special message protocol, and provide responses.
115
116config CROS_EC_LPC
117 bool "Enable Chrome OS EC LPC driver"
118 depends on CROS_EC
119 help
120 Enable I2C access to the Chrome OS EC. This is used on x86
121 Chromebooks such as link and falco. The keyboard is provided
122 through a legacy port interface, so on x86 machines the main
123 function of the EC is power and thermal management.
124
Simon Glassaaba7032018-11-18 08:14:27 -0700125config SPL_CROS_EC_LPC
126 bool "Enable Chrome OS EC LPC driver in SPL"
127 depends on CROS_EC
128 help
129 Enable I2C access to the Chrome OS EC. This is used on x86
130 Chromebooks such as link and falco. The keyboard is provided
131 through a legacy port interface, so on x86 machines the main
132 function of the EC is power and thermal management.
133
134config TPL_CROS_EC_LPC
135 bool "Enable Chrome OS EC LPC driver in TPL"
136 depends on CROS_EC
137 help
138 Enable I2C access to the Chrome OS EC. This is used on x86
139 Chromebooks such as link and falco. The keyboard is provided
140 through a legacy port interface, so on x86 machines the main
141 function of the EC is power and thermal management.
142
Simon Glass47cb8c62015-03-26 09:29:40 -0600143config CROS_EC_SANDBOX
144 bool "Enable Chrome OS EC sandbox driver"
145 depends on CROS_EC && SANDBOX
146 help
147 Enable a sandbox emulation of the Chrome OS EC. This supports
148 keyboard (use the -l flag to enable the LCD), verified boot context,
149 EC flash read/write/erase support and a few other things. It is
150 enough to perform a Chrome OS verified boot on sandbox.
151
Simon Glassaaba7032018-11-18 08:14:27 -0700152config SPL_CROS_EC_SANDBOX
153 bool "Enable Chrome OS EC sandbox driver in SPL"
154 depends on SPL_CROS_EC && SANDBOX
155 help
156 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
157 keyboard (use the -l flag to enable the LCD), verified boot context,
158 EC flash read/write/erase support and a few other things. It is
159 enough to perform a Chrome OS verified boot on sandbox.
160
161config TPL_CROS_EC_SANDBOX
162 bool "Enable Chrome OS EC sandbox driver in TPL"
163 depends on TPL_CROS_EC && SANDBOX
164 help
165 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
166 keyboard (use the -l flag to enable the LCD), verified boot context,
167 EC flash read/write/erase support and a few other things. It is
168 enough to perform a Chrome OS verified boot on sandbox.
169
Simon Glass6fb9ac12015-02-13 12:20:47 -0700170config CROS_EC_SPI
171 bool "Enable Chrome OS EC SPI driver"
172 depends on CROS_EC
173 help
174 Enable SPI access to the Chrome OS EC. This is used on newer
175 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
176 provides a faster and more robust interface than I2C but the bugs
177 are less interesting.
178
Simon Glass879704d2017-05-17 03:25:02 -0600179config DS4510
180 bool "Enable support for DS4510 CPU supervisor"
181 help
182 Enable support for the Maxim DS4510 CPU supervisor. It has an
183 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
184 and a configurable timer for the supervisor function. The device is
185 connected over I2C.
186
Peng Fanc12e0d92015-08-26 15:41:33 +0800187config FSL_SEC_MON
gaurav ranafe783782015-02-27 09:44:22 +0530188 bool "Enable FSL SEC_MON Driver"
189 help
190 Freescale Security Monitor block is responsible for monitoring
191 system states.
192 Security Monitor can be transitioned on any security failures,
193 like software violations or hardware security violations.
Stefan Roese1cdd9412015-03-12 11:22:46 +0100194
Paul Burtonb5392c52018-12-16 19:25:19 -0300195config JZ4780_EFUSE
196 bool "Ingenic JZ4780 eFUSE support"
197 depends on ARCH_JZ47XX
198 help
199 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
200
Peng Fan3e020f02015-08-27 14:49:05 +0800201config MXC_OCOTP
202 bool "Enable MXC OCOTP Driver"
Marcel Ziswiler0a6f6252019-03-25 17:24:57 +0100203 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_VF610
204 default y
Peng Fan3e020f02015-08-27 14:49:05 +0800205 help
206 If you say Y here, you will get support for the One Time
207 Programmable memory pages that are stored on the some
208 Freescale i.MX processors.
209
Stefan Roese4cf9e462016-07-19 07:45:46 +0200210config NUVOTON_NCT6102D
211 bool "Enable Nuvoton NCT6102D Super I/O driver"
212 help
213 If you say Y here, you will get support for the Nuvoton
214 NCT6102D Super I/O driver. This can be used to enable or
215 disable the legacy UART, the watchdog or other devices
216 in the Nuvoton Super IO chips on X86 platforms.
217
Simon Glass5fd6bad2016-01-21 19:43:31 -0700218config PWRSEQ
219 bool "Enable power-sequencing drivers"
220 depends on DM
221 help
222 Power-sequencing drivers provide support for controlling power for
223 devices. They are typically referenced by a phandle from another
224 device. When the device is started up, its power sequence can be
225 initiated.
226
227config SPL_PWRSEQ
228 bool "Enable power-sequencing drivers for SPL"
229 depends on PWRSEQ
230 help
231 Power-sequencing drivers provide support for controlling power for
232 devices. They are typically referenced by a phandle from another
233 device. When the device is started up, its power sequence can be
234 initiated.
235
Stefan Roese1cdd9412015-03-12 11:22:46 +0100236config PCA9551_LED
237 bool "Enable PCA9551 LED driver"
238 help
239 Enable driver for PCA9551 LED controller. This controller
240 is connected via I2C. So I2C needs to be enabled.
241
242config PCA9551_I2C_ADDR
243 hex "I2C address of PCA9551 LED controller"
244 depends on PCA9551_LED
245 default 0x60
246 help
247 The I2C address of the PCA9551 LED controller.
Simon Glassf9917452015-06-23 15:39:13 -0600248
Patrick Delaunayc3600e12018-05-17 15:24:06 +0200249config STM32MP_FUSE
250 bool "Enable STM32MP fuse wrapper providing the fuse API"
251 depends on ARCH_STM32MP && MISC
252 default y if CMD_FUSE
253 help
254 If you say Y here, you will get support for the fuse API (OTP)
255 for STM32MP architecture.
256 This API is needed for CMD_FUSE.
257
Christophe Kerello4e280b92017-09-13 18:00:08 +0200258config STM32_RCC
259 bool "Enable RCC driver for the STM32 SoC's family"
Patrick Delaunayd090cba2018-07-09 15:17:20 +0200260 depends on (STM32 || ARCH_STM32MP) && MISC
Christophe Kerello4e280b92017-09-13 18:00:08 +0200261 help
262 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
263 block) is responsible of the management of the clock and reset
264 generation.
265 This driver is similar to an MFD driver in the Linux kernel.
266
Stephen Warrenbd3ee842016-09-13 10:45:57 -0600267config TEGRA_CAR
268 bool "Enable support for the Tegra CAR driver"
269 depends on TEGRA_NO_BPMP
270 help
271 The Tegra CAR (Clock and Reset Controller) is a HW module that
272 controls almost all clocks and resets in a Tegra SoC.
273
Stephen Warren73dd5c42016-08-08 09:41:34 -0600274config TEGRA186_BPMP
275 bool "Enable support for the Tegra186 BPMP driver"
276 depends on TEGRA186
277 help
278 The Tegra BPMP (Boot and Power Management Processor) is a separate
279 auxiliary CPU embedded into Tegra to perform power management work,
280 and controls related features such as clocks, resets, power domains,
281 PMIC I2C bus, etc. This driver provides the core low-level
282 communication path by which feature-specific drivers (such as clock)
283 can make requests to the BPMP. This driver is similar to an MFD
284 driver in the Linux kernel.
285
Adam Fordcc3fedb2018-08-06 14:26:50 -0500286config TWL4030_LED
287 bool "Enable TWL4030 LED controller"
288 help
289 Enable this to add support for the TWL4030 LED controller.
290
Stefan Roese85056932016-01-19 14:05:10 +0100291config WINBOND_W83627
292 bool "Enable Winbond Super I/O driver"
293 help
294 If you say Y here, you will get support for the Winbond
295 W83627 Super I/O driver. This can be used to enable the
296 legacy UART or other devices in the Winbond Super IO chips
297 on X86 platforms.
298
Miao Yanfcf5c042016-05-22 19:37:14 -0700299config QFW
300 bool
301 help
302 Hidden option to enable QEMU fw_cfg interface. This will be selected by
Miao Yan18686592016-05-22 19:37:17 -0700303 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
Miao Yanfcf5c042016-05-22 19:37:14 -0700304
mario.six@gdsys.ccd7e28912016-06-22 15:14:16 +0200305config I2C_EEPROM
306 bool "Enable driver for generic I2C-attached EEPROMs"
307 depends on MISC
308 help
309 Enable a generic driver for EEPROMs attached via I2C.
Adam Forde3f24d42017-08-13 09:00:28 -0500310
Wenyou Yangd81a1de2017-09-06 13:08:14 +0800311
312config SPL_I2C_EEPROM
313 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
314 depends on MISC && SPL && SPL_DM
315 help
316 This option is an SPL-variant of the I2C_EEPROM option.
317 See the help of I2C_EEPROM for details.
318
Vipul Kumar5c32de22018-02-16 19:07:21 +0530319config ZYNQ_GEM_I2C_MAC_OFFSET
320 hex "Set the I2C MAC offset"
321 default 0x0
Michal Simek027b1132019-01-22 15:55:46 +0100322 depends on DM_I2C
Vipul Kumar5c32de22018-02-16 19:07:21 +0530323 help
324 Set the MAC offset for i2C.
325
Adam Forde3f24d42017-08-13 09:00:28 -0500326if I2C_EEPROM
327
328config SYS_I2C_EEPROM_ADDR
329 hex "Chip address of the EEPROM device"
330 default 0
331
332config SYS_I2C_EEPROM_BUS
333 int "I2C bus of the EEPROM device."
334 default 0
335
336config SYS_EEPROM_SIZE
337 int "Size in bytes of the EEPROM device"
338 default 256
339
340config SYS_EEPROM_PAGE_WRITE_BITS
341 int "Number of bits used to address bytes in a single page"
342 default 0
343 help
344 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
345 A 64 byte page, for example would require six bits.
346
347config SYS_EEPROM_PAGE_WRITE_DELAY_MS
348 int "Number of milliseconds to delay between page writes"
349 default 0
350
351config SYS_I2C_EEPROM_ADDR_LEN
352 int "Length in bytes of the EEPROM memory array address"
353 default 1
354 help
355 Note: This is NOT the chip address length!
356
357config SYS_I2C_EEPROM_ADDR_OVERFLOW
358 hex "EEPROM Address Overflow"
359 default 0
360 help
361 EEPROM chips that implement "address overflow" are ones
362 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
363 address and the extra bits end up in the "chip address" bit
364 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
365 byte chips.
366
367endif
368
Mario Six86da8c12018-04-27 14:53:33 +0200369config GDSYS_RXAUI_CTRL
370 bool "Enable gdsys RXAUI control driver"
371 depends on MISC
372 help
373 Support gdsys FPGA's RXAUI control.
Mario Six7e862422018-07-31 14:24:15 +0200374
375config GDSYS_IOEP
376 bool "Enable gdsys IOEP driver"
377 depends on MISC
378 help
379 Support gdsys FPGA's IO endpoint driver.
Mario Sixd2166312018-08-06 10:23:46 +0200380
381config MPC83XX_SERDES
382 bool "Enable MPC83xx serdes driver"
383 depends on MISC
384 help
385 Support for serdes found on MPC83xx SoCs.
386
Tien Fong Chee62030002018-07-06 16:28:03 +0800387config FS_LOADER
388 bool "Enable loader driver for file system"
389 help
390 This is file system generic loader which can be used to load
391 the file image from the storage into target such as memory.
392
393 The consumer driver would then use this loader to program whatever,
394 ie. the FPGA device.
395
Mario Sixc0a2b082018-10-04 09:00:54 +0200396config GDSYS_SOC
397 bool "Enable gdsys SOC driver"
398 depends on MISC
399 help
400 Support for gdsys IHS SOC, a simple bus associated with each gdsys
401 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
402 register maps are contained within the FPGA's register map.
403
Mario Sixab88bd22018-10-04 09:00:55 +0200404config IHS_FPGA
405 bool "Enable IHS FPGA driver"
406 depends on MISC
407 help
408 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
409 gdsys devices, which supply the majority of the functionality offered
410 by the devices. This driver supports both CON and CPU variants of the
411 devices, depending on the device tree entry.
412
Masahiro Yamada0b11dbf2015-07-26 02:46:26 +0900413endmenu