blob: fad0bdb56c4a7ec6e7088cc1bc0843d8233acb21 [file] [log] [blame]
Kim Phillips1c274c42007-07-25 19:25:33 -05001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published
6 * by the Free Software Foundation.
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Kim Phillips1c274c42007-07-25 19:25:33 -050012/*
13 * High Level Configuration Options
14 */
15#define CONFIG_E300 1 /* E300 family */
16#define CONFIG_QE 1 /* Has QE */
Peter Tyser2c7920a2009-05-22 17:23:25 -050017#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
Kim Phillips1c274c42007-07-25 19:25:33 -050018
Kim Phillips1c274c42007-07-25 19:25:33 -050019/*
20 * System Clock Setup
21 */
22#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
23
24#ifndef CONFIG_SYS_CLK_FREQ
25#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
26#endif
27
28/*
29 * Hardware Reset Configuration Word
30 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020031#define CONFIG_SYS_HRCW_LOW (\
Kim Phillips1c274c42007-07-25 19:25:33 -050032 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
33 HRCWL_DDR_TO_SCB_CLK_2X1 |\
34 HRCWL_VCO_1X2 |\
35 HRCWL_CSB_TO_CLKIN_2X1 |\
36 HRCWL_CORE_TO_CSB_2_5X1 |\
37 HRCWL_CE_PLL_VCO_DIV_2 |\
38 HRCWL_CE_PLL_DIV_1X1 |\
39 HRCWL_CE_TO_PLL_1X3)
40
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_HRCW_HIGH (\
Kim Phillips1c274c42007-07-25 19:25:33 -050042 HRCWH_PCI_HOST |\
43 HRCWH_PCI1_ARBITER_ENABLE |\
44 HRCWH_CORE_ENABLE |\
45 HRCWH_FROM_0X00000100 |\
46 HRCWH_BOOTSEQ_DISABLE |\
47 HRCWH_SW_WATCHDOG_DISABLE |\
48 HRCWH_ROM_LOC_LOCAL_16BIT |\
49 HRCWH_BIG_ENDIAN |\
50 HRCWH_LALE_NORMAL)
51
52/*
53 * System IO Config
54 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_SICRL 0x00000000
Kim Phillips1c274c42007-07-25 19:25:33 -050056
Kim Phillips1c274c42007-07-25 19:25:33 -050057/*
58 * IMMR new address
59 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_IMMR 0xE0000000
Kim Phillips1c274c42007-07-25 19:25:33 -050061
62/*
Michael Barkowski5bbeea82008-03-20 13:15:34 -040063 * System performance
64 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
Joe Hershberger4dde49d2011-10-11 23:57:12 -050066#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
67/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
68#define CONFIG_SYS_SPCR_OPT 1
Michael Barkowski5bbeea82008-03-20 13:15:34 -040069
70/*
Kim Phillips1c274c42007-07-25 19:25:33 -050071 * DDR Setup
72 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -050073#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
74#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Kim Phillips1c274c42007-07-25 19:25:33 -050076
77#undef CONFIG_SPD_EEPROM
78#if defined(CONFIG_SPD_EEPROM)
79/* Determine DDR configuration from I2C interface
80 */
81#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
82#else
83/* Manually set up DDR parameters
84 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -050085#define CONFIG_SYS_DDR_SIZE 64 /* MB */
86#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger4dde49d2011-10-11 23:57:12 -050087 | CSCONFIG_ROW_BIT_13 \
88 | CSCONFIG_COL_BIT_9)
Michael Barkowski5bbeea82008-03-20 13:15:34 -040089 /* 0x80010101 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -050090#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
91 | (0 << TIMING_CFG0_WRT_SHIFT) \
92 | (0 << TIMING_CFG0_RRT_SHIFT) \
93 | (0 << TIMING_CFG0_WWT_SHIFT) \
94 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
95 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
96 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
97 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Michael Barkowskifc549c82008-03-20 13:15:28 -040098 /* 0x00220802 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -050099#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
100 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
101 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
102 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
103 | (3 << TIMING_CFG1_REFREC_SHIFT) \
104 | (2 << TIMING_CFG1_WRREC_SHIFT) \
105 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
106 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400107 /* 0x26253222 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500108#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
109 | (31 << TIMING_CFG2_CPO_SHIFT) \
110 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
111 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
112 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
113 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
114 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400115 /* 0x1f9048c7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_DDR_TIMING_3 0x00000000
117#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
Michael Barkowskifc549c82008-03-20 13:15:28 -0400118 /* 0x02000000 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500119#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
120 | (0x0232 << SDRAM_MODE_SD_SHIFT))
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400121 /* 0x44480232 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500122#define CONFIG_SYS_DDR_MODE2 0x8000c000
123#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
124 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Michael Barkowskifc549c82008-03-20 13:15:28 -0400125 /* 0x03200064 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500127#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
Michael Barkowskifc549c82008-03-20 13:15:28 -0400128 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500129 | SDRAM_CFG_32_BE)
Michael Barkowskifc549c82008-03-20 13:15:28 -0400130 /* 0x43080000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
Kim Phillips1c274c42007-07-25 19:25:33 -0500132#endif
133
134/*
135 * Memory test
136 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
138#define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
139#define CONFIG_SYS_MEMTEST_END 0x03f00000
Kim Phillips1c274c42007-07-25 19:25:33 -0500140
141/*
142 * The reserved memory
143 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200144#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Kim Phillips1c274c42007-07-25 19:25:33 -0500145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
147#define CONFIG_SYS_RAMBOOT
Kim Phillips1c274c42007-07-25 19:25:33 -0500148#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#undef CONFIG_SYS_RAMBOOT
Kim Phillips1c274c42007-07-25 19:25:33 -0500150#endif
151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Kevin Hao16c8c172016-07-08 11:25:14 +0800153#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
Kim Phillipsc8a90642012-06-30 18:29:20 -0500154#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
Kim Phillips1c274c42007-07-25 19:25:33 -0500155
156/*
157 * Initial RAM Base Address Setup
158 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_INIT_RAM_LOCK 1
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500160#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
161#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
162#define CONFIG_SYS_GBL_DATA_OFFSET \
163 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Kim Phillips1c274c42007-07-25 19:25:33 -0500164
165/*
166 * Local Bus Configuration & Clock Setup
167 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500168#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
169#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_LBC_LBCR 0x00000000
Kim Phillips1c274c42007-07-25 19:25:33 -0500171
172/*
173 * FLASH on the Local Bus
174 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200176#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500177#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500179#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Kim Phillips1c274c42007-07-25 19:25:33 -0500180
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500181 /* Window base at flash base */
182#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500183#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
Kim Phillips1c274c42007-07-25 19:25:33 -0500184
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500185#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500186 | BR_PS_16 /* 16 bit port */ \
187 | BR_MS_GPCM /* MSEL = GPCM */ \
188 | BR_V) /* valid */
189#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
190 | OR_GPCM_XAM \
191 | OR_GPCM_CSNT \
192 | OR_GPCM_ACS_DIV2 \
193 | OR_GPCM_XACS \
194 | OR_GPCM_SCY_15 \
195 | OR_GPCM_TRLX_SET \
196 | OR_GPCM_EHTR_SET \
197 | OR_GPCM_EAD)
198 /* 0xFE006FF7 */
Kim Phillips1c274c42007-07-25 19:25:33 -0500199
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500200#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
201#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
Kim Phillips1c274c42007-07-25 19:25:33 -0500202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#undef CONFIG_SYS_FLASH_CHECKSUM
Kim Phillips1c274c42007-07-25 19:25:33 -0500204
205/*
Kim Phillips1c274c42007-07-25 19:25:33 -0500206 * Serial Port
207 */
208#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_NS16550_SERIAL
210#define CONFIG_SYS_NS16550_REG_SIZE 1
211#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kim Phillips1c274c42007-07-25 19:25:33 -0500212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500214 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Kim Phillips1c274c42007-07-25 19:25:33 -0500215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
217#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Kim Phillips1c274c42007-07-25 19:25:33 -0500218
219#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500220#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Kim Phillips1c274c42007-07-25 19:25:33 -0500221
Kim Phillips1c274c42007-07-25 19:25:33 -0500222/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200223#define CONFIG_SYS_I2C
224#define CONFIG_SYS_I2C_FSL
225#define CONFIG_SYS_FSL_I2C_SPEED 400000
226#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
227#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
228#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
Kim Phillips1c274c42007-07-25 19:25:33 -0500229
230/*
Michael Barkowski0fa7a1b2008-03-20 13:15:39 -0400231 * Config on-board EEPROM
Kim Phillips1c274c42007-07-25 19:25:33 -0500232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
234#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
235#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
236#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Kim Phillips1c274c42007-07-25 19:25:33 -0500237
238/*
239 * General PCI
240 * Addresses are mapped 1-1.
241 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
243#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
244#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
245#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
246#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
247#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
248#define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
249#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
250#define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
Kim Phillips1c274c42007-07-25 19:25:33 -0500251
252#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000253#define CONFIG_PCI_INDIRECT_BRIDGE
Michael Barkowski8f325cf2008-03-28 15:15:38 -0400254#define CONFIG_PCI_SKIP_HOST_BRIDGE
Kim Phillips1c274c42007-07-25 19:25:33 -0500255
256#undef CONFIG_EEPRO100
257#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Kim Phillips1c274c42007-07-25 19:25:33 -0500259
260#endif /* CONFIG_PCI */
261
Kim Phillips1c274c42007-07-25 19:25:33 -0500262/*
263 * QE UEC ethernet configuration
264 */
265#define CONFIG_UEC_ETH
Kim Phillips78b7a8e2010-07-26 18:34:57 -0500266#define CONFIG_ETHPRIME "UEC0"
Kim Phillips1c274c42007-07-25 19:25:33 -0500267
268#define CONFIG_UEC_ETH1 /* ETH3 */
269
270#ifdef CONFIG_UEC_ETH1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
272#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
273#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
274#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
275#define CONFIG_SYS_UEC1_PHY_ADDR 4
Andy Fleming865ff852011-04-13 00:37:12 -0500276#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100277#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
Kim Phillips1c274c42007-07-25 19:25:33 -0500278#endif
279
280#define CONFIG_UEC_ETH2 /* ETH4 */
281
282#ifdef CONFIG_UEC_ETH2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
284#define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
285#define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
286#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
287#define CONFIG_SYS_UEC2_PHY_ADDR 0
Andy Fleming865ff852011-04-13 00:37:12 -0500288#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100289#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
Kim Phillips1c274c42007-07-25 19:25:33 -0500290#endif
291
292/*
293 * Environment
294 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#ifndef CONFIG_SYS_RAMBOOT
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500296 #define CONFIG_ENV_ADDR \
297 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200298 #define CONFIG_ENV_SECT_SIZE 0x20000
299 #define CONFIG_ENV_SIZE 0x2000
Kim Phillips1c274c42007-07-25 19:25:33 -0500300#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200302 #define CONFIG_ENV_SIZE 0x2000
Kim Phillips1c274c42007-07-25 19:25:33 -0500303#endif
304
305#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kim Phillips1c274c42007-07-25 19:25:33 -0500307
308/*
309 * BOOTP options
310 */
311#define CONFIG_BOOTP_BOOTFILESIZE
312#define CONFIG_BOOTP_BOOTPATH
313#define CONFIG_BOOTP_GATEWAY
314#define CONFIG_BOOTP_HOSTNAME
315
316/*
317 * Command line configuration.
318 */
Kim Phillips1c274c42007-07-25 19:25:33 -0500319
Kim Phillips1c274c42007-07-25 19:25:33 -0500320#undef CONFIG_WATCHDOG /* watchdog disabled */
321
322/*
323 * Miscellaneous configurable options
324 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500325#define CONFIG_SYS_LONGHELP /* undef to save memory */
326#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kim Phillips1c274c42007-07-25 19:25:33 -0500327
Kim Phillips1c274c42007-07-25 19:25:33 -0500328/*
329 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700330 * have to be in the first 256 MB of memory, since this is
Kim Phillips1c274c42007-07-25 19:25:33 -0500331 * the maximum mapped by the Linux kernel during initialization.
332 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500333 /* Initial Memory map for Linux */
334#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Kevin Hao63865272016-07-08 11:25:15 +0800335#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kim Phillips1c274c42007-07-25 19:25:33 -0500336
337/*
338 * Core HID Setup
339 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500340#define CONFIG_SYS_HID0_INIT 0x000000000
341#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
342 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_HID2 HID2_HBE
Kim Phillips1c274c42007-07-25 19:25:33 -0500344
345/*
Kim Phillips1c274c42007-07-25 19:25:33 -0500346 * MMU Setup
347 */
Becky Bruce31d82672008-05-08 19:02:12 -0500348#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Kim Phillips1c274c42007-07-25 19:25:33 -0500349
350/* DDR: cache cacheable */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500351#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500352 | BATL_PP_RW \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500353 | BATL_MEMCOHERENCE)
354#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
355 | BATU_BL_256M \
356 | BATU_VS \
357 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
359#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Kim Phillips1c274c42007-07-25 19:25:33 -0500360
361/* IMMRBAR & PCI IO: cache-inhibit and guarded */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500362#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500363 | BATL_PP_RW \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500364 | BATL_CACHEINHIBIT \
365 | BATL_GUARDEDSTORAGE)
366#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
367 | BATU_BL_4M \
368 | BATU_VS \
369 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
371#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Kim Phillips1c274c42007-07-25 19:25:33 -0500372
373/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500374#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500375 | BATL_PP_RW \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500376 | BATL_MEMCOHERENCE)
377#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
378 | BATU_BL_32M \
379 | BATU_VS \
380 | BATU_VP)
381#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500382 | BATL_PP_RW \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500383 | BATL_CACHEINHIBIT \
384 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Kim Phillips1c274c42007-07-25 19:25:33 -0500386
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_IBAT3L (0)
388#define CONFIG_SYS_IBAT3U (0)
389#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
390#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Kim Phillips1c274c42007-07-25 19:25:33 -0500391
392/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500393#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500394#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
395 | BATU_BL_128K \
396 | BATU_VS \
397 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
399#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Kim Phillips1c274c42007-07-25 19:25:33 -0500400
401#ifdef CONFIG_PCI
402/* PCI MEM space: cacheable */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500403#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500404 | BATL_PP_RW \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500405 | BATL_MEMCOHERENCE)
406#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \
407 | BATU_BL_256M \
408 | BATU_VS \
409 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
411#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Kim Phillips1c274c42007-07-25 19:25:33 -0500412/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500413#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500414 | BATL_PP_RW \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500415 | BATL_CACHEINHIBIT \
416 | BATL_GUARDEDSTORAGE)
417#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \
418 | BATU_BL_256M \
419 | BATU_VS \
420 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
422#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Kim Phillips1c274c42007-07-25 19:25:33 -0500423#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_IBAT5L (0)
425#define CONFIG_SYS_IBAT5U (0)
426#define CONFIG_SYS_IBAT6L (0)
427#define CONFIG_SYS_IBAT6U (0)
428#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
429#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
430#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
431#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Kim Phillips1c274c42007-07-25 19:25:33 -0500432#endif
433
434/* Nothing in BAT7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_IBAT7L (0)
436#define CONFIG_SYS_IBAT7U (0)
437#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
438#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Kim Phillips1c274c42007-07-25 19:25:33 -0500439
Kim Phillips1c274c42007-07-25 19:25:33 -0500440#if (CONFIG_CMD_KGDB)
441#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Kim Phillips1c274c42007-07-25 19:25:33 -0500442#endif
443
444/*
445 * Environment Configuration
446 */
447#define CONFIG_ENV_OVERWRITE
448
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500449#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
450#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
Kim Phillips1c274c42007-07-25 19:25:33 -0500451
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500452/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
453 * (see CONFIG_SYS_I2C_EEPROM) */
454 /* MAC address offset in I2C EEPROM */
455#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
Michael Barkowski5b2793a2008-03-27 14:34:43 -0400456
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500457#define CONFIG_NETDEV "eth1"
Kim Phillips1c274c42007-07-25 19:25:33 -0500458
459#define CONFIG_HOSTNAME mpc8323erdb
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000460#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000461#define CONFIG_BOOTFILE "uImage"
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500462 /* U-Boot image on TFTP server */
463#define CONFIG_UBOOTPATH "u-boot.bin"
464#define CONFIG_FDTFILE "mpc832x_rdb.dtb"
465#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
Kim Phillips1c274c42007-07-25 19:25:33 -0500466
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500467 /* default location for tftp and bootm */
468#define CONFIG_LOADADDR 800000
Kim Phillips1c274c42007-07-25 19:25:33 -0500469
Kim Phillips1c274c42007-07-25 19:25:33 -0500470#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500471 "netdev=" CONFIG_NETDEV "\0" \
472 "uboot=" CONFIG_UBOOTPATH "\0" \
Kim Phillips1c274c42007-07-25 19:25:33 -0500473 "tftpflash=tftp $loadaddr $uboot;" \
Marek Vasut5368c552012-09-23 17:41:24 +0200474 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
475 " +$filesize; " \
476 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
477 " +$filesize; " \
478 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
479 " $filesize; " \
480 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
481 " +$filesize; " \
482 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
483 " $filesize\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500484 "fdtaddr=780000\0" \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500485 "fdtfile=" CONFIG_FDTFILE "\0" \
Kim Phillips1c274c42007-07-25 19:25:33 -0500486 "ramdiskaddr=1000000\0" \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500487 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
Kim Phillips1c274c42007-07-25 19:25:33 -0500488 "console=ttyS0\0" \
489 "setbootargs=setenv bootargs " \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500490 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
Kim Phillips1c274c42007-07-25 19:25:33 -0500491 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500492 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
493 "$netdev:off "\
Kim Phillips1c274c42007-07-25 19:25:33 -0500494 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
495
496#define CONFIG_NFSBOOTCOMMAND \
497 "setenv rootdev /dev/nfs;" \
498 "run setbootargs;" \
499 "run setipargs;" \
500 "tftp $loadaddr $bootfile;" \
501 "tftp $fdtaddr $fdtfile;" \
502 "bootm $loadaddr - $fdtaddr"
503
504#define CONFIG_RAMBOOTCOMMAND \
505 "setenv rootdev /dev/ram;" \
506 "run setbootargs;" \
507 "tftp $ramdiskaddr $ramdiskfile;" \
508 "tftp $loadaddr $bootfile;" \
509 "tftp $fdtaddr $fdtfile;" \
510 "bootm $loadaddr $ramdiskaddr $fdtaddr"
511
Kim Phillips1c274c42007-07-25 19:25:33 -0500512#endif /* __CONFIG_H */