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Bo Shen7ca6f362014-02-09 15:52:39 +08001/*
2 * Configuration settings for the SAMA5D3 Xplained board.
3 *
4 * Copyright (C) 2014 Atmel Corporation
5 * Bo Shen <voice.shen@atmel.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Wu, Joshb2d387b2015-03-30 14:51:19 +080013#include "at91-sama5_common.h"
Bo Shen7ca6f362014-02-09 15:52:39 +080014
Bo Shen7ca6f362014-02-09 15:52:39 +080015/*
16 * This needs to be defined for the OHCI code to work but it is defined as
17 * ATMEL_ID_UHPHS in the CPU specific header files.
18 */
Wenyou Yange61ed482017-09-14 11:07:42 +080019#define ATMEL_ID_UHP 32
Bo Shen7ca6f362014-02-09 15:52:39 +080020
21/*
22 * Specify the clock enable bit in the PMC_SCER register.
23 */
Wenyou Yange61ed482017-09-14 11:07:42 +080024#define ATMEL_PMC_UHP (1 << 6)
Bo Shen7ca6f362014-02-09 15:52:39 +080025
Bo Shen7ca6f362014-02-09 15:52:39 +080026/* SDRAM */
27#define CONFIG_NR_DRAM_BANKS 1
Wenyou Yange61ed482017-09-14 11:07:42 +080028#define CONFIG_SYS_SDRAM_BASE 0x20000000
Bo Shen7ca6f362014-02-09 15:52:39 +080029#define CONFIG_SYS_SDRAM_SIZE 0x10000000
30
Bo Shencd23aac42014-03-19 14:48:45 +080031#ifdef CONFIG_SPL_BUILD
Wenyou Yang18788042017-04-14 08:51:45 +080032#define CONFIG_SYS_INIT_SP_ADDR 0x318000
Bo Shencd23aac42014-03-19 14:48:45 +080033#else
Bo Shen7ca6f362014-02-09 15:52:39 +080034#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yang18788042017-04-14 08:51:45 +080035 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Bo Shencd23aac42014-03-19 14:48:45 +080036#endif
Bo Shen7ca6f362014-02-09 15:52:39 +080037
38/* NAND flash */
Bo Shen7ca6f362014-02-09 15:52:39 +080039#ifdef CONFIG_CMD_NAND
40#define CONFIG_NAND_ATMEL
41#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wenyou Yange61ed482017-09-14 11:07:42 +080042#define CONFIG_SYS_NAND_BASE 0x60000000
Bo Shen7ca6f362014-02-09 15:52:39 +080043/* our ALE is AD21 */
44#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
45/* our CLE is AD22 */
46#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
47#define CONFIG_SYS_NAND_ONFI_DETECTION
Tom Rini8f1a80e2017-07-28 21:31:42 -040048
49#define CONFIG_MTD_DEVICE
50#define CONFIG_MTD_PARTITIONS
51#endif
Bo Shen7ca6f362014-02-09 15:52:39 +080052/* PMECC & PMERRLOC */
53#define CONFIG_ATMEL_NAND_HWECC
54#define CONFIG_ATMEL_NAND_HW_PMECC
55#define CONFIG_PMECC_CAP 4
56#define CONFIG_PMECC_SECTOR_SIZE 512
Bo Shen7ca6f362014-02-09 15:52:39 +080057
Bo Shen7ca6f362014-02-09 15:52:39 +080058/* USB */
Bo Shen7ca6f362014-02-09 15:52:39 +080059
60#ifdef CONFIG_CMD_USB
61#define CONFIG_USB_ATMEL
62#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
63#define CONFIG_USB_OHCI_NEW
64#define CONFIG_SYS_USB_OHCI_CPU_INIT
Wenyou Yange61ed482017-09-14 11:07:42 +080065#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000
Bo Shen7ca6f362014-02-09 15:52:39 +080066#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained"
67#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Bo Shen7ca6f362014-02-09 15:52:39 +080068#endif
69
Bo Shen7ca6f362014-02-09 15:52:39 +080070#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
71
Bo Shencd23aac42014-03-19 14:48:45 +080072/* SPL */
Bo Shencd23aac42014-03-19 14:48:45 +080073#define CONFIG_SPL_TEXT_BASE 0x300000
Wenyou Yang18788042017-04-14 08:51:45 +080074#define CONFIG_SPL_MAX_SIZE 0x18000
Bo Shencd23aac42014-03-19 14:48:45 +080075#define CONFIG_SPL_BSS_START_ADDR 0x20000000
76#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
77#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
78#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
79
Bo Shencd23aac42014-03-19 14:48:45 +080080#define CONFIG_SYS_MONITOR_LEN (512 << 10)
81
Wenyou Yang55415432017-09-14 11:07:44 +080082#ifdef CONFIG_SD_BOOT
Paul Kocialkowskie2ccdf82014-11-08 23:14:55 +010083#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
Guillaume GARDET205b4f32014-10-15 17:53:11 +020084#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Bo Shencd23aac42014-03-19 14:48:45 +080085
Wenyou Yang55415432017-09-14 11:07:44 +080086#elif CONFIG_NAND_BOOT
Bo Shencd23aac42014-03-19 14:48:45 +080087#define CONFIG_SPL_NAND_DRIVERS
88#define CONFIG_SPL_NAND_BASE
Wenyou Yang55415432017-09-14 11:07:44 +080089#endif
Bo Shencd23aac42014-03-19 14:48:45 +080090#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
91#define CONFIG_SYS_NAND_5_ADDR_CYCLE
92#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
93#define CONFIG_SYS_NAND_PAGE_COUNT 64
94#define CONFIG_SYS_NAND_OOBSIZE 64
95#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
96#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
Wu, Josh05a4d542014-11-19 19:03:00 +080097#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
Bo Shencd23aac42014-03-19 14:48:45 +080098
99#endif